1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Coresight configuration 4# 5menuconfig CORESIGHT 6 bool "CoreSight Tracing Support" 7 select ARM_AMBA 8 select PERF_EVENTS 9 help 10 This framework provides a kernel interface for the CoreSight debug 11 and trace drivers to register themselves with. It's intended to build 12 a topological view of the CoreSight components based on a DT 13 specification and configure the right series of components when a 14 trace source gets enabled. 15 16if CORESIGHT 17config CORESIGHT_LINKS_AND_SINKS 18 bool "CoreSight Link and Sink drivers" 19 help 20 This enables support for CoreSight link and sink drivers that are 21 responsible for transporting and collecting the trace data 22 respectively. Link and sinks are dynamically aggregated with a trace 23 entity at run time to form a complete trace path. 24 25config CORESIGHT_LINK_AND_SINK_TMC 26 bool "Coresight generic TMC driver" 27 depends on CORESIGHT_LINKS_AND_SINKS 28 help 29 This enables support for the Trace Memory Controller driver. 30 Depending on its configuration the device can act as a link (embedded 31 trace router - ETR) or sink (embedded trace FIFO). The driver 32 complies with the generic implementation of the component without 33 special enhancement or added features. 34 35config CORESIGHT_CATU 36 bool "Coresight Address Translation Unit (CATU) driver" 37 depends on CORESIGHT_LINK_AND_SINK_TMC 38 help 39 Enable support for the Coresight Address Translation Unit (CATU). 40 CATU supports a scatter gather table of 4K pages, with forward/backward 41 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace 42 buffer by translating the addresses used by ETR to the physical address 43 by looking up the provided table. CATU can also be used in pass-through 44 mode where the address is not translated. 45 46config CORESIGHT_SINK_TPIU 47 bool "Coresight generic TPIU driver" 48 depends on CORESIGHT_LINKS_AND_SINKS 49 help 50 This enables support for the Trace Port Interface Unit driver, 51 responsible for bridging the gap between the on-chip coresight 52 components and a trace for bridging the gap between the on-chip 53 coresight components and a trace port collection engine, typically 54 connected to an external host for use case capturing more traces than 55 the on-board coresight memory can handle. 56 57config CORESIGHT_SINK_ETBV10 58 bool "Coresight ETBv1.0 driver" 59 depends on CORESIGHT_LINKS_AND_SINKS 60 help 61 This enables support for the Embedded Trace Buffer version 1.0 driver 62 that complies with the generic implementation of the component without 63 special enhancement or added features. 64 65config CORESIGHT_SOURCE_ETM3X 66 bool "CoreSight Embedded Trace Macrocell 3.x driver" 67 depends on !ARM64 68 select CORESIGHT_LINKS_AND_SINKS 69 help 70 This driver provides support for processor ETM3.x and PTM1.x modules, 71 which allows tracing the instructions that a processor is executing 72 This is primarily useful for instruction level tracing. Depending 73 the ETM version data tracing may also be available. 74 75config CORESIGHT_SOURCE_ETM4X 76 bool "CoreSight Embedded Trace Macrocell 4.x driver" 77 depends on ARM64 78 select CORESIGHT_LINKS_AND_SINKS 79 select PID_IN_CONTEXTIDR 80 help 81 This driver provides support for the ETM4.x tracer module, tracing the 82 instructions that a processor is executing. This is primarily useful 83 for instruction level tracing. Depending on the implemented version 84 data tracing may also be available. 85 86config CORESIGHT_STM 87 bool "CoreSight System Trace Macrocell driver" 88 depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 89 select CORESIGHT_LINKS_AND_SINKS 90 select STM 91 help 92 This driver provides support for hardware assisted software 93 instrumentation based tracing. This is primarily used for 94 logging useful software events or data coming from various entities 95 in the system, possibly running different OSs 96 97config CORESIGHT_CPU_DEBUG 98 tristate "CoreSight CPU Debug driver" 99 depends on ARM || ARM64 100 depends on DEBUG_FS 101 help 102 This driver provides support for coresight debugging module. This 103 is primarily used to dump sample-based profiling registers when 104 system triggers panic, the driver will parse context registers so 105 can quickly get to know program counter (PC), secure state, 106 exception level, etc. Before use debugging functionality, platform 107 needs to ensure the clock domain and power domain are enabled 108 properly, please refer Documentation/trace/coresight-cpu-debug.txt 109 for detailed description and the example for usage. 110 111endif 112