170ba4cc2SSimon Que /* 270ba4cc2SSimon Que * OMAP hardware spinlock driver 370ba4cc2SSimon Que * 470ba4cc2SSimon Que * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com 570ba4cc2SSimon Que * 670ba4cc2SSimon Que * Contact: Simon Que <sque@ti.com> 770ba4cc2SSimon Que * Hari Kanigeri <h-kanigeri2@ti.com> 870ba4cc2SSimon Que * Ohad Ben-Cohen <ohad@wizery.com> 970ba4cc2SSimon Que * 1070ba4cc2SSimon Que * This program is free software; you can redistribute it and/or 1170ba4cc2SSimon Que * modify it under the terms of the GNU General Public License 1270ba4cc2SSimon Que * version 2 as published by the Free Software Foundation. 1370ba4cc2SSimon Que * 1470ba4cc2SSimon Que * This program is distributed in the hope that it will be useful, but 1570ba4cc2SSimon Que * WITHOUT ANY WARRANTY; without even the implied warranty of 1670ba4cc2SSimon Que * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1770ba4cc2SSimon Que * General Public License for more details. 1870ba4cc2SSimon Que */ 1970ba4cc2SSimon Que 2070ba4cc2SSimon Que #include <linux/kernel.h> 2170ba4cc2SSimon Que #include <linux/module.h> 2270ba4cc2SSimon Que #include <linux/device.h> 2370ba4cc2SSimon Que #include <linux/delay.h> 2470ba4cc2SSimon Que #include <linux/io.h> 2570ba4cc2SSimon Que #include <linux/bitops.h> 2670ba4cc2SSimon Que #include <linux/pm_runtime.h> 2770ba4cc2SSimon Que #include <linux/slab.h> 2870ba4cc2SSimon Que #include <linux/spinlock.h> 2970ba4cc2SSimon Que #include <linux/hwspinlock.h> 3070ba4cc2SSimon Que #include <linux/platform_device.h> 3170ba4cc2SSimon Que 3270ba4cc2SSimon Que #include "hwspinlock_internal.h" 3370ba4cc2SSimon Que 3470ba4cc2SSimon Que /* Spinlock register offsets */ 3570ba4cc2SSimon Que #define SYSSTATUS_OFFSET 0x0014 3670ba4cc2SSimon Que #define LOCK_BASE_OFFSET 0x0800 3770ba4cc2SSimon Que 3870ba4cc2SSimon Que #define SPINLOCK_NUMLOCKS_BIT_OFFSET (24) 3970ba4cc2SSimon Que 4070ba4cc2SSimon Que /* Possible values of SPINLOCK_LOCK_REG */ 4170ba4cc2SSimon Que #define SPINLOCK_NOTTAKEN (0) /* free */ 4270ba4cc2SSimon Que #define SPINLOCK_TAKEN (1) /* locked */ 4370ba4cc2SSimon Que 4470ba4cc2SSimon Que #define to_omap_hwspinlock(lock) \ 4570ba4cc2SSimon Que container_of(lock, struct omap_hwspinlock, lock) 4670ba4cc2SSimon Que 4770ba4cc2SSimon Que struct omap_hwspinlock { 4870ba4cc2SSimon Que struct hwspinlock lock; 4970ba4cc2SSimon Que void __iomem *addr; 5070ba4cc2SSimon Que }; 5170ba4cc2SSimon Que 5270ba4cc2SSimon Que struct omap_hwspinlock_state { 5370ba4cc2SSimon Que int num_locks; /* Total number of locks in system */ 5470ba4cc2SSimon Que void __iomem *io_base; /* Mapped base address */ 55c97f6dd0SOhad Ben-Cohen struct omap_hwspinlock lock[0]; /* Array of 'num_locks' locks */ 5670ba4cc2SSimon Que }; 5770ba4cc2SSimon Que 5870ba4cc2SSimon Que static int omap_hwspinlock_trylock(struct hwspinlock *lock) 5970ba4cc2SSimon Que { 6070ba4cc2SSimon Que struct omap_hwspinlock *omap_lock = to_omap_hwspinlock(lock); 6170ba4cc2SSimon Que 6270ba4cc2SSimon Que /* attempt to acquire the lock by reading its value */ 6370ba4cc2SSimon Que return (SPINLOCK_NOTTAKEN == readl(omap_lock->addr)); 6470ba4cc2SSimon Que } 6570ba4cc2SSimon Que 6670ba4cc2SSimon Que static void omap_hwspinlock_unlock(struct hwspinlock *lock) 6770ba4cc2SSimon Que { 6870ba4cc2SSimon Que struct omap_hwspinlock *omap_lock = to_omap_hwspinlock(lock); 6970ba4cc2SSimon Que 7070ba4cc2SSimon Que /* release the lock by writing 0 to it */ 7170ba4cc2SSimon Que writel(SPINLOCK_NOTTAKEN, omap_lock->addr); 7270ba4cc2SSimon Que } 7370ba4cc2SSimon Que 7470ba4cc2SSimon Que /* 7570ba4cc2SSimon Que * relax the OMAP interconnect while spinning on it. 7670ba4cc2SSimon Que * 7770ba4cc2SSimon Que * The specs recommended that the retry delay time will be 7870ba4cc2SSimon Que * just over half of the time that a requester would be 7970ba4cc2SSimon Que * expected to hold the lock. 8070ba4cc2SSimon Que * 8170ba4cc2SSimon Que * The number below is taken from an hardware specs example, 8270ba4cc2SSimon Que * obviously it is somewhat arbitrary. 8370ba4cc2SSimon Que */ 8470ba4cc2SSimon Que static void omap_hwspinlock_relax(struct hwspinlock *lock) 8570ba4cc2SSimon Que { 8670ba4cc2SSimon Que ndelay(50); 8770ba4cc2SSimon Que } 8870ba4cc2SSimon Que 8970ba4cc2SSimon Que static const struct hwspinlock_ops omap_hwspinlock_ops = { 9070ba4cc2SSimon Que .trylock = omap_hwspinlock_trylock, 9170ba4cc2SSimon Que .unlock = omap_hwspinlock_unlock, 9270ba4cc2SSimon Que .relax = omap_hwspinlock_relax, 9370ba4cc2SSimon Que }; 9470ba4cc2SSimon Que 9570ba4cc2SSimon Que static int __devinit omap_hwspinlock_probe(struct platform_device *pdev) 9670ba4cc2SSimon Que { 97c3c1250eSOhad Ben-Cohen struct hwspinlock_pdata *pdata = pdev->dev.platform_data; 9870ba4cc2SSimon Que struct omap_hwspinlock *omap_lock; 9970ba4cc2SSimon Que struct omap_hwspinlock_state *state; 10070ba4cc2SSimon Que struct resource *res; 10170ba4cc2SSimon Que void __iomem *io_base; 10270ba4cc2SSimon Que int i, ret; 10370ba4cc2SSimon Que 104c3c1250eSOhad Ben-Cohen if (!pdata) 105c3c1250eSOhad Ben-Cohen return -ENODEV; 106c3c1250eSOhad Ben-Cohen 10770ba4cc2SSimon Que res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 10870ba4cc2SSimon Que if (!res) 10970ba4cc2SSimon Que return -ENODEV; 11070ba4cc2SSimon Que 11170ba4cc2SSimon Que io_base = ioremap(res->start, resource_size(res)); 112c97f6dd0SOhad Ben-Cohen if (!io_base) 113c97f6dd0SOhad Ben-Cohen return -ENOMEM; 11470ba4cc2SSimon Que 11570ba4cc2SSimon Que /* Determine number of locks */ 11670ba4cc2SSimon Que i = readl(io_base + SYSSTATUS_OFFSET); 11770ba4cc2SSimon Que i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET; 11870ba4cc2SSimon Que 11970ba4cc2SSimon Que /* one of the four lsb's must be set, and nothing else */ 12070ba4cc2SSimon Que if (hweight_long(i & 0xf) != 1 || i > 8) { 12170ba4cc2SSimon Que ret = -EINVAL; 12270ba4cc2SSimon Que goto iounmap_base; 12370ba4cc2SSimon Que } 12470ba4cc2SSimon Que 125c97f6dd0SOhad Ben-Cohen i *= 32; /* actual number of locks in this device */ 126c97f6dd0SOhad Ben-Cohen 127c97f6dd0SOhad Ben-Cohen state = kzalloc(sizeof(*state) + i * sizeof(*omap_lock), GFP_KERNEL); 128c97f6dd0SOhad Ben-Cohen if (!state) { 129c97f6dd0SOhad Ben-Cohen ret = -ENOMEM; 130c97f6dd0SOhad Ben-Cohen goto iounmap_base; 131c97f6dd0SOhad Ben-Cohen } 132c97f6dd0SOhad Ben-Cohen 133c97f6dd0SOhad Ben-Cohen state->num_locks = i; 13470ba4cc2SSimon Que state->io_base = io_base; 13570ba4cc2SSimon Que 13670ba4cc2SSimon Que platform_set_drvdata(pdev, state); 13770ba4cc2SSimon Que 13870ba4cc2SSimon Que /* 13970ba4cc2SSimon Que * runtime PM will make sure the clock of this module is 14070ba4cc2SSimon Que * enabled iff at least one lock is requested 14170ba4cc2SSimon Que */ 14270ba4cc2SSimon Que pm_runtime_enable(&pdev->dev); 14370ba4cc2SSimon Que 14470ba4cc2SSimon Que for (i = 0; i < state->num_locks; i++) { 145c97f6dd0SOhad Ben-Cohen omap_lock = &state->lock[i]; 14670ba4cc2SSimon Que 14770ba4cc2SSimon Que omap_lock->lock.dev = &pdev->dev; 148c3c1250eSOhad Ben-Cohen omap_lock->lock.id = pdata->base_id + i; 14970ba4cc2SSimon Que omap_lock->lock.ops = &omap_hwspinlock_ops; 15070ba4cc2SSimon Que omap_lock->addr = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i; 15170ba4cc2SSimon Que 15270ba4cc2SSimon Que ret = hwspin_lock_register(&omap_lock->lock); 153c97f6dd0SOhad Ben-Cohen if (ret) 15470ba4cc2SSimon Que goto free_locks; 15570ba4cc2SSimon Que } 15670ba4cc2SSimon Que 15770ba4cc2SSimon Que return 0; 15870ba4cc2SSimon Que 15970ba4cc2SSimon Que free_locks: 160c97f6dd0SOhad Ben-Cohen while (--i >= 0) 161c97f6dd0SOhad Ben-Cohen hwspin_lock_unregister(i); 16270ba4cc2SSimon Que pm_runtime_disable(&pdev->dev); 163c97f6dd0SOhad Ben-Cohen kfree(state); 16470ba4cc2SSimon Que iounmap_base: 16570ba4cc2SSimon Que iounmap(io_base); 16670ba4cc2SSimon Que return ret; 16770ba4cc2SSimon Que } 16870ba4cc2SSimon Que 16970ba4cc2SSimon Que static int omap_hwspinlock_remove(struct platform_device *pdev) 17070ba4cc2SSimon Que { 17170ba4cc2SSimon Que struct omap_hwspinlock_state *state = platform_get_drvdata(pdev); 17270ba4cc2SSimon Que struct hwspinlock *lock; 17370ba4cc2SSimon Que int i; 17470ba4cc2SSimon Que 17570ba4cc2SSimon Que for (i = 0; i < state->num_locks; i++) { 17670ba4cc2SSimon Que lock = hwspin_lock_unregister(i); 17770ba4cc2SSimon Que /* this shouldn't happen at this point. if it does, at least 17870ba4cc2SSimon Que * don't continue with the remove */ 17970ba4cc2SSimon Que if (!lock) { 18070ba4cc2SSimon Que dev_err(&pdev->dev, "%s: failed on %d\n", __func__, i); 18170ba4cc2SSimon Que return -EBUSY; 18270ba4cc2SSimon Que } 18370ba4cc2SSimon Que } 18470ba4cc2SSimon Que 18570ba4cc2SSimon Que pm_runtime_disable(&pdev->dev); 18670ba4cc2SSimon Que iounmap(state->io_base); 18770ba4cc2SSimon Que kfree(state); 18870ba4cc2SSimon Que 18970ba4cc2SSimon Que return 0; 19070ba4cc2SSimon Que } 19170ba4cc2SSimon Que 19270ba4cc2SSimon Que static struct platform_driver omap_hwspinlock_driver = { 19370ba4cc2SSimon Que .probe = omap_hwspinlock_probe, 19470ba4cc2SSimon Que .remove = omap_hwspinlock_remove, 19570ba4cc2SSimon Que .driver = { 19670ba4cc2SSimon Que .name = "omap_hwspinlock", 197e467b642SOhad Ben-Cohen .owner = THIS_MODULE, 19870ba4cc2SSimon Que }, 19970ba4cc2SSimon Que }; 20070ba4cc2SSimon Que 20170ba4cc2SSimon Que static int __init omap_hwspinlock_init(void) 20270ba4cc2SSimon Que { 20370ba4cc2SSimon Que return platform_driver_register(&omap_hwspinlock_driver); 20470ba4cc2SSimon Que } 20570ba4cc2SSimon Que /* board init code might need to reserve hwspinlocks for predefined purposes */ 20670ba4cc2SSimon Que postcore_initcall(omap_hwspinlock_init); 20770ba4cc2SSimon Que 20870ba4cc2SSimon Que static void __exit omap_hwspinlock_exit(void) 20970ba4cc2SSimon Que { 21070ba4cc2SSimon Que platform_driver_unregister(&omap_hwspinlock_driver); 21170ba4cc2SSimon Que } 21270ba4cc2SSimon Que module_exit(omap_hwspinlock_exit); 21370ba4cc2SSimon Que 21470ba4cc2SSimon Que MODULE_LICENSE("GPL v2"); 21570ba4cc2SSimon Que MODULE_DESCRIPTION("Hardware spinlock driver for OMAP"); 21670ba4cc2SSimon Que MODULE_AUTHOR("Simon Que <sque@ti.com>"); 21770ba4cc2SSimon Que MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>"); 21870ba4cc2SSimon Que MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>"); 219