1357ace03SSuman Anna // SPDX-License-Identifier: GPL-2.0 270ba4cc2SSimon Que /* 370ba4cc2SSimon Que * OMAP hardware spinlock driver 470ba4cc2SSimon Que * 5*b9ddb250SSuman Anna * Copyright (C) 2010-2021 Texas Instruments Incorporated - https://www.ti.com 670ba4cc2SSimon Que * 770ba4cc2SSimon Que * Contact: Simon Que <sque@ti.com> 870ba4cc2SSimon Que * Hari Kanigeri <h-kanigeri2@ti.com> 970ba4cc2SSimon Que * Ohad Ben-Cohen <ohad@wizery.com> 10*b9ddb250SSuman Anna * Suman Anna <s-anna@ti.com> 1170ba4cc2SSimon Que */ 1270ba4cc2SSimon Que 1370ba4cc2SSimon Que #include <linux/kernel.h> 1470ba4cc2SSimon Que #include <linux/module.h> 1570ba4cc2SSimon Que #include <linux/device.h> 1670ba4cc2SSimon Que #include <linux/delay.h> 1770ba4cc2SSimon Que #include <linux/io.h> 1870ba4cc2SSimon Que #include <linux/bitops.h> 1970ba4cc2SSimon Que #include <linux/pm_runtime.h> 2070ba4cc2SSimon Que #include <linux/slab.h> 2170ba4cc2SSimon Que #include <linux/spinlock.h> 2270ba4cc2SSimon Que #include <linux/hwspinlock.h> 2365bd4341SSuman Anna #include <linux/of.h> 2470ba4cc2SSimon Que #include <linux/platform_device.h> 2570ba4cc2SSimon Que 2670ba4cc2SSimon Que #include "hwspinlock_internal.h" 2770ba4cc2SSimon Que 2870ba4cc2SSimon Que /* Spinlock register offsets */ 2970ba4cc2SSimon Que #define SYSSTATUS_OFFSET 0x0014 3070ba4cc2SSimon Que #define LOCK_BASE_OFFSET 0x0800 3170ba4cc2SSimon Que 3270ba4cc2SSimon Que #define SPINLOCK_NUMLOCKS_BIT_OFFSET (24) 3370ba4cc2SSimon Que 3470ba4cc2SSimon Que /* Possible values of SPINLOCK_LOCK_REG */ 3570ba4cc2SSimon Que #define SPINLOCK_NOTTAKEN (0) /* free */ 3670ba4cc2SSimon Que #define SPINLOCK_TAKEN (1) /* locked */ 3770ba4cc2SSimon Que 3870ba4cc2SSimon Que static int omap_hwspinlock_trylock(struct hwspinlock *lock) 3970ba4cc2SSimon Que { 40300bab97SOhad Ben-Cohen void __iomem *lock_addr = lock->priv; 4170ba4cc2SSimon Que 4270ba4cc2SSimon Que /* attempt to acquire the lock by reading its value */ 43300bab97SOhad Ben-Cohen return (SPINLOCK_NOTTAKEN == readl(lock_addr)); 4470ba4cc2SSimon Que } 4570ba4cc2SSimon Que 4670ba4cc2SSimon Que static void omap_hwspinlock_unlock(struct hwspinlock *lock) 4770ba4cc2SSimon Que { 48300bab97SOhad Ben-Cohen void __iomem *lock_addr = lock->priv; 4970ba4cc2SSimon Que 5070ba4cc2SSimon Que /* release the lock by writing 0 to it */ 51300bab97SOhad Ben-Cohen writel(SPINLOCK_NOTTAKEN, lock_addr); 5270ba4cc2SSimon Que } 5370ba4cc2SSimon Que 5470ba4cc2SSimon Que /* 5570ba4cc2SSimon Que * relax the OMAP interconnect while spinning on it. 5670ba4cc2SSimon Que * 5770ba4cc2SSimon Que * The specs recommended that the retry delay time will be 5870ba4cc2SSimon Que * just over half of the time that a requester would be 5970ba4cc2SSimon Que * expected to hold the lock. 6070ba4cc2SSimon Que * 6170ba4cc2SSimon Que * The number below is taken from an hardware specs example, 6270ba4cc2SSimon Que * obviously it is somewhat arbitrary. 6370ba4cc2SSimon Que */ 6470ba4cc2SSimon Que static void omap_hwspinlock_relax(struct hwspinlock *lock) 6570ba4cc2SSimon Que { 6670ba4cc2SSimon Que ndelay(50); 6770ba4cc2SSimon Que } 6870ba4cc2SSimon Que 6970ba4cc2SSimon Que static const struct hwspinlock_ops omap_hwspinlock_ops = { 7070ba4cc2SSimon Que .trylock = omap_hwspinlock_trylock, 7170ba4cc2SSimon Que .unlock = omap_hwspinlock_unlock, 7270ba4cc2SSimon Que .relax = omap_hwspinlock_relax, 7370ba4cc2SSimon Que }; 7470ba4cc2SSimon Que 7557129106SBill Pemberton static int omap_hwspinlock_probe(struct platform_device *pdev) 7670ba4cc2SSimon Que { 7765bd4341SSuman Anna struct device_node *node = pdev->dev.of_node; 78300bab97SOhad Ben-Cohen struct hwspinlock_device *bank; 79300bab97SOhad Ben-Cohen struct hwspinlock *hwlock; 8070ba4cc2SSimon Que void __iomem *io_base; 81300bab97SOhad Ben-Cohen int num_locks, i, ret; 8265bd4341SSuman Anna /* Only a single hwspinlock block device is supported */ 8365bd4341SSuman Anna int base_id = 0; 8470ba4cc2SSimon Que 8565bd4341SSuman Anna if (!node) 86c3c1250eSOhad Ben-Cohen return -ENODEV; 87c3c1250eSOhad Ben-Cohen 88bf274006SBaolin Wang io_base = devm_platform_ioremap_resource(pdev, 0); 89bf274006SBaolin Wang if (IS_ERR(io_base)) 90bf274006SBaolin Wang return PTR_ERR(io_base); 9170ba4cc2SSimon Que 92e1e4528fSSuman Anna /* 93e1e4528fSSuman Anna * make sure the module is enabled and clocked before reading 94e1e4528fSSuman Anna * the module SYSSTATUS register 95e1e4528fSSuman Anna */ 96e1e4528fSSuman Anna pm_runtime_enable(&pdev->dev); 97e1e4528fSSuman Anna ret = pm_runtime_get_sync(&pdev->dev); 98e1e4528fSSuman Anna if (ret < 0) { 99e1e4528fSSuman Anna pm_runtime_put_noidle(&pdev->dev); 100bf274006SBaolin Wang goto runtime_err; 101e1e4528fSSuman Anna } 102e1e4528fSSuman Anna 10370ba4cc2SSimon Que /* Determine number of locks */ 10470ba4cc2SSimon Que i = readl(io_base + SYSSTATUS_OFFSET); 10570ba4cc2SSimon Que i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET; 10670ba4cc2SSimon Que 107e1e4528fSSuman Anna /* 108e1e4528fSSuman Anna * runtime PM will make sure the clock of this module is 109e1e4528fSSuman Anna * enabled again iff at least one lock is requested 110e1e4528fSSuman Anna */ 111e1e4528fSSuman Anna ret = pm_runtime_put(&pdev->dev); 112e1e4528fSSuman Anna if (ret < 0) 113bf274006SBaolin Wang goto runtime_err; 114e1e4528fSSuman Anna 11570ba4cc2SSimon Que /* one of the four lsb's must be set, and nothing else */ 11670ba4cc2SSimon Que if (hweight_long(i & 0xf) != 1 || i > 8) { 11770ba4cc2SSimon Que ret = -EINVAL; 118bf274006SBaolin Wang goto runtime_err; 11970ba4cc2SSimon Que } 12070ba4cc2SSimon Que 121300bab97SOhad Ben-Cohen num_locks = i * 32; /* actual number of locks in this device */ 122c97f6dd0SOhad Ben-Cohen 12342f291ebSBaolin Wang bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks), 12442f291ebSBaolin Wang GFP_KERNEL); 125300bab97SOhad Ben-Cohen if (!bank) { 126c97f6dd0SOhad Ben-Cohen ret = -ENOMEM; 127bf274006SBaolin Wang goto runtime_err; 128c97f6dd0SOhad Ben-Cohen } 129c97f6dd0SOhad Ben-Cohen 130300bab97SOhad Ben-Cohen platform_set_drvdata(pdev, bank); 13170ba4cc2SSimon Que 132300bab97SOhad Ben-Cohen for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++) 133300bab97SOhad Ben-Cohen hwlock->priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i; 13470ba4cc2SSimon Que 135300bab97SOhad Ben-Cohen ret = hwspin_lock_register(bank, &pdev->dev, &omap_hwspinlock_ops, 13665bd4341SSuman Anna base_id, num_locks); 137c97f6dd0SOhad Ben-Cohen if (ret) 13842f291ebSBaolin Wang goto runtime_err; 13970ba4cc2SSimon Que 140d4d98bbaSSuman Anna dev_dbg(&pdev->dev, "Registered %d locks with HwSpinlock core\n", 141d4d98bbaSSuman Anna num_locks); 142d4d98bbaSSuman Anna 14370ba4cc2SSimon Que return 0; 14470ba4cc2SSimon Que 145bf274006SBaolin Wang runtime_err: 146e1e4528fSSuman Anna pm_runtime_disable(&pdev->dev); 14770ba4cc2SSimon Que return ret; 14870ba4cc2SSimon Que } 14970ba4cc2SSimon Que 150e533a349SBill Pemberton static int omap_hwspinlock_remove(struct platform_device *pdev) 15170ba4cc2SSimon Que { 152300bab97SOhad Ben-Cohen struct hwspinlock_device *bank = platform_get_drvdata(pdev); 153300bab97SOhad Ben-Cohen int ret; 15470ba4cc2SSimon Que 155300bab97SOhad Ben-Cohen ret = hwspin_lock_unregister(bank); 156300bab97SOhad Ben-Cohen if (ret) { 157300bab97SOhad Ben-Cohen dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); 158300bab97SOhad Ben-Cohen return ret; 15970ba4cc2SSimon Que } 16070ba4cc2SSimon Que 16170ba4cc2SSimon Que pm_runtime_disable(&pdev->dev); 16270ba4cc2SSimon Que 16370ba4cc2SSimon Que return 0; 16470ba4cc2SSimon Que } 16570ba4cc2SSimon Que 16665bd4341SSuman Anna static const struct of_device_id omap_hwspinlock_of_match[] = { 16765bd4341SSuman Anna { .compatible = "ti,omap4-hwspinlock", }, 168*b9ddb250SSuman Anna { .compatible = "ti,am64-hwspinlock", }, 1696fa154e2SSuman Anna { .compatible = "ti,am654-hwspinlock", }, 17065bd4341SSuman Anna { /* end */ }, 17165bd4341SSuman Anna }; 17265bd4341SSuman Anna MODULE_DEVICE_TABLE(of, omap_hwspinlock_of_match); 17365bd4341SSuman Anna 17470ba4cc2SSimon Que static struct platform_driver omap_hwspinlock_driver = { 17570ba4cc2SSimon Que .probe = omap_hwspinlock_probe, 1769eb26bddSBill Pemberton .remove = omap_hwspinlock_remove, 17770ba4cc2SSimon Que .driver = { 17870ba4cc2SSimon Que .name = "omap_hwspinlock", 17965bd4341SSuman Anna .of_match_table = of_match_ptr(omap_hwspinlock_of_match), 18070ba4cc2SSimon Que }, 18170ba4cc2SSimon Que }; 18270ba4cc2SSimon Que 18370ba4cc2SSimon Que static int __init omap_hwspinlock_init(void) 18470ba4cc2SSimon Que { 18570ba4cc2SSimon Que return platform_driver_register(&omap_hwspinlock_driver); 18670ba4cc2SSimon Que } 18770ba4cc2SSimon Que /* board init code might need to reserve hwspinlocks for predefined purposes */ 18870ba4cc2SSimon Que postcore_initcall(omap_hwspinlock_init); 18970ba4cc2SSimon Que 19070ba4cc2SSimon Que static void __exit omap_hwspinlock_exit(void) 19170ba4cc2SSimon Que { 19270ba4cc2SSimon Que platform_driver_unregister(&omap_hwspinlock_driver); 19370ba4cc2SSimon Que } 19470ba4cc2SSimon Que module_exit(omap_hwspinlock_exit); 19570ba4cc2SSimon Que 19670ba4cc2SSimon Que MODULE_LICENSE("GPL v2"); 19770ba4cc2SSimon Que MODULE_DESCRIPTION("Hardware spinlock driver for OMAP"); 19870ba4cc2SSimon Que MODULE_AUTHOR("Simon Que <sque@ti.com>"); 19970ba4cc2SSimon Que MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>"); 20070ba4cc2SSimon Que MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>"); 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