1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * pmbus.h - Common defines and structures for PMBus devices 4 * 5 * Copyright (c) 2010, 2011 Ericsson AB. 6 * Copyright (c) 2012 Guenter Roeck 7 */ 8 9 #ifndef PMBUS_H 10 #define PMBUS_H 11 12 #include <linux/bitops.h> 13 #include <linux/regulator/driver.h> 14 15 /* 16 * Registers 17 */ 18 enum pmbus_regs { 19 PMBUS_PAGE = 0x00, 20 PMBUS_OPERATION = 0x01, 21 PMBUS_ON_OFF_CONFIG = 0x02, 22 PMBUS_CLEAR_FAULTS = 0x03, 23 PMBUS_PHASE = 0x04, 24 25 PMBUS_WRITE_PROTECT = 0x10, 26 27 PMBUS_CAPABILITY = 0x19, 28 PMBUS_QUERY = 0x1A, 29 30 PMBUS_VOUT_MODE = 0x20, 31 PMBUS_VOUT_COMMAND = 0x21, 32 PMBUS_VOUT_TRIM = 0x22, 33 PMBUS_VOUT_CAL_OFFSET = 0x23, 34 PMBUS_VOUT_MAX = 0x24, 35 PMBUS_VOUT_MARGIN_HIGH = 0x25, 36 PMBUS_VOUT_MARGIN_LOW = 0x26, 37 PMBUS_VOUT_TRANSITION_RATE = 0x27, 38 PMBUS_VOUT_DROOP = 0x28, 39 PMBUS_VOUT_SCALE_LOOP = 0x29, 40 PMBUS_VOUT_SCALE_MONITOR = 0x2A, 41 42 PMBUS_COEFFICIENTS = 0x30, 43 PMBUS_POUT_MAX = 0x31, 44 45 PMBUS_FAN_CONFIG_12 = 0x3A, 46 PMBUS_FAN_COMMAND_1 = 0x3B, 47 PMBUS_FAN_COMMAND_2 = 0x3C, 48 PMBUS_FAN_CONFIG_34 = 0x3D, 49 PMBUS_FAN_COMMAND_3 = 0x3E, 50 PMBUS_FAN_COMMAND_4 = 0x3F, 51 52 PMBUS_VOUT_OV_FAULT_LIMIT = 0x40, 53 PMBUS_VOUT_OV_FAULT_RESPONSE = 0x41, 54 PMBUS_VOUT_OV_WARN_LIMIT = 0x42, 55 PMBUS_VOUT_UV_WARN_LIMIT = 0x43, 56 PMBUS_VOUT_UV_FAULT_LIMIT = 0x44, 57 PMBUS_VOUT_UV_FAULT_RESPONSE = 0x45, 58 PMBUS_IOUT_OC_FAULT_LIMIT = 0x46, 59 PMBUS_IOUT_OC_FAULT_RESPONSE = 0x47, 60 PMBUS_IOUT_OC_LV_FAULT_LIMIT = 0x48, 61 PMBUS_IOUT_OC_LV_FAULT_RESPONSE = 0x49, 62 PMBUS_IOUT_OC_WARN_LIMIT = 0x4A, 63 PMBUS_IOUT_UC_FAULT_LIMIT = 0x4B, 64 PMBUS_IOUT_UC_FAULT_RESPONSE = 0x4C, 65 66 PMBUS_OT_FAULT_LIMIT = 0x4F, 67 PMBUS_OT_FAULT_RESPONSE = 0x50, 68 PMBUS_OT_WARN_LIMIT = 0x51, 69 PMBUS_UT_WARN_LIMIT = 0x52, 70 PMBUS_UT_FAULT_LIMIT = 0x53, 71 PMBUS_UT_FAULT_RESPONSE = 0x54, 72 PMBUS_VIN_OV_FAULT_LIMIT = 0x55, 73 PMBUS_VIN_OV_FAULT_RESPONSE = 0x56, 74 PMBUS_VIN_OV_WARN_LIMIT = 0x57, 75 PMBUS_VIN_UV_WARN_LIMIT = 0x58, 76 PMBUS_VIN_UV_FAULT_LIMIT = 0x59, 77 78 PMBUS_IIN_OC_FAULT_LIMIT = 0x5B, 79 PMBUS_IIN_OC_WARN_LIMIT = 0x5D, 80 81 PMBUS_POUT_OP_FAULT_LIMIT = 0x68, 82 PMBUS_POUT_OP_WARN_LIMIT = 0x6A, 83 PMBUS_PIN_OP_WARN_LIMIT = 0x6B, 84 85 PMBUS_STATUS_BYTE = 0x78, 86 PMBUS_STATUS_WORD = 0x79, 87 PMBUS_STATUS_VOUT = 0x7A, 88 PMBUS_STATUS_IOUT = 0x7B, 89 PMBUS_STATUS_INPUT = 0x7C, 90 PMBUS_STATUS_TEMPERATURE = 0x7D, 91 PMBUS_STATUS_CML = 0x7E, 92 PMBUS_STATUS_OTHER = 0x7F, 93 PMBUS_STATUS_MFR_SPECIFIC = 0x80, 94 PMBUS_STATUS_FAN_12 = 0x81, 95 PMBUS_STATUS_FAN_34 = 0x82, 96 97 PMBUS_READ_VIN = 0x88, 98 PMBUS_READ_IIN = 0x89, 99 PMBUS_READ_VCAP = 0x8A, 100 PMBUS_READ_VOUT = 0x8B, 101 PMBUS_READ_IOUT = 0x8C, 102 PMBUS_READ_TEMPERATURE_1 = 0x8D, 103 PMBUS_READ_TEMPERATURE_2 = 0x8E, 104 PMBUS_READ_TEMPERATURE_3 = 0x8F, 105 PMBUS_READ_FAN_SPEED_1 = 0x90, 106 PMBUS_READ_FAN_SPEED_2 = 0x91, 107 PMBUS_READ_FAN_SPEED_3 = 0x92, 108 PMBUS_READ_FAN_SPEED_4 = 0x93, 109 PMBUS_READ_DUTY_CYCLE = 0x94, 110 PMBUS_READ_FREQUENCY = 0x95, 111 PMBUS_READ_POUT = 0x96, 112 PMBUS_READ_PIN = 0x97, 113 114 PMBUS_REVISION = 0x98, 115 PMBUS_MFR_ID = 0x99, 116 PMBUS_MFR_MODEL = 0x9A, 117 PMBUS_MFR_REVISION = 0x9B, 118 PMBUS_MFR_LOCATION = 0x9C, 119 PMBUS_MFR_DATE = 0x9D, 120 PMBUS_MFR_SERIAL = 0x9E, 121 122 PMBUS_IC_DEVICE_ID = 0xAD, 123 PMBUS_IC_DEVICE_REV = 0xAE, 124 125 /* 126 * Virtual registers. 127 * Useful to support attributes which are not supported by standard PMBus 128 * registers but exist as manufacturer specific registers on individual chips. 129 * Must be mapped to real registers in device specific code. 130 * 131 * Semantics: 132 * Virtual registers are all word size. 133 * READ registers are read-only; writes are either ignored or return an error. 134 * RESET registers are read/write. Reading reset registers returns zero 135 * (used for detection), writing any value causes the associated history to be 136 * reset. 137 * Virtual registers have to be handled in device specific driver code. Chip 138 * driver code returns non-negative register values if a virtual register is 139 * supported, or a negative error code if not. The chip driver may return 140 * -ENODATA or any other error code in this case, though an error code other 141 * than -ENODATA is handled more efficiently and thus preferred. Either case, 142 * the calling PMBus core code will abort if the chip driver returns an error 143 * code when reading or writing virtual registers. 144 */ 145 PMBUS_VIRT_BASE = 0x100, 146 PMBUS_VIRT_READ_TEMP_AVG, 147 PMBUS_VIRT_READ_TEMP_MIN, 148 PMBUS_VIRT_READ_TEMP_MAX, 149 PMBUS_VIRT_RESET_TEMP_HISTORY, 150 PMBUS_VIRT_READ_VIN_AVG, 151 PMBUS_VIRT_READ_VIN_MIN, 152 PMBUS_VIRT_READ_VIN_MAX, 153 PMBUS_VIRT_RESET_VIN_HISTORY, 154 PMBUS_VIRT_READ_IIN_AVG, 155 PMBUS_VIRT_READ_IIN_MIN, 156 PMBUS_VIRT_READ_IIN_MAX, 157 PMBUS_VIRT_RESET_IIN_HISTORY, 158 PMBUS_VIRT_READ_PIN_AVG, 159 PMBUS_VIRT_READ_PIN_MIN, 160 PMBUS_VIRT_READ_PIN_MAX, 161 PMBUS_VIRT_RESET_PIN_HISTORY, 162 PMBUS_VIRT_READ_POUT_AVG, 163 PMBUS_VIRT_READ_POUT_MIN, 164 PMBUS_VIRT_READ_POUT_MAX, 165 PMBUS_VIRT_RESET_POUT_HISTORY, 166 PMBUS_VIRT_READ_VOUT_AVG, 167 PMBUS_VIRT_READ_VOUT_MIN, 168 PMBUS_VIRT_READ_VOUT_MAX, 169 PMBUS_VIRT_RESET_VOUT_HISTORY, 170 PMBUS_VIRT_READ_IOUT_AVG, 171 PMBUS_VIRT_READ_IOUT_MIN, 172 PMBUS_VIRT_READ_IOUT_MAX, 173 PMBUS_VIRT_RESET_IOUT_HISTORY, 174 PMBUS_VIRT_READ_TEMP2_AVG, 175 PMBUS_VIRT_READ_TEMP2_MIN, 176 PMBUS_VIRT_READ_TEMP2_MAX, 177 PMBUS_VIRT_RESET_TEMP2_HISTORY, 178 179 PMBUS_VIRT_READ_VMON, 180 PMBUS_VIRT_VMON_UV_WARN_LIMIT, 181 PMBUS_VIRT_VMON_OV_WARN_LIMIT, 182 PMBUS_VIRT_VMON_UV_FAULT_LIMIT, 183 PMBUS_VIRT_VMON_OV_FAULT_LIMIT, 184 PMBUS_VIRT_STATUS_VMON, 185 186 /* 187 * RPM and PWM Fan control 188 * 189 * Drivers wanting to expose PWM control must define the behaviour of 190 * PMBUS_VIRT_PWM_[1-4] and PMBUS_VIRT_PWM_ENABLE_[1-4] in the 191 * {read,write}_word_data callback. 192 * 193 * pmbus core provides a default implementation for 194 * PMBUS_VIRT_FAN_TARGET_[1-4]. 195 * 196 * TARGET, PWM and PWM_ENABLE members must be defined sequentially; 197 * pmbus core uses the difference between the provided register and 198 * it's _1 counterpart to calculate the FAN/PWM ID. 199 */ 200 PMBUS_VIRT_FAN_TARGET_1, 201 PMBUS_VIRT_FAN_TARGET_2, 202 PMBUS_VIRT_FAN_TARGET_3, 203 PMBUS_VIRT_FAN_TARGET_4, 204 PMBUS_VIRT_PWM_1, 205 PMBUS_VIRT_PWM_2, 206 PMBUS_VIRT_PWM_3, 207 PMBUS_VIRT_PWM_4, 208 PMBUS_VIRT_PWM_ENABLE_1, 209 PMBUS_VIRT_PWM_ENABLE_2, 210 PMBUS_VIRT_PWM_ENABLE_3, 211 PMBUS_VIRT_PWM_ENABLE_4, 212 213 /* Samples for average 214 * 215 * Drivers wanting to expose functionality for changing the number of 216 * samples used for average values should implement support in 217 * {read,write}_word_data callback for either PMBUS_VIRT_SAMPLES if it 218 * applies to all types of measurements, or any number of specific 219 * PMBUS_VIRT_*_SAMPLES registers to allow for individual control. 220 */ 221 PMBUS_VIRT_SAMPLES, 222 PMBUS_VIRT_IN_SAMPLES, 223 PMBUS_VIRT_CURR_SAMPLES, 224 PMBUS_VIRT_POWER_SAMPLES, 225 PMBUS_VIRT_TEMP_SAMPLES, 226 }; 227 228 /* 229 * OPERATION 230 */ 231 #define PB_OPERATION_CONTROL_ON BIT(7) 232 233 /* 234 * WRITE_PROTECT 235 */ 236 #define PB_WP_ALL BIT(7) /* all but WRITE_PROTECT */ 237 #define PB_WP_OP BIT(6) /* all but WP, OPERATION, PAGE */ 238 #define PB_WP_VOUT BIT(5) /* all but WP, OPERATION, PAGE, VOUT, ON_OFF */ 239 240 #define PB_WP_ANY (PB_WP_ALL | PB_WP_OP | PB_WP_VOUT) 241 242 /* 243 * CAPABILITY 244 */ 245 #define PB_CAPABILITY_SMBALERT BIT(4) 246 #define PB_CAPABILITY_ERROR_CHECK BIT(7) 247 248 /* 249 * VOUT_MODE 250 */ 251 #define PB_VOUT_MODE_MODE_MASK 0xe0 252 #define PB_VOUT_MODE_PARAM_MASK 0x1f 253 254 #define PB_VOUT_MODE_LINEAR 0x00 255 #define PB_VOUT_MODE_VID 0x20 256 #define PB_VOUT_MODE_DIRECT 0x40 257 258 /* 259 * Fan configuration 260 */ 261 #define PB_FAN_2_PULSE_MASK (BIT(0) | BIT(1)) 262 #define PB_FAN_2_RPM BIT(2) 263 #define PB_FAN_2_INSTALLED BIT(3) 264 #define PB_FAN_1_PULSE_MASK (BIT(4) | BIT(5)) 265 #define PB_FAN_1_RPM BIT(6) 266 #define PB_FAN_1_INSTALLED BIT(7) 267 268 enum pmbus_fan_mode { percent = 0, rpm }; 269 270 /* 271 * STATUS_BYTE, STATUS_WORD (lower) 272 */ 273 #define PB_STATUS_NONE_ABOVE BIT(0) 274 #define PB_STATUS_CML BIT(1) 275 #define PB_STATUS_TEMPERATURE BIT(2) 276 #define PB_STATUS_VIN_UV BIT(3) 277 #define PB_STATUS_IOUT_OC BIT(4) 278 #define PB_STATUS_VOUT_OV BIT(5) 279 #define PB_STATUS_OFF BIT(6) 280 #define PB_STATUS_BUSY BIT(7) 281 282 /* 283 * STATUS_WORD (upper) 284 */ 285 #define PB_STATUS_UNKNOWN BIT(8) 286 #define PB_STATUS_OTHER BIT(9) 287 #define PB_STATUS_FANS BIT(10) 288 #define PB_STATUS_POWER_GOOD_N BIT(11) 289 #define PB_STATUS_WORD_MFR BIT(12) 290 #define PB_STATUS_INPUT BIT(13) 291 #define PB_STATUS_IOUT_POUT BIT(14) 292 #define PB_STATUS_VOUT BIT(15) 293 294 /* 295 * STATUS_IOUT 296 */ 297 #define PB_POUT_OP_WARNING BIT(0) 298 #define PB_POUT_OP_FAULT BIT(1) 299 #define PB_POWER_LIMITING BIT(2) 300 #define PB_CURRENT_SHARE_FAULT BIT(3) 301 #define PB_IOUT_UC_FAULT BIT(4) 302 #define PB_IOUT_OC_WARNING BIT(5) 303 #define PB_IOUT_OC_LV_FAULT BIT(6) 304 #define PB_IOUT_OC_FAULT BIT(7) 305 306 /* 307 * STATUS_VOUT, STATUS_INPUT 308 */ 309 #define PB_VOLTAGE_UV_FAULT BIT(4) 310 #define PB_VOLTAGE_UV_WARNING BIT(5) 311 #define PB_VOLTAGE_OV_WARNING BIT(6) 312 #define PB_VOLTAGE_OV_FAULT BIT(7) 313 314 /* 315 * STATUS_INPUT 316 */ 317 #define PB_PIN_OP_WARNING BIT(0) 318 #define PB_IIN_OC_WARNING BIT(1) 319 #define PB_IIN_OC_FAULT BIT(2) 320 321 /* 322 * STATUS_TEMPERATURE 323 */ 324 #define PB_TEMP_UT_FAULT BIT(4) 325 #define PB_TEMP_UT_WARNING BIT(5) 326 #define PB_TEMP_OT_WARNING BIT(6) 327 #define PB_TEMP_OT_FAULT BIT(7) 328 329 /* 330 * STATUS_FAN 331 */ 332 #define PB_FAN_AIRFLOW_WARNING BIT(0) 333 #define PB_FAN_AIRFLOW_FAULT BIT(1) 334 #define PB_FAN_FAN2_SPEED_OVERRIDE BIT(2) 335 #define PB_FAN_FAN1_SPEED_OVERRIDE BIT(3) 336 #define PB_FAN_FAN2_WARNING BIT(4) 337 #define PB_FAN_FAN1_WARNING BIT(5) 338 #define PB_FAN_FAN2_FAULT BIT(6) 339 #define PB_FAN_FAN1_FAULT BIT(7) 340 341 /* 342 * CML_FAULT_STATUS 343 */ 344 #define PB_CML_FAULT_OTHER_MEM_LOGIC BIT(0) 345 #define PB_CML_FAULT_OTHER_COMM BIT(1) 346 #define PB_CML_FAULT_PROCESSOR BIT(3) 347 #define PB_CML_FAULT_MEMORY BIT(4) 348 #define PB_CML_FAULT_PACKET_ERROR BIT(5) 349 #define PB_CML_FAULT_INVALID_DATA BIT(6) 350 #define PB_CML_FAULT_INVALID_COMMAND BIT(7) 351 352 enum pmbus_sensor_classes { 353 PSC_VOLTAGE_IN = 0, 354 PSC_VOLTAGE_OUT, 355 PSC_CURRENT_IN, 356 PSC_CURRENT_OUT, 357 PSC_POWER, 358 PSC_TEMPERATURE, 359 PSC_FAN, 360 PSC_PWM, 361 PSC_NUM_CLASSES /* Number of power sensor classes */ 362 }; 363 364 #define PMBUS_PAGES 32 /* Per PMBus specification */ 365 #define PMBUS_PHASES 8 /* Maximum number of phases per page */ 366 367 /* Functionality bit mask */ 368 #define PMBUS_HAVE_VIN BIT(0) 369 #define PMBUS_HAVE_VCAP BIT(1) 370 #define PMBUS_HAVE_VOUT BIT(2) 371 #define PMBUS_HAVE_IIN BIT(3) 372 #define PMBUS_HAVE_IOUT BIT(4) 373 #define PMBUS_HAVE_PIN BIT(5) 374 #define PMBUS_HAVE_POUT BIT(6) 375 #define PMBUS_HAVE_FAN12 BIT(7) 376 #define PMBUS_HAVE_FAN34 BIT(8) 377 #define PMBUS_HAVE_TEMP BIT(9) 378 #define PMBUS_HAVE_TEMP2 BIT(10) 379 #define PMBUS_HAVE_TEMP3 BIT(11) 380 #define PMBUS_HAVE_STATUS_VOUT BIT(12) 381 #define PMBUS_HAVE_STATUS_IOUT BIT(13) 382 #define PMBUS_HAVE_STATUS_INPUT BIT(14) 383 #define PMBUS_HAVE_STATUS_TEMP BIT(15) 384 #define PMBUS_HAVE_STATUS_FAN12 BIT(16) 385 #define PMBUS_HAVE_STATUS_FAN34 BIT(17) 386 #define PMBUS_HAVE_VMON BIT(18) 387 #define PMBUS_HAVE_STATUS_VMON BIT(19) 388 #define PMBUS_HAVE_PWM12 BIT(20) 389 #define PMBUS_HAVE_PWM34 BIT(21) 390 #define PMBUS_HAVE_SAMPLES BIT(22) 391 392 #define PMBUS_PHASE_VIRTUAL BIT(30) /* Phases on this page are virtual */ 393 #define PMBUS_PAGE_VIRTUAL BIT(31) /* Page is virtual */ 394 395 enum pmbus_data_format { linear = 0, direct, vid }; 396 enum vrm_version { vr11 = 0, vr12, vr13, imvp9, amd625mv }; 397 398 struct pmbus_driver_info { 399 int pages; /* Total number of pages */ 400 u8 phases[PMBUS_PAGES]; /* Number of phases per page */ 401 enum pmbus_data_format format[PSC_NUM_CLASSES]; 402 enum vrm_version vrm_version[PMBUS_PAGES]; /* vrm version per page */ 403 /* 404 * Support one set of coefficients for each sensor type 405 * Used for chips providing data in direct mode. 406 */ 407 int m[PSC_NUM_CLASSES]; /* mantissa for direct data format */ 408 int b[PSC_NUM_CLASSES]; /* offset */ 409 int R[PSC_NUM_CLASSES]; /* exponent */ 410 411 u32 func[PMBUS_PAGES]; /* Functionality, per page */ 412 u32 pfunc[PMBUS_PHASES];/* Functionality, per phase */ 413 /* 414 * The following functions map manufacturing specific register values 415 * to PMBus standard register values. Specify only if mapping is 416 * necessary. 417 * Functions return the register value (read) or zero (write) if 418 * successful. A return value of -ENODATA indicates that there is no 419 * manufacturer specific register, but that a standard PMBus register 420 * may exist. Any other negative return value indicates that the 421 * register does not exist, and that no attempt should be made to read 422 * the standard register. 423 */ 424 int (*read_byte_data)(struct i2c_client *client, int page, int reg); 425 int (*read_word_data)(struct i2c_client *client, int page, int phase, 426 int reg); 427 int (*write_word_data)(struct i2c_client *client, int page, int reg, 428 u16 word); 429 int (*write_byte)(struct i2c_client *client, int page, u8 value); 430 /* 431 * The identify function determines supported PMBus functionality. 432 * This function is only necessary if a chip driver supports multiple 433 * chips, and the chip functionality is not pre-determined. 434 */ 435 int (*identify)(struct i2c_client *client, 436 struct pmbus_driver_info *info); 437 438 /* Regulator functionality, if supported by this chip driver. */ 439 int num_regulators; 440 const struct regulator_desc *reg_desc; 441 442 /* custom attributes */ 443 const struct attribute_group **groups; 444 }; 445 446 /* Regulator ops */ 447 448 extern const struct regulator_ops pmbus_regulator_ops; 449 450 /* Macro for filling in array of struct regulator_desc */ 451 #define PMBUS_REGULATOR(_name, _id) \ 452 [_id] = { \ 453 .name = (_name # _id), \ 454 .id = (_id), \ 455 .of_match = of_match_ptr(_name # _id), \ 456 .regulators_node = of_match_ptr("regulators"), \ 457 .ops = &pmbus_regulator_ops, \ 458 .type = REGULATOR_VOLTAGE, \ 459 .owner = THIS_MODULE, \ 460 } 461 462 /* Function declarations */ 463 464 void pmbus_clear_cache(struct i2c_client *client); 465 int pmbus_set_page(struct i2c_client *client, int page, int phase); 466 int pmbus_read_word_data(struct i2c_client *client, int page, int phase, 467 u8 reg); 468 int pmbus_write_word_data(struct i2c_client *client, int page, u8 reg, 469 u16 word); 470 int pmbus_read_byte_data(struct i2c_client *client, int page, u8 reg); 471 int pmbus_write_byte(struct i2c_client *client, int page, u8 value); 472 int pmbus_write_byte_data(struct i2c_client *client, int page, u8 reg, 473 u8 value); 474 int pmbus_update_byte_data(struct i2c_client *client, int page, u8 reg, 475 u8 mask, u8 value); 476 void pmbus_clear_faults(struct i2c_client *client); 477 bool pmbus_check_byte_register(struct i2c_client *client, int page, int reg); 478 bool pmbus_check_word_register(struct i2c_client *client, int page, int reg); 479 int pmbus_do_probe(struct i2c_client *client, const struct i2c_device_id *id, 480 struct pmbus_driver_info *info); 481 int pmbus_do_remove(struct i2c_client *client); 482 const struct pmbus_driver_info *pmbus_get_driver_info(struct i2c_client 483 *client); 484 int pmbus_get_fan_rate_device(struct i2c_client *client, int page, int id, 485 enum pmbus_fan_mode mode); 486 int pmbus_get_fan_rate_cached(struct i2c_client *client, int page, int id, 487 enum pmbus_fan_mode mode); 488 int pmbus_update_fan(struct i2c_client *client, int page, int id, 489 u8 config, u8 mask, u16 command); 490 struct dentry *pmbus_get_debugfs_dir(struct i2c_client *client); 491 492 #endif /* PMBUS_H */ 493