1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * nct7904.c - driver for Nuvoton NCT7904D. 4 * 5 * Copyright (c) 2015 Kontron 6 * Author: Vadim V. Vlasov <vvlasov@dev.rtsoft.ru> 7 * 8 * Copyright (c) 2019 Advantech 9 * Author: Amy.Shih <amy.shih@advantech.com.tw> 10 * 11 * Supports the following chips: 12 * 13 * Chip #vin #fan #pwm #temp #dts chip ID 14 * nct7904d 20 12 4 5 8 0xc5 15 */ 16 17 #include <linux/module.h> 18 #include <linux/device.h> 19 #include <linux/init.h> 20 #include <linux/i2c.h> 21 #include <linux/mutex.h> 22 #include <linux/hwmon.h> 23 24 #define VENDOR_ID_REG 0x7A /* Any bank */ 25 #define NUVOTON_ID 0x50 26 #define CHIP_ID_REG 0x7B /* Any bank */ 27 #define NCT7904_ID 0xC5 28 #define DEVICE_ID_REG 0x7C /* Any bank */ 29 30 #define BANK_SEL_REG 0xFF 31 #define BANK_0 0x00 32 #define BANK_1 0x01 33 #define BANK_2 0x02 34 #define BANK_3 0x03 35 #define BANK_4 0x04 36 #define BANK_MAX 0x04 37 38 #define FANIN_MAX 12 /* Counted from 1 */ 39 #define VSEN_MAX 21 /* VSEN1..14, 3VDD, VBAT, V3VSB, 40 LTD (not a voltage), VSEN17..19 */ 41 #define FANCTL_MAX 4 /* Counted from 1 */ 42 #define TCPU_MAX 8 /* Counted from 1 */ 43 #define TEMP_MAX 4 /* Counted from 1 */ 44 #define SMI_STS_MAX 10 /* Counted from 1 */ 45 46 #define VT_ADC_CTRL0_REG 0x20 /* Bank 0 */ 47 #define VT_ADC_CTRL1_REG 0x21 /* Bank 0 */ 48 #define VT_ADC_CTRL2_REG 0x22 /* Bank 0 */ 49 #define FANIN_CTRL0_REG 0x24 50 #define FANIN_CTRL1_REG 0x25 51 #define DTS_T_CTRL0_REG 0x26 52 #define DTS_T_CTRL1_REG 0x27 53 #define VT_ADC_MD_REG 0x2E 54 55 #define VSEN1_HV_LL_REG 0x02 /* Bank 1; 2 regs (HV/LV) per sensor */ 56 #define VSEN1_LV_LL_REG 0x03 /* Bank 1; 2 regs (HV/LV) per sensor */ 57 #define VSEN1_HV_HL_REG 0x00 /* Bank 1; 2 regs (HV/LV) per sensor */ 58 #define VSEN1_LV_HL_REG 0x01 /* Bank 1; 2 regs (HV/LV) per sensor */ 59 #define SMI_STS1_REG 0xC1 /* Bank 0; SMI Status Register */ 60 #define SMI_STS3_REG 0xC3 /* Bank 0; SMI Status Register */ 61 #define SMI_STS5_REG 0xC5 /* Bank 0; SMI Status Register */ 62 #define SMI_STS7_REG 0xC7 /* Bank 0; SMI Status Register */ 63 #define SMI_STS8_REG 0xC8 /* Bank 0; SMI Status Register */ 64 65 #define VSEN1_HV_REG 0x40 /* Bank 0; 2 regs (HV/LV) per sensor */ 66 #define TEMP_CH1_HV_REG 0x42 /* Bank 0; same as VSEN2_HV */ 67 #define LTD_HV_REG 0x62 /* Bank 0; 2 regs in VSEN range */ 68 #define LTD_HV_HL_REG 0x44 /* Bank 1; 1 reg for LTD */ 69 #define LTD_LV_HL_REG 0x45 /* Bank 1; 1 reg for LTD */ 70 #define LTD_HV_LL_REG 0x46 /* Bank 1; 1 reg for LTD */ 71 #define LTD_LV_LL_REG 0x47 /* Bank 1; 1 reg for LTD */ 72 #define TEMP_CH1_CH_REG 0x05 /* Bank 1; 1 reg for LTD */ 73 #define TEMP_CH1_W_REG 0x06 /* Bank 1; 1 reg for LTD */ 74 #define TEMP_CH1_WH_REG 0x07 /* Bank 1; 1 reg for LTD */ 75 #define TEMP_CH1_C_REG 0x04 /* Bank 1; 1 reg per sensor */ 76 #define DTS_T_CPU1_C_REG 0x90 /* Bank 1; 1 reg per sensor */ 77 #define DTS_T_CPU1_CH_REG 0x91 /* Bank 1; 1 reg per sensor */ 78 #define DTS_T_CPU1_W_REG 0x92 /* Bank 1; 1 reg per sensor */ 79 #define DTS_T_CPU1_WH_REG 0x93 /* Bank 1; 1 reg per sensor */ 80 #define FANIN1_HV_REG 0x80 /* Bank 0; 2 regs (HV/LV) per sensor */ 81 #define FANIN1_HV_HL_REG 0x60 /* Bank 1; 2 regs (HV/LV) per sensor */ 82 #define FANIN1_LV_HL_REG 0x61 /* Bank 1; 2 regs (HV/LV) per sensor */ 83 #define T_CPU1_HV_REG 0xA0 /* Bank 0; 2 regs (HV/LV) per sensor */ 84 85 #define PRTS_REG 0x03 /* Bank 2 */ 86 #define PFE_REG 0x00 /* Bank 2; PECI Function Enable */ 87 #define TSI_CTRL_REG 0x50 /* Bank 2; TSI Control Register */ 88 #define FANCTL1_FMR_REG 0x00 /* Bank 3; 1 reg per channel */ 89 #define FANCTL1_OUT_REG 0x10 /* Bank 3; 1 reg per channel */ 90 91 #define VOLT_MONITOR_MODE 0x0 92 #define THERMAL_DIODE_MODE 0x1 93 #define THERMISTOR_MODE 0x3 94 95 #define ENABLE_TSI BIT(1) 96 97 static const unsigned short normal_i2c[] = { 98 0x2d, 0x2e, I2C_CLIENT_END 99 }; 100 101 struct nct7904_data { 102 struct i2c_client *client; 103 struct mutex bank_lock; 104 int bank_sel; 105 u32 fanin_mask; 106 u32 vsen_mask; 107 u32 tcpu_mask; 108 u8 fan_mode[FANCTL_MAX]; 109 u8 enable_dts; 110 u8 has_dts; 111 u8 temp_mode; /* 0: TR mode, 1: TD mode */ 112 u8 fan_alarm[2]; 113 u8 vsen_alarm[3]; 114 }; 115 116 /* Access functions */ 117 static int nct7904_bank_lock(struct nct7904_data *data, unsigned int bank) 118 { 119 int ret; 120 121 mutex_lock(&data->bank_lock); 122 if (data->bank_sel == bank) 123 return 0; 124 ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank); 125 if (ret == 0) 126 data->bank_sel = bank; 127 else 128 data->bank_sel = -1; 129 return ret; 130 } 131 132 static inline void nct7904_bank_release(struct nct7904_data *data) 133 { 134 mutex_unlock(&data->bank_lock); 135 } 136 137 /* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */ 138 static int nct7904_read_reg(struct nct7904_data *data, 139 unsigned int bank, unsigned int reg) 140 { 141 struct i2c_client *client = data->client; 142 int ret; 143 144 ret = nct7904_bank_lock(data, bank); 145 if (ret == 0) 146 ret = i2c_smbus_read_byte_data(client, reg); 147 148 nct7904_bank_release(data); 149 return ret; 150 } 151 152 /* 153 * Read 2-byte register. Returns register in big-endian format or 154 * -ERRNO on error. 155 */ 156 static int nct7904_read_reg16(struct nct7904_data *data, 157 unsigned int bank, unsigned int reg) 158 { 159 struct i2c_client *client = data->client; 160 int ret, hi; 161 162 ret = nct7904_bank_lock(data, bank); 163 if (ret == 0) { 164 ret = i2c_smbus_read_byte_data(client, reg); 165 if (ret >= 0) { 166 hi = ret; 167 ret = i2c_smbus_read_byte_data(client, reg + 1); 168 if (ret >= 0) 169 ret |= hi << 8; 170 } 171 } 172 173 nct7904_bank_release(data); 174 return ret; 175 } 176 177 /* Write 1-byte register. Returns 0 or -ERRNO on error. */ 178 static int nct7904_write_reg(struct nct7904_data *data, 179 unsigned int bank, unsigned int reg, u8 val) 180 { 181 struct i2c_client *client = data->client; 182 int ret; 183 184 ret = nct7904_bank_lock(data, bank); 185 if (ret == 0) 186 ret = i2c_smbus_write_byte_data(client, reg, val); 187 188 nct7904_bank_release(data); 189 return ret; 190 } 191 192 static int nct7904_read_fan(struct device *dev, u32 attr, int channel, 193 long *val) 194 { 195 struct nct7904_data *data = dev_get_drvdata(dev); 196 unsigned int cnt, rpm; 197 int ret; 198 199 switch (attr) { 200 case hwmon_fan_input: 201 ret = nct7904_read_reg16(data, BANK_0, 202 FANIN1_HV_REG + channel * 2); 203 if (ret < 0) 204 return ret; 205 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f); 206 if (cnt == 0x1fff) 207 rpm = 0; 208 else 209 rpm = 1350000 / cnt; 210 *val = rpm; 211 return 0; 212 case hwmon_fan_min: 213 ret = nct7904_read_reg16(data, BANK_1, 214 FANIN1_HV_HL_REG + channel * 2); 215 if (ret < 0) 216 return ret; 217 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f); 218 if (cnt == 0x1fff) 219 rpm = 0; 220 else 221 rpm = 1350000 / cnt; 222 *val = rpm; 223 return 0; 224 case hwmon_fan_alarm: 225 ret = nct7904_read_reg(data, BANK_0, 226 SMI_STS5_REG + (channel >> 3)); 227 if (ret < 0) 228 return ret; 229 if (!data->fan_alarm[channel >> 3]) 230 data->fan_alarm[channel >> 3] = ret & 0xff; 231 else 232 /* If there is new alarm showing up */ 233 data->fan_alarm[channel >> 3] |= (ret & 0xff); 234 *val = (data->fan_alarm[channel >> 3] >> (channel & 0x07)) & 1; 235 /* Needs to clean the alarm if alarm existing */ 236 if (*val) 237 data->fan_alarm[channel >> 3] ^= 1 << (channel & 0x07); 238 return 0; 239 default: 240 return -EOPNOTSUPP; 241 } 242 } 243 244 static umode_t nct7904_fan_is_visible(const void *_data, u32 attr, int channel) 245 { 246 const struct nct7904_data *data = _data; 247 248 switch (attr) { 249 case hwmon_fan_input: 250 case hwmon_fan_alarm: 251 if (data->fanin_mask & (1 << channel)) 252 return 0444; 253 break; 254 case hwmon_fan_min: 255 if (data->fanin_mask & (1 << channel)) 256 return 0644; 257 break; 258 default: 259 break; 260 } 261 262 return 0; 263 } 264 265 static u8 nct7904_chan_to_index[] = { 266 0, /* Not used */ 267 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 268 18, 19, 20, 16 269 }; 270 271 static int nct7904_read_in(struct device *dev, u32 attr, int channel, 272 long *val) 273 { 274 struct nct7904_data *data = dev_get_drvdata(dev); 275 int ret, volt, index; 276 277 index = nct7904_chan_to_index[channel]; 278 279 switch (attr) { 280 case hwmon_in_input: 281 ret = nct7904_read_reg16(data, BANK_0, 282 VSEN1_HV_REG + index * 2); 283 if (ret < 0) 284 return ret; 285 volt = ((ret & 0xff00) >> 5) | (ret & 0x7); 286 if (index < 14) 287 volt *= 2; /* 0.002V scale */ 288 else 289 volt *= 6; /* 0.006V scale */ 290 *val = volt; 291 return 0; 292 case hwmon_in_min: 293 ret = nct7904_read_reg16(data, BANK_1, 294 VSEN1_HV_LL_REG + index * 4); 295 if (ret < 0) 296 return ret; 297 volt = ((ret & 0xff00) >> 5) | (ret & 0x7); 298 if (index < 14) 299 volt *= 2; /* 0.002V scale */ 300 else 301 volt *= 6; /* 0.006V scale */ 302 *val = volt; 303 return 0; 304 case hwmon_in_max: 305 ret = nct7904_read_reg16(data, BANK_1, 306 VSEN1_HV_HL_REG + index * 4); 307 if (ret < 0) 308 return ret; 309 volt = ((ret & 0xff00) >> 5) | (ret & 0x7); 310 if (index < 14) 311 volt *= 2; /* 0.002V scale */ 312 else 313 volt *= 6; /* 0.006V scale */ 314 *val = volt; 315 return 0; 316 case hwmon_in_alarm: 317 ret = nct7904_read_reg(data, BANK_0, 318 SMI_STS1_REG + (index >> 3)); 319 if (ret < 0) 320 return ret; 321 if (!data->vsen_alarm[index >> 3]) 322 data->vsen_alarm[index >> 3] = ret & 0xff; 323 else 324 /* If there is new alarm showing up */ 325 data->vsen_alarm[index >> 3] |= (ret & 0xff); 326 *val = (data->vsen_alarm[index >> 3] >> (index & 0x07)) & 1; 327 /* Needs to clean the alarm if alarm existing */ 328 if (*val) 329 data->vsen_alarm[index >> 3] ^= 1 << (index & 0x07); 330 return 0; 331 default: 332 return -EOPNOTSUPP; 333 } 334 } 335 336 static umode_t nct7904_in_is_visible(const void *_data, u32 attr, int channel) 337 { 338 const struct nct7904_data *data = _data; 339 int index = nct7904_chan_to_index[channel]; 340 341 switch (attr) { 342 case hwmon_in_input: 343 case hwmon_in_alarm: 344 if (channel > 0 && (data->vsen_mask & BIT(index))) 345 return 0444; 346 break; 347 case hwmon_in_min: 348 case hwmon_in_max: 349 if (channel > 0 && (data->vsen_mask & BIT(index))) 350 return 0644; 351 break; 352 default: 353 break; 354 } 355 356 return 0; 357 } 358 359 static int nct7904_read_temp(struct device *dev, u32 attr, int channel, 360 long *val) 361 { 362 struct nct7904_data *data = dev_get_drvdata(dev); 363 int ret, temp; 364 unsigned int reg1, reg2, reg3; 365 s8 temps; 366 367 switch (attr) { 368 case hwmon_temp_input: 369 if (channel == 4) 370 ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG); 371 else if (channel < 5) 372 ret = nct7904_read_reg16(data, BANK_0, 373 TEMP_CH1_HV_REG + channel * 4); 374 else 375 ret = nct7904_read_reg16(data, BANK_0, 376 T_CPU1_HV_REG + (channel - 5) 377 * 2); 378 if (ret < 0) 379 return ret; 380 temp = ((ret & 0xff00) >> 5) | (ret & 0x7); 381 *val = sign_extend32(temp, 10) * 125; 382 return 0; 383 case hwmon_temp_alarm: 384 if (channel == 4) { 385 ret = nct7904_read_reg(data, BANK_0, 386 SMI_STS3_REG); 387 if (ret < 0) 388 return ret; 389 *val = (ret >> 1) & 1; 390 } else if (channel < 4) { 391 ret = nct7904_read_reg(data, BANK_0, 392 SMI_STS1_REG); 393 if (ret < 0) 394 return ret; 395 *val = (ret >> (((channel * 2) + 1) & 0x07)) & 1; 396 } else { 397 if ((channel - 5) < 4) { 398 ret = nct7904_read_reg(data, BANK_0, 399 SMI_STS7_REG + 400 ((channel - 5) >> 3)); 401 if (ret < 0) 402 return ret; 403 *val = (ret >> ((channel - 5) & 0x07)) & 1; 404 } else { 405 ret = nct7904_read_reg(data, BANK_0, 406 SMI_STS8_REG + 407 ((channel - 5) >> 3)); 408 if (ret < 0) 409 return ret; 410 *val = (ret >> (((channel - 5) & 0x07) - 4)) 411 & 1; 412 } 413 } 414 return 0; 415 case hwmon_temp_type: 416 if (channel < 5) { 417 if ((data->tcpu_mask >> channel) & 0x01) { 418 if ((data->temp_mode >> channel) & 0x01) 419 *val = 3; /* TD */ 420 else 421 *val = 4; /* TR */ 422 } else { 423 *val = 0; 424 } 425 } else { 426 if ((data->has_dts >> (channel - 5)) & 0x01) { 427 if (data->enable_dts & ENABLE_TSI) 428 *val = 5; /* TSI */ 429 else 430 *val = 6; /* PECI */ 431 } else { 432 *val = 0; 433 } 434 } 435 return 0; 436 case hwmon_temp_max: 437 reg1 = LTD_HV_LL_REG; 438 reg2 = TEMP_CH1_W_REG; 439 reg3 = DTS_T_CPU1_W_REG; 440 break; 441 case hwmon_temp_max_hyst: 442 reg1 = LTD_LV_LL_REG; 443 reg2 = TEMP_CH1_WH_REG; 444 reg3 = DTS_T_CPU1_WH_REG; 445 break; 446 case hwmon_temp_crit: 447 reg1 = LTD_HV_HL_REG; 448 reg2 = TEMP_CH1_C_REG; 449 reg3 = DTS_T_CPU1_C_REG; 450 break; 451 case hwmon_temp_crit_hyst: 452 reg1 = LTD_LV_HL_REG; 453 reg2 = TEMP_CH1_CH_REG; 454 reg3 = DTS_T_CPU1_CH_REG; 455 break; 456 default: 457 return -EOPNOTSUPP; 458 } 459 460 if (channel == 4) 461 ret = nct7904_read_reg(data, BANK_1, reg1); 462 else if (channel < 5) 463 ret = nct7904_read_reg(data, BANK_1, 464 reg2 + channel * 8); 465 else 466 ret = nct7904_read_reg(data, BANK_1, 467 reg3 + (channel - 5) * 4); 468 469 if (ret < 0) 470 return ret; 471 temps = ret; 472 *val = temps * 1000; 473 return 0; 474 } 475 476 static umode_t nct7904_temp_is_visible(const void *_data, u32 attr, int channel) 477 { 478 const struct nct7904_data *data = _data; 479 480 switch (attr) { 481 case hwmon_temp_input: 482 case hwmon_temp_alarm: 483 case hwmon_temp_type: 484 if (channel < 5) { 485 if (data->tcpu_mask & BIT(channel)) 486 return 0444; 487 } else { 488 if (data->has_dts & BIT(channel - 5)) 489 return 0444; 490 } 491 break; 492 case hwmon_temp_max: 493 case hwmon_temp_max_hyst: 494 case hwmon_temp_crit: 495 case hwmon_temp_crit_hyst: 496 if (channel < 5) { 497 if (data->tcpu_mask & BIT(channel)) 498 return 0644; 499 } else { 500 if (data->has_dts & BIT(channel - 5)) 501 return 0644; 502 } 503 break; 504 default: 505 break; 506 } 507 508 return 0; 509 } 510 511 static int nct7904_read_pwm(struct device *dev, u32 attr, int channel, 512 long *val) 513 { 514 struct nct7904_data *data = dev_get_drvdata(dev); 515 int ret; 516 517 switch (attr) { 518 case hwmon_pwm_input: 519 ret = nct7904_read_reg(data, BANK_3, FANCTL1_OUT_REG + channel); 520 if (ret < 0) 521 return ret; 522 *val = ret; 523 return 0; 524 case hwmon_pwm_enable: 525 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + channel); 526 if (ret < 0) 527 return ret; 528 529 *val = ret ? 2 : 1; 530 return 0; 531 default: 532 return -EOPNOTSUPP; 533 } 534 } 535 536 static int nct7904_write_temp(struct device *dev, u32 attr, int channel, 537 long val) 538 { 539 struct nct7904_data *data = dev_get_drvdata(dev); 540 int ret; 541 unsigned int reg1, reg2, reg3; 542 543 val = clamp_val(val / 1000, -128, 127); 544 545 switch (attr) { 546 case hwmon_temp_max: 547 reg1 = LTD_HV_LL_REG; 548 reg2 = TEMP_CH1_W_REG; 549 reg3 = DTS_T_CPU1_W_REG; 550 break; 551 case hwmon_temp_max_hyst: 552 reg1 = LTD_LV_LL_REG; 553 reg2 = TEMP_CH1_WH_REG; 554 reg3 = DTS_T_CPU1_WH_REG; 555 break; 556 case hwmon_temp_crit: 557 reg1 = LTD_HV_HL_REG; 558 reg2 = TEMP_CH1_C_REG; 559 reg3 = DTS_T_CPU1_C_REG; 560 break; 561 case hwmon_temp_crit_hyst: 562 reg1 = LTD_LV_HL_REG; 563 reg2 = TEMP_CH1_CH_REG; 564 reg3 = DTS_T_CPU1_CH_REG; 565 break; 566 default: 567 return -EOPNOTSUPP; 568 } 569 if (channel == 4) 570 ret = nct7904_write_reg(data, BANK_1, reg1, val); 571 else if (channel < 5) 572 ret = nct7904_write_reg(data, BANK_1, 573 reg2 + channel * 8, val); 574 else 575 ret = nct7904_write_reg(data, BANK_1, 576 reg3 + (channel - 5) * 4, val); 577 578 return ret; 579 } 580 581 static int nct7904_write_fan(struct device *dev, u32 attr, int channel, 582 long val) 583 { 584 struct nct7904_data *data = dev_get_drvdata(dev); 585 int ret; 586 u8 tmp; 587 588 switch (attr) { 589 case hwmon_fan_min: 590 if (val <= 0) 591 return -EINVAL; 592 593 val = clamp_val(DIV_ROUND_CLOSEST(1350000, val), 1, 0x1fff); 594 tmp = (val >> 5) & 0xff; 595 ret = nct7904_write_reg(data, BANK_1, 596 FANIN1_HV_HL_REG + channel * 2, tmp); 597 if (ret < 0) 598 return ret; 599 tmp = val & 0x1f; 600 ret = nct7904_write_reg(data, BANK_1, 601 FANIN1_LV_HL_REG + channel * 2, tmp); 602 return ret; 603 default: 604 return -EOPNOTSUPP; 605 } 606 } 607 608 static int nct7904_write_in(struct device *dev, u32 attr, int channel, 609 long val) 610 { 611 struct nct7904_data *data = dev_get_drvdata(dev); 612 int ret, index, tmp; 613 614 index = nct7904_chan_to_index[channel]; 615 616 if (index < 14) 617 val = val / 2; /* 0.002V scale */ 618 else 619 val = val / 6; /* 0.006V scale */ 620 621 val = clamp_val(val, 0, 0x7ff); 622 623 switch (attr) { 624 case hwmon_in_min: 625 tmp = nct7904_read_reg(data, BANK_1, 626 VSEN1_LV_LL_REG + index * 4); 627 if (tmp < 0) 628 return tmp; 629 tmp &= ~0x7; 630 tmp |= val & 0x7; 631 ret = nct7904_write_reg(data, BANK_1, 632 VSEN1_LV_LL_REG + index * 4, tmp); 633 if (ret < 0) 634 return ret; 635 tmp = nct7904_read_reg(data, BANK_1, 636 VSEN1_HV_LL_REG + index * 4); 637 if (tmp < 0) 638 return tmp; 639 tmp = (val >> 3) & 0xff; 640 ret = nct7904_write_reg(data, BANK_1, 641 VSEN1_HV_LL_REG + index * 4, tmp); 642 return ret; 643 case hwmon_in_max: 644 tmp = nct7904_read_reg(data, BANK_1, 645 VSEN1_LV_HL_REG + index * 4); 646 if (tmp < 0) 647 return tmp; 648 tmp &= ~0x7; 649 tmp |= val & 0x7; 650 ret = nct7904_write_reg(data, BANK_1, 651 VSEN1_LV_HL_REG + index * 4, tmp); 652 if (ret < 0) 653 return ret; 654 tmp = nct7904_read_reg(data, BANK_1, 655 VSEN1_HV_HL_REG + index * 4); 656 if (tmp < 0) 657 return tmp; 658 tmp = (val >> 3) & 0xff; 659 ret = nct7904_write_reg(data, BANK_1, 660 VSEN1_HV_HL_REG + index * 4, tmp); 661 return ret; 662 default: 663 return -EOPNOTSUPP; 664 } 665 } 666 667 static int nct7904_write_pwm(struct device *dev, u32 attr, int channel, 668 long val) 669 { 670 struct nct7904_data *data = dev_get_drvdata(dev); 671 int ret; 672 673 switch (attr) { 674 case hwmon_pwm_input: 675 if (val < 0 || val > 255) 676 return -EINVAL; 677 ret = nct7904_write_reg(data, BANK_3, FANCTL1_OUT_REG + channel, 678 val); 679 return ret; 680 case hwmon_pwm_enable: 681 if (val < 1 || val > 2 || 682 (val == 2 && !data->fan_mode[channel])) 683 return -EINVAL; 684 ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + channel, 685 val == 2 ? data->fan_mode[channel] : 0); 686 return ret; 687 default: 688 return -EOPNOTSUPP; 689 } 690 } 691 692 static umode_t nct7904_pwm_is_visible(const void *_data, u32 attr, int channel) 693 { 694 switch (attr) { 695 case hwmon_pwm_input: 696 case hwmon_pwm_enable: 697 return 0644; 698 default: 699 return 0; 700 } 701 } 702 703 static int nct7904_read(struct device *dev, enum hwmon_sensor_types type, 704 u32 attr, int channel, long *val) 705 { 706 switch (type) { 707 case hwmon_in: 708 return nct7904_read_in(dev, attr, channel, val); 709 case hwmon_fan: 710 return nct7904_read_fan(dev, attr, channel, val); 711 case hwmon_pwm: 712 return nct7904_read_pwm(dev, attr, channel, val); 713 case hwmon_temp: 714 return nct7904_read_temp(dev, attr, channel, val); 715 default: 716 return -EOPNOTSUPP; 717 } 718 } 719 720 static int nct7904_write(struct device *dev, enum hwmon_sensor_types type, 721 u32 attr, int channel, long val) 722 { 723 switch (type) { 724 case hwmon_in: 725 return nct7904_write_in(dev, attr, channel, val); 726 case hwmon_fan: 727 return nct7904_write_fan(dev, attr, channel, val); 728 case hwmon_pwm: 729 return nct7904_write_pwm(dev, attr, channel, val); 730 case hwmon_temp: 731 return nct7904_write_temp(dev, attr, channel, val); 732 default: 733 return -EOPNOTSUPP; 734 } 735 } 736 737 static umode_t nct7904_is_visible(const void *data, 738 enum hwmon_sensor_types type, 739 u32 attr, int channel) 740 { 741 switch (type) { 742 case hwmon_in: 743 return nct7904_in_is_visible(data, attr, channel); 744 case hwmon_fan: 745 return nct7904_fan_is_visible(data, attr, channel); 746 case hwmon_pwm: 747 return nct7904_pwm_is_visible(data, attr, channel); 748 case hwmon_temp: 749 return nct7904_temp_is_visible(data, attr, channel); 750 default: 751 return 0; 752 } 753 } 754 755 /* Return 0 if detection is successful, -ENODEV otherwise */ 756 static int nct7904_detect(struct i2c_client *client, 757 struct i2c_board_info *info) 758 { 759 struct i2c_adapter *adapter = client->adapter; 760 761 if (!i2c_check_functionality(adapter, 762 I2C_FUNC_SMBUS_READ_BYTE | 763 I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) 764 return -ENODEV; 765 766 /* Determine the chip type. */ 767 if (i2c_smbus_read_byte_data(client, VENDOR_ID_REG) != NUVOTON_ID || 768 i2c_smbus_read_byte_data(client, CHIP_ID_REG) != NCT7904_ID || 769 (i2c_smbus_read_byte_data(client, DEVICE_ID_REG) & 0xf0) != 0x50 || 770 (i2c_smbus_read_byte_data(client, BANK_SEL_REG) & 0xf8) != 0x00) 771 return -ENODEV; 772 773 strlcpy(info->type, "nct7904", I2C_NAME_SIZE); 774 775 return 0; 776 } 777 778 static const struct hwmon_channel_info *nct7904_info[] = { 779 HWMON_CHANNEL_INFO(in, 780 /* dummy, skipped in is_visible */ 781 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 782 HWMON_I_ALARM, 783 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 784 HWMON_I_ALARM, 785 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 786 HWMON_I_ALARM, 787 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 788 HWMON_I_ALARM, 789 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 790 HWMON_I_ALARM, 791 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 792 HWMON_I_ALARM, 793 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 794 HWMON_I_ALARM, 795 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 796 HWMON_I_ALARM, 797 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 798 HWMON_I_ALARM, 799 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 800 HWMON_I_ALARM, 801 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 802 HWMON_I_ALARM, 803 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 804 HWMON_I_ALARM, 805 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 806 HWMON_I_ALARM, 807 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 808 HWMON_I_ALARM, 809 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 810 HWMON_I_ALARM, 811 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 812 HWMON_I_ALARM, 813 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 814 HWMON_I_ALARM, 815 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 816 HWMON_I_ALARM, 817 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 818 HWMON_I_ALARM, 819 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 820 HWMON_I_ALARM, 821 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 822 HWMON_I_ALARM), 823 HWMON_CHANNEL_INFO(fan, 824 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 825 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 826 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 827 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 828 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 829 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 830 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 831 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 832 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 833 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 834 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM, 835 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM), 836 HWMON_CHANNEL_INFO(pwm, 837 HWMON_PWM_INPUT | HWMON_PWM_ENABLE, 838 HWMON_PWM_INPUT | HWMON_PWM_ENABLE, 839 HWMON_PWM_INPUT | HWMON_PWM_ENABLE, 840 HWMON_PWM_INPUT | HWMON_PWM_ENABLE), 841 HWMON_CHANNEL_INFO(temp, 842 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 843 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 844 HWMON_T_CRIT_HYST, 845 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 846 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 847 HWMON_T_CRIT_HYST, 848 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 849 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 850 HWMON_T_CRIT_HYST, 851 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 852 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 853 HWMON_T_CRIT_HYST, 854 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 855 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 856 HWMON_T_CRIT_HYST, 857 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 858 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 859 HWMON_T_CRIT_HYST, 860 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 861 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 862 HWMON_T_CRIT_HYST, 863 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 864 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 865 HWMON_T_CRIT_HYST, 866 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 867 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 868 HWMON_T_CRIT_HYST, 869 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 870 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 871 HWMON_T_CRIT_HYST, 872 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 873 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 874 HWMON_T_CRIT_HYST, 875 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 876 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 877 HWMON_T_CRIT_HYST, 878 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX | 879 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT | 880 HWMON_T_CRIT_HYST), 881 NULL 882 }; 883 884 static const struct hwmon_ops nct7904_hwmon_ops = { 885 .is_visible = nct7904_is_visible, 886 .read = nct7904_read, 887 .write = nct7904_write, 888 }; 889 890 static const struct hwmon_chip_info nct7904_chip_info = { 891 .ops = &nct7904_hwmon_ops, 892 .info = nct7904_info, 893 }; 894 895 static int nct7904_probe(struct i2c_client *client, 896 const struct i2c_device_id *id) 897 { 898 struct nct7904_data *data; 899 struct device *hwmon_dev; 900 struct device *dev = &client->dev; 901 int ret, i; 902 u32 mask; 903 u8 val, bit; 904 905 data = devm_kzalloc(dev, sizeof(struct nct7904_data), GFP_KERNEL); 906 if (!data) 907 return -ENOMEM; 908 909 data->client = client; 910 mutex_init(&data->bank_lock); 911 data->bank_sel = -1; 912 913 /* Setup sensor groups. */ 914 /* FANIN attributes */ 915 ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG); 916 if (ret < 0) 917 return ret; 918 data->fanin_mask = (ret >> 8) | ((ret & 0xff) << 8); 919 920 /* 921 * VSEN attributes 922 * 923 * Note: voltage sensors overlap with external temperature 924 * sensors. So, if we ever decide to support the latter 925 * we will have to adjust 'vsen_mask' accordingly. 926 */ 927 mask = 0; 928 ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG); 929 if (ret >= 0) 930 mask = (ret >> 8) | ((ret & 0xff) << 8); 931 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG); 932 if (ret >= 0) 933 mask |= (ret << 16); 934 data->vsen_mask = mask; 935 936 /* CPU_TEMP attributes */ 937 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG); 938 if (ret < 0) 939 return ret; 940 941 if ((ret & 0x6) == 0x6) 942 data->tcpu_mask |= 1; /* TR1 */ 943 if ((ret & 0x18) == 0x18) 944 data->tcpu_mask |= 2; /* TR2 */ 945 if ((ret & 0x20) == 0x20) 946 data->tcpu_mask |= 4; /* TR3 */ 947 if ((ret & 0x80) == 0x80) 948 data->tcpu_mask |= 8; /* TR4 */ 949 950 /* LTD */ 951 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG); 952 if (ret < 0) 953 return ret; 954 if ((ret & 0x02) == 0x02) 955 data->tcpu_mask |= 0x10; 956 957 /* Multi-Function detecting for Volt and TR/TD */ 958 ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG); 959 if (ret < 0) 960 return ret; 961 962 data->temp_mode = 0; 963 for (i = 0; i < 4; i++) { 964 val = (ret >> (i * 2)) & 0x03; 965 bit = (1 << i); 966 if (val == VOLT_MONITOR_MODE) { 967 data->tcpu_mask &= ~bit; 968 } else if (val == THERMAL_DIODE_MODE && i < 2) { 969 data->temp_mode |= bit; 970 data->vsen_mask &= ~(0x06 << (i * 2)); 971 } else if (val == THERMISTOR_MODE) { 972 data->vsen_mask &= ~(0x02 << (i * 2)); 973 } else { 974 /* Reserved */ 975 data->tcpu_mask &= ~bit; 976 data->vsen_mask &= ~(0x06 << (i * 2)); 977 } 978 } 979 980 /* PECI */ 981 ret = nct7904_read_reg(data, BANK_2, PFE_REG); 982 if (ret < 0) 983 return ret; 984 if (ret & 0x80) { 985 data->enable_dts = 1; /* Enable DTS & PECI */ 986 } else { 987 ret = nct7904_read_reg(data, BANK_2, TSI_CTRL_REG); 988 if (ret < 0) 989 return ret; 990 if (ret & 0x80) 991 data->enable_dts = 0x3; /* Enable DTS & TSI */ 992 } 993 994 /* Check DTS enable status */ 995 if (data->enable_dts) { 996 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG); 997 if (ret < 0) 998 return ret; 999 data->has_dts = ret & 0xF; 1000 if (data->enable_dts & ENABLE_TSI) { 1001 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG); 1002 if (ret < 0) 1003 return ret; 1004 data->has_dts |= (ret & 0xF) << 4; 1005 } 1006 } 1007 1008 for (i = 0; i < FANCTL_MAX; i++) { 1009 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + i); 1010 if (ret < 0) 1011 return ret; 1012 data->fan_mode[i] = ret; 1013 } 1014 1015 /* Read all of SMI status register to clear alarms */ 1016 for (i = 0; i < SMI_STS_MAX; i++) { 1017 ret = nct7904_read_reg(data, BANK_0, SMI_STS1_REG + i); 1018 if (ret < 0) 1019 return ret; 1020 } 1021 1022 hwmon_dev = 1023 devm_hwmon_device_register_with_info(dev, client->name, data, 1024 &nct7904_chip_info, NULL); 1025 return PTR_ERR_OR_ZERO(hwmon_dev); 1026 } 1027 1028 static const struct i2c_device_id nct7904_id[] = { 1029 {"nct7904", 0}, 1030 {} 1031 }; 1032 MODULE_DEVICE_TABLE(i2c, nct7904_id); 1033 1034 static struct i2c_driver nct7904_driver = { 1035 .class = I2C_CLASS_HWMON, 1036 .driver = { 1037 .name = "nct7904", 1038 }, 1039 .probe = nct7904_probe, 1040 .id_table = nct7904_id, 1041 .detect = nct7904_detect, 1042 .address_list = normal_i2c, 1043 }; 1044 1045 module_i2c_driver(nct7904_driver); 1046 1047 MODULE_AUTHOR("Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>"); 1048 MODULE_DESCRIPTION("Hwmon driver for NUVOTON NCT7904"); 1049 MODULE_LICENSE("GPL"); 1050