1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * nct7904.c - driver for Nuvoton NCT7904D. 4 * 5 * Copyright (c) 2015 Kontron 6 * Author: Vadim V. Vlasov <vvlasov@dev.rtsoft.ru> 7 * 8 * Copyright (c) 2019 Advantech 9 * Author: Amy.Shih <amy.shih@advantech.com.tw> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/device.h> 14 #include <linux/init.h> 15 #include <linux/i2c.h> 16 #include <linux/mutex.h> 17 #include <linux/hwmon.h> 18 19 #define VENDOR_ID_REG 0x7A /* Any bank */ 20 #define NUVOTON_ID 0x50 21 #define CHIP_ID_REG 0x7B /* Any bank */ 22 #define NCT7904_ID 0xC5 23 #define DEVICE_ID_REG 0x7C /* Any bank */ 24 25 #define BANK_SEL_REG 0xFF 26 #define BANK_0 0x00 27 #define BANK_1 0x01 28 #define BANK_2 0x02 29 #define BANK_3 0x03 30 #define BANK_4 0x04 31 #define BANK_MAX 0x04 32 33 #define FANIN_MAX 12 /* Counted from 1 */ 34 #define VSEN_MAX 21 /* VSEN1..14, 3VDD, VBAT, V3VSB, 35 LTD (not a voltage), VSEN17..19 */ 36 #define FANCTL_MAX 4 /* Counted from 1 */ 37 #define TCPU_MAX 8 /* Counted from 1 */ 38 #define TEMP_MAX 4 /* Counted from 1 */ 39 40 #define VT_ADC_CTRL0_REG 0x20 /* Bank 0 */ 41 #define VT_ADC_CTRL1_REG 0x21 /* Bank 0 */ 42 #define VT_ADC_CTRL2_REG 0x22 /* Bank 0 */ 43 #define FANIN_CTRL0_REG 0x24 44 #define FANIN_CTRL1_REG 0x25 45 #define DTS_T_CTRL0_REG 0x26 46 #define DTS_T_CTRL1_REG 0x27 47 #define VT_ADC_MD_REG 0x2E 48 49 #define VSEN1_HV_REG 0x40 /* Bank 0; 2 regs (HV/LV) per sensor */ 50 #define TEMP_CH1_HV_REG 0x42 /* Bank 0; same as VSEN2_HV */ 51 #define LTD_HV_REG 0x62 /* Bank 0; 2 regs in VSEN range */ 52 #define FANIN1_HV_REG 0x80 /* Bank 0; 2 regs (HV/LV) per sensor */ 53 #define T_CPU1_HV_REG 0xA0 /* Bank 0; 2 regs (HV/LV) per sensor */ 54 55 #define PRTS_REG 0x03 /* Bank 2 */ 56 #define PFE_REG 0x00 /* Bank 2; PECI Function Enable */ 57 #define TSI_CTRL_REG 0x50 /* Bank 2; TSI Control Register */ 58 #define FANCTL1_FMR_REG 0x00 /* Bank 3; 1 reg per channel */ 59 #define FANCTL1_OUT_REG 0x10 /* Bank 3; 1 reg per channel */ 60 61 static const unsigned short normal_i2c[] = { 62 0x2d, 0x2e, I2C_CLIENT_END 63 }; 64 65 struct nct7904_data { 66 struct i2c_client *client; 67 struct mutex bank_lock; 68 int bank_sel; 69 u32 fanin_mask; 70 u32 vsen_mask; 71 u32 tcpu_mask; 72 u8 fan_mode[FANCTL_MAX]; 73 u8 enable_dts; 74 u8 has_dts; 75 }; 76 77 /* Access functions */ 78 static int nct7904_bank_lock(struct nct7904_data *data, unsigned int bank) 79 { 80 int ret; 81 82 mutex_lock(&data->bank_lock); 83 if (data->bank_sel == bank) 84 return 0; 85 ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank); 86 if (ret == 0) 87 data->bank_sel = bank; 88 else 89 data->bank_sel = -1; 90 return ret; 91 } 92 93 static inline void nct7904_bank_release(struct nct7904_data *data) 94 { 95 mutex_unlock(&data->bank_lock); 96 } 97 98 /* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */ 99 static int nct7904_read_reg(struct nct7904_data *data, 100 unsigned int bank, unsigned int reg) 101 { 102 struct i2c_client *client = data->client; 103 int ret; 104 105 ret = nct7904_bank_lock(data, bank); 106 if (ret == 0) 107 ret = i2c_smbus_read_byte_data(client, reg); 108 109 nct7904_bank_release(data); 110 return ret; 111 } 112 113 /* 114 * Read 2-byte register. Returns register in big-endian format or 115 * -ERRNO on error. 116 */ 117 static int nct7904_read_reg16(struct nct7904_data *data, 118 unsigned int bank, unsigned int reg) 119 { 120 struct i2c_client *client = data->client; 121 int ret, hi; 122 123 ret = nct7904_bank_lock(data, bank); 124 if (ret == 0) { 125 ret = i2c_smbus_read_byte_data(client, reg); 126 if (ret >= 0) { 127 hi = ret; 128 ret = i2c_smbus_read_byte_data(client, reg + 1); 129 if (ret >= 0) 130 ret |= hi << 8; 131 } 132 } 133 134 nct7904_bank_release(data); 135 return ret; 136 } 137 138 /* Write 1-byte register. Returns 0 or -ERRNO on error. */ 139 static int nct7904_write_reg(struct nct7904_data *data, 140 unsigned int bank, unsigned int reg, u8 val) 141 { 142 struct i2c_client *client = data->client; 143 int ret; 144 145 ret = nct7904_bank_lock(data, bank); 146 if (ret == 0) 147 ret = i2c_smbus_write_byte_data(client, reg, val); 148 149 nct7904_bank_release(data); 150 return ret; 151 } 152 153 static int nct7904_read_fan(struct device *dev, u32 attr, int channel, 154 long *val) 155 { 156 struct nct7904_data *data = dev_get_drvdata(dev); 157 unsigned int cnt, rpm; 158 int ret; 159 160 switch (attr) { 161 case hwmon_fan_input: 162 ret = nct7904_read_reg16(data, BANK_0, 163 FANIN1_HV_REG + channel * 2); 164 if (ret < 0) 165 return ret; 166 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f); 167 if (cnt == 0x1fff) 168 rpm = 0; 169 else 170 rpm = 1350000 / cnt; 171 *val = rpm; 172 return 0; 173 default: 174 return -EOPNOTSUPP; 175 } 176 } 177 178 static umode_t nct7904_fan_is_visible(const void *_data, u32 attr, int channel) 179 { 180 const struct nct7904_data *data = _data; 181 182 if (attr == hwmon_fan_input && data->fanin_mask & (1 << channel)) 183 return 0444; 184 return 0; 185 } 186 187 static u8 nct7904_chan_to_index[] = { 188 0, /* Not used */ 189 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 190 18, 19, 20, 16 191 }; 192 193 static int nct7904_read_in(struct device *dev, u32 attr, int channel, 194 long *val) 195 { 196 struct nct7904_data *data = dev_get_drvdata(dev); 197 int ret, volt, index; 198 199 index = nct7904_chan_to_index[channel]; 200 201 switch (attr) { 202 case hwmon_in_input: 203 ret = nct7904_read_reg16(data, BANK_0, 204 VSEN1_HV_REG + index * 2); 205 if (ret < 0) 206 return ret; 207 volt = ((ret & 0xff00) >> 5) | (ret & 0x7); 208 if (index < 14) 209 volt *= 2; /* 0.002V scale */ 210 else 211 volt *= 6; /* 0.006V scale */ 212 *val = volt; 213 return 0; 214 default: 215 return -EOPNOTSUPP; 216 } 217 } 218 219 static umode_t nct7904_in_is_visible(const void *_data, u32 attr, int channel) 220 { 221 const struct nct7904_data *data = _data; 222 int index = nct7904_chan_to_index[channel]; 223 224 if (channel > 0 && attr == hwmon_in_input && 225 (data->vsen_mask & BIT(index))) 226 return 0444; 227 228 return 0; 229 } 230 231 static int nct7904_read_temp(struct device *dev, u32 attr, int channel, 232 long *val) 233 { 234 struct nct7904_data *data = dev_get_drvdata(dev); 235 int ret, temp; 236 237 switch (attr) { 238 case hwmon_temp_input: 239 if (channel == 4) 240 ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG); 241 else if (channel < 5) 242 ret = nct7904_read_reg16(data, BANK_0, 243 TEMP_CH1_HV_REG + channel * 4); 244 else 245 ret = nct7904_read_reg16(data, BANK_0, 246 T_CPU1_HV_REG + (channel - 5) 247 * 2); 248 if (ret < 0) 249 return ret; 250 temp = ((ret & 0xff00) >> 5) | (ret & 0x7); 251 *val = sign_extend32(temp, 10) * 125; 252 return 0; 253 default: 254 return -EOPNOTSUPP; 255 } 256 } 257 258 static umode_t nct7904_temp_is_visible(const void *_data, u32 attr, int channel) 259 { 260 const struct nct7904_data *data = _data; 261 262 if (attr == hwmon_temp_input) { 263 if (channel < 5) { 264 if (data->tcpu_mask & BIT(channel)) 265 return 0444; 266 } else { 267 if (data->has_dts & BIT(channel - 5)) 268 return 0444; 269 } 270 } 271 272 return 0; 273 } 274 275 static int nct7904_read_pwm(struct device *dev, u32 attr, int channel, 276 long *val) 277 { 278 struct nct7904_data *data = dev_get_drvdata(dev); 279 int ret; 280 281 switch (attr) { 282 case hwmon_pwm_input: 283 ret = nct7904_read_reg(data, BANK_3, FANCTL1_OUT_REG + channel); 284 if (ret < 0) 285 return ret; 286 *val = ret; 287 return 0; 288 case hwmon_pwm_enable: 289 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + channel); 290 if (ret < 0) 291 return ret; 292 293 *val = ret ? 2 : 1; 294 return 0; 295 default: 296 return -EOPNOTSUPP; 297 } 298 } 299 300 static int nct7904_write_pwm(struct device *dev, u32 attr, int channel, 301 long val) 302 { 303 struct nct7904_data *data = dev_get_drvdata(dev); 304 int ret; 305 306 switch (attr) { 307 case hwmon_pwm_input: 308 if (val < 0 || val > 255) 309 return -EINVAL; 310 ret = nct7904_write_reg(data, BANK_3, FANCTL1_OUT_REG + channel, 311 val); 312 return ret; 313 case hwmon_pwm_enable: 314 if (val < 1 || val > 2 || 315 (val == 2 && !data->fan_mode[channel])) 316 return -EINVAL; 317 ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + channel, 318 val == 2 ? data->fan_mode[channel] : 0); 319 return ret; 320 default: 321 return -EOPNOTSUPP; 322 } 323 } 324 325 static umode_t nct7904_pwm_is_visible(const void *_data, u32 attr, int channel) 326 { 327 switch (attr) { 328 case hwmon_pwm_input: 329 case hwmon_pwm_enable: 330 return 0644; 331 default: 332 return 0; 333 } 334 } 335 336 static int nct7904_read(struct device *dev, enum hwmon_sensor_types type, 337 u32 attr, int channel, long *val) 338 { 339 switch (type) { 340 case hwmon_in: 341 return nct7904_read_in(dev, attr, channel, val); 342 case hwmon_fan: 343 return nct7904_read_fan(dev, attr, channel, val); 344 case hwmon_pwm: 345 return nct7904_read_pwm(dev, attr, channel, val); 346 case hwmon_temp: 347 return nct7904_read_temp(dev, attr, channel, val); 348 default: 349 return -EOPNOTSUPP; 350 } 351 } 352 353 static int nct7904_write(struct device *dev, enum hwmon_sensor_types type, 354 u32 attr, int channel, long val) 355 { 356 switch (type) { 357 case hwmon_pwm: 358 return nct7904_write_pwm(dev, attr, channel, val); 359 default: 360 return -EOPNOTSUPP; 361 } 362 } 363 364 static umode_t nct7904_is_visible(const void *data, 365 enum hwmon_sensor_types type, 366 u32 attr, int channel) 367 { 368 switch (type) { 369 case hwmon_in: 370 return nct7904_in_is_visible(data, attr, channel); 371 case hwmon_fan: 372 return nct7904_fan_is_visible(data, attr, channel); 373 case hwmon_pwm: 374 return nct7904_pwm_is_visible(data, attr, channel); 375 case hwmon_temp: 376 return nct7904_temp_is_visible(data, attr, channel); 377 default: 378 return 0; 379 } 380 } 381 382 /* Return 0 if detection is successful, -ENODEV otherwise */ 383 static int nct7904_detect(struct i2c_client *client, 384 struct i2c_board_info *info) 385 { 386 struct i2c_adapter *adapter = client->adapter; 387 388 if (!i2c_check_functionality(adapter, 389 I2C_FUNC_SMBUS_READ_BYTE | 390 I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) 391 return -ENODEV; 392 393 /* Determine the chip type. */ 394 if (i2c_smbus_read_byte_data(client, VENDOR_ID_REG) != NUVOTON_ID || 395 i2c_smbus_read_byte_data(client, CHIP_ID_REG) != NCT7904_ID || 396 (i2c_smbus_read_byte_data(client, DEVICE_ID_REG) & 0xf0) != 0x50 || 397 (i2c_smbus_read_byte_data(client, BANK_SEL_REG) & 0xf8) != 0x00) 398 return -ENODEV; 399 400 strlcpy(info->type, "nct7904", I2C_NAME_SIZE); 401 402 return 0; 403 } 404 405 static const struct hwmon_channel_info *nct7904_info[] = { 406 HWMON_CHANNEL_INFO(in, 407 HWMON_I_INPUT, /* dummy, skipped in is_visible */ 408 HWMON_I_INPUT, 409 HWMON_I_INPUT, 410 HWMON_I_INPUT, 411 HWMON_I_INPUT, 412 HWMON_I_INPUT, 413 HWMON_I_INPUT, 414 HWMON_I_INPUT, 415 HWMON_I_INPUT, 416 HWMON_I_INPUT, 417 HWMON_I_INPUT, 418 HWMON_I_INPUT, 419 HWMON_I_INPUT, 420 HWMON_I_INPUT, 421 HWMON_I_INPUT, 422 HWMON_I_INPUT, 423 HWMON_I_INPUT, 424 HWMON_I_INPUT, 425 HWMON_I_INPUT, 426 HWMON_I_INPUT, 427 HWMON_I_INPUT), 428 HWMON_CHANNEL_INFO(fan, 429 HWMON_F_INPUT, 430 HWMON_F_INPUT, 431 HWMON_F_INPUT, 432 HWMON_F_INPUT, 433 HWMON_F_INPUT, 434 HWMON_F_INPUT, 435 HWMON_F_INPUT, 436 HWMON_F_INPUT), 437 HWMON_CHANNEL_INFO(pwm, 438 HWMON_PWM_INPUT | HWMON_PWM_ENABLE, 439 HWMON_PWM_INPUT | HWMON_PWM_ENABLE, 440 HWMON_PWM_INPUT | HWMON_PWM_ENABLE, 441 HWMON_PWM_INPUT | HWMON_PWM_ENABLE), 442 HWMON_CHANNEL_INFO(temp, 443 HWMON_T_INPUT, 444 HWMON_T_INPUT, 445 HWMON_T_INPUT, 446 HWMON_T_INPUT, 447 HWMON_T_INPUT, 448 HWMON_T_INPUT, 449 HWMON_T_INPUT, 450 HWMON_T_INPUT, 451 HWMON_T_INPUT), 452 NULL 453 }; 454 455 static const struct hwmon_ops nct7904_hwmon_ops = { 456 .is_visible = nct7904_is_visible, 457 .read = nct7904_read, 458 .write = nct7904_write, 459 }; 460 461 static const struct hwmon_chip_info nct7904_chip_info = { 462 .ops = &nct7904_hwmon_ops, 463 .info = nct7904_info, 464 }; 465 466 static int nct7904_probe(struct i2c_client *client, 467 const struct i2c_device_id *id) 468 { 469 struct nct7904_data *data; 470 struct device *hwmon_dev; 471 struct device *dev = &client->dev; 472 int ret, i; 473 u32 mask; 474 u8 val, bit; 475 476 data = devm_kzalloc(dev, sizeof(struct nct7904_data), GFP_KERNEL); 477 if (!data) 478 return -ENOMEM; 479 480 data->client = client; 481 mutex_init(&data->bank_lock); 482 data->bank_sel = -1; 483 484 /* Setup sensor groups. */ 485 /* FANIN attributes */ 486 ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG); 487 if (ret < 0) 488 return ret; 489 data->fanin_mask = (ret >> 8) | ((ret & 0xff) << 8); 490 491 /* 492 * VSEN attributes 493 * 494 * Note: voltage sensors overlap with external temperature 495 * sensors. So, if we ever decide to support the latter 496 * we will have to adjust 'vsen_mask' accordingly. 497 */ 498 mask = 0; 499 ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG); 500 if (ret >= 0) 501 mask = (ret >> 8) | ((ret & 0xff) << 8); 502 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG); 503 if (ret >= 0) 504 mask |= (ret << 16); 505 data->vsen_mask = mask; 506 507 /* CPU_TEMP attributes */ 508 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG); 509 if (ret < 0) 510 return ret; 511 512 if ((ret & 0x6) == 0x6) 513 data->tcpu_mask |= 1; /* TR1 */ 514 if ((ret & 0x18) == 0x18) 515 data->tcpu_mask |= 2; /* TR2 */ 516 if ((ret & 0x20) == 0x20) 517 data->tcpu_mask |= 4; /* TR3 */ 518 if ((ret & 0x80) == 0x80) 519 data->tcpu_mask |= 8; /* TR4 */ 520 521 /* LTD */ 522 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG); 523 if (ret < 0) 524 return ret; 525 if ((ret & 0x02) == 0x02) 526 data->tcpu_mask |= 0x10; 527 528 /* Multi-Function detecting for Volt and TR/TD */ 529 ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG); 530 if (ret < 0) 531 return ret; 532 533 for (i = 0; i < 4; i++) { 534 val = (ret & (0x03 << i)) >> (i * 2); 535 bit = (1 << i); 536 if (val == 0) 537 data->tcpu_mask &= ~bit; 538 } 539 540 /* PECI */ 541 ret = nct7904_read_reg(data, BANK_2, PFE_REG); 542 if (ret < 0) 543 return ret; 544 if (ret & 0x80) { 545 data->enable_dts = 1; /* Enable DTS & PECI */ 546 } else { 547 ret = nct7904_read_reg(data, BANK_2, TSI_CTRL_REG); 548 if (ret < 0) 549 return ret; 550 if (ret & 0x80) 551 data->enable_dts = 0x3; /* Enable DTS & TSI */ 552 } 553 554 /* Check DTS enable status */ 555 if (data->enable_dts) { 556 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG); 557 if (ret < 0) 558 return ret; 559 data->has_dts = ret & 0xF; 560 if (data->enable_dts & 0x2) { 561 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG); 562 if (ret < 0) 563 return ret; 564 data->has_dts |= (ret & 0xF) << 4; 565 } 566 } 567 568 for (i = 0; i < FANCTL_MAX; i++) { 569 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + i); 570 if (ret < 0) 571 return ret; 572 data->fan_mode[i] = ret; 573 } 574 575 hwmon_dev = 576 devm_hwmon_device_register_with_info(dev, client->name, data, 577 &nct7904_chip_info, NULL); 578 return PTR_ERR_OR_ZERO(hwmon_dev); 579 } 580 581 static const struct i2c_device_id nct7904_id[] = { 582 {"nct7904", 0}, 583 {} 584 }; 585 MODULE_DEVICE_TABLE(i2c, nct7904_id); 586 587 static struct i2c_driver nct7904_driver = { 588 .class = I2C_CLASS_HWMON, 589 .driver = { 590 .name = "nct7904", 591 }, 592 .probe = nct7904_probe, 593 .id_table = nct7904_id, 594 .detect = nct7904_detect, 595 .address_list = normal_i2c, 596 }; 597 598 module_i2c_driver(nct7904_driver); 599 600 MODULE_AUTHOR("Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>"); 601 MODULE_DESCRIPTION("Hwmon driver for NUVOTON NCT7904"); 602 MODULE_LICENSE("GPL"); 603