1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 #ifndef __HWMON_NCT6775_H__ 3 #define __HWMON_NCT6775_H__ 4 5 #include <linux/types.h> 6 7 enum kinds { nct6106, nct6116, nct6775, nct6776, nct6779, nct6791, nct6792, 8 nct6793, nct6795, nct6796, nct6797, nct6798, nct6799 }; 9 enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 }; 10 11 #define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/ 12 #define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */ 13 #define NUM_TSI_TEMP 8 /* Max number of TSI temp register pairs */ 14 15 #define NUM_REG_ALARM 7 /* Max number of alarm registers */ 16 #define NUM_REG_BEEP 5 /* Max number of beep registers */ 17 18 #define NUM_FAN 7 19 20 struct nct6775_data { 21 int addr; /* IO base of hw monitor block */ 22 int sioreg; /* SIO register address */ 23 enum kinds kind; 24 const char *name; 25 26 const struct attribute_group *groups[7]; 27 u8 num_groups; 28 29 u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst, 30 * 3=temp_crit, 4=temp_lcrit 31 */ 32 u8 temp_src[NUM_TEMP]; 33 u16 reg_temp_config[NUM_TEMP]; 34 const char * const *temp_label; 35 u32 temp_mask; 36 u32 virt_temp_mask; 37 38 u16 REG_CONFIG; 39 u16 REG_VBAT; 40 u16 REG_DIODE; 41 u8 DIODE_MASK; 42 43 const s8 *ALARM_BITS; 44 const s8 *BEEP_BITS; 45 46 const u16 *REG_VIN; 47 const u16 *REG_IN_MINMAX[2]; 48 49 const u16 *REG_TARGET; 50 const u16 *REG_FAN; 51 const u16 *REG_FAN_MODE; 52 const u16 *REG_FAN_MIN; 53 const u16 *REG_FAN_PULSES; 54 const u16 *FAN_PULSE_SHIFT; 55 const u16 *REG_FAN_TIME[3]; 56 57 const u16 *REG_TOLERANCE_H; 58 59 const u8 *REG_PWM_MODE; 60 const u8 *PWM_MODE_MASK; 61 62 const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor, 63 * [3]=pwm_max, [4]=pwm_step, 64 * [5]=weight_duty_step, [6]=weight_duty_base 65 */ 66 const u16 *REG_PWM_READ; 67 68 const u16 *REG_CRITICAL_PWM_ENABLE; 69 u8 CRITICAL_PWM_ENABLE_MASK; 70 const u16 *REG_CRITICAL_PWM; 71 72 const u16 *REG_AUTO_TEMP; 73 const u16 *REG_AUTO_PWM; 74 75 const u16 *REG_CRITICAL_TEMP; 76 const u16 *REG_CRITICAL_TEMP_TOLERANCE; 77 78 const u16 *REG_TEMP_SOURCE; /* temp register sources */ 79 const u16 *REG_TEMP_SEL; 80 const u16 *REG_WEIGHT_TEMP_SEL; 81 const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */ 82 83 const u16 *REG_TEMP_OFFSET; 84 85 const u16 *REG_ALARM; 86 const u16 *REG_BEEP; 87 88 const u16 *REG_TSI_TEMP; 89 90 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg); 91 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg); 92 93 struct mutex update_lock; 94 bool valid; /* true if following fields are valid */ 95 unsigned long last_updated; /* In jiffies */ 96 97 /* Register values */ 98 u8 bank; /* current register bank */ 99 u8 in_num; /* number of in inputs we have */ 100 u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */ 101 const u16 *scale_in; /* internal scaling factors */ 102 unsigned int rpm[NUM_FAN]; 103 u16 fan_min[NUM_FAN]; 104 u8 fan_pulses[NUM_FAN]; 105 u8 fan_div[NUM_FAN]; 106 u8 has_pwm; 107 u8 has_fan; /* some fan inputs can be disabled */ 108 u8 has_fan_min; /* some fans don't have min register */ 109 bool has_fan_div; 110 111 u8 num_temp_alarms; /* 2, 3, or 6 */ 112 u8 num_temp_beeps; /* 2, 3, or 6 */ 113 u8 temp_fixed_num; /* 3 or 6 */ 114 u8 temp_type[NUM_TEMP_FIXED]; 115 s8 temp_offset[NUM_TEMP_FIXED]; 116 s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst, 117 * 3=temp_crit, 4=temp_lcrit 118 */ 119 s16 tsi_temp[NUM_TSI_TEMP]; 120 u64 alarms; 121 u64 beeps; 122 123 u8 pwm_num; /* number of pwm */ 124 u8 pwm_mode[NUM_FAN]; /* 0->DC variable voltage, 125 * 1->PWM variable duty cycle 126 */ 127 enum pwm_enable pwm_enable[NUM_FAN]; 128 /* 0->off 129 * 1->manual 130 * 2->thermal cruise mode (also called SmartFan I) 131 * 3->fan speed cruise mode 132 * 4->SmartFan III 133 * 5->enhanced variable thermal cruise (SmartFan IV) 134 */ 135 u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor, 136 * [3]=pwm_max, [4]=pwm_step, 137 * [5]=weight_duty_step, [6]=weight_duty_base 138 */ 139 140 u8 target_temp[NUM_FAN]; 141 u8 target_temp_mask; 142 u32 target_speed[NUM_FAN]; 143 u32 target_speed_tolerance[NUM_FAN]; 144 u8 speed_tolerance_limit; 145 146 u8 temp_tolerance[2][NUM_FAN]; 147 u8 tolerance_mask; 148 149 u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */ 150 151 /* Automatic fan speed control registers */ 152 int auto_pwm_num; 153 u8 auto_pwm[NUM_FAN][7]; 154 u8 auto_temp[NUM_FAN][7]; 155 u8 pwm_temp_sel[NUM_FAN]; 156 u8 pwm_weight_temp_sel[NUM_FAN]; 157 u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol, 158 * 2->temp_base 159 */ 160 161 u8 vid; 162 u8 vrm; 163 164 bool have_vid; 165 166 u16 have_temp; 167 u16 have_temp_fixed; 168 u16 have_tsi_temp; 169 u16 have_in; 170 171 /* Remember extra register values over suspend/resume */ 172 u8 vbat; 173 u8 fandiv1; 174 u8 fandiv2; 175 u8 sio_reg_enable; 176 177 struct regmap *regmap; 178 bool read_only; 179 180 /* driver-specific (platform, i2c) initialization hook and data */ 181 int (*driver_init)(struct nct6775_data *data); 182 void *driver_data; 183 }; 184 185 static inline int nct6775_read_value(struct nct6775_data *data, u16 reg, u16 *value) 186 { 187 unsigned int tmp; 188 int ret = regmap_read(data->regmap, reg, &tmp); 189 190 if (!ret) 191 *value = tmp; 192 return ret; 193 } 194 195 static inline int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value) 196 { 197 return regmap_write(data->regmap, reg, value); 198 } 199 200 struct nct6775_data *nct6775_update_device(struct device *dev); 201 202 bool nct6775_reg_is_word_sized(struct nct6775_data *data, u16 reg); 203 int nct6775_probe(struct device *dev, struct nct6775_data *data, 204 const struct regmap_config *regmapcfg); 205 206 ssize_t nct6775_show_alarm(struct device *dev, struct device_attribute *attr, char *buf); 207 ssize_t nct6775_show_beep(struct device *dev, struct device_attribute *attr, char *buf); 208 ssize_t nct6775_store_beep(struct device *dev, struct device_attribute *attr, const char *buf, 209 size_t count); 210 211 static inline int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value) 212 { 213 if (!nct6775_reg_is_word_sized(data, reg)) 214 value >>= 8; 215 return nct6775_write_value(data, reg, value); 216 } 217 218 static inline umode_t nct6775_attr_mode(struct nct6775_data *data, struct attribute *attr) 219 { 220 return data->read_only ? (attr->mode & ~0222) : attr->mode; 221 } 222 223 static inline int 224 nct6775_add_attr_group(struct nct6775_data *data, const struct attribute_group *group) 225 { 226 /* Need to leave a NULL terminator at the end of data->groups */ 227 if (data->num_groups == ARRAY_SIZE(data->groups) - 1) 228 return -ENOBUFS; 229 230 data->groups[data->num_groups++] = group; 231 return 0; 232 } 233 234 #define NCT6775_REG_BANK 0x4E 235 #define NCT6775_REG_CONFIG 0x40 236 237 #define NCT6775_REG_FANDIV1 0x506 238 #define NCT6775_REG_FANDIV2 0x507 239 240 #define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28 241 242 #define FAN_ALARM_BASE 16 243 #define TEMP_ALARM_BASE 24 244 #define INTRUSION_ALARM_BASE 30 245 #define BEEP_ENABLE_BASE 15 246 247 /* 248 * Not currently used: 249 * REG_MAN_ID has the value 0x5ca3 for all supported chips. 250 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model. 251 * REG_MAN_ID is at port 0x4f 252 * REG_CHIP_ID is at port 0x58 253 */ 254 255 #endif /* __HWMON_NCT6775_H__ */ 256