1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * nct6775 - Platform driver for the hardware monitoring 4 * functionality of Nuvoton NCT677x Super-I/O chips 5 * 6 * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/acpi.h> 12 #include <linux/dmi.h> 13 #include <linux/hwmon-sysfs.h> 14 #include <linux/hwmon-vid.h> 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 21 #include "nct6775.h" 22 23 enum sensor_access { access_direct, access_asuswmi }; 24 25 static const char * const nct6775_sio_names[] __initconst = { 26 "NCT6106D", 27 "NCT6116D", 28 "NCT6775F", 29 "NCT6776D/F", 30 "NCT6779D", 31 "NCT6791D", 32 "NCT6792D", 33 "NCT6793D", 34 "NCT6795D", 35 "NCT6796D", 36 "NCT6797D", 37 "NCT6798D", 38 }; 39 40 static unsigned short force_id; 41 module_param(force_id, ushort, 0); 42 MODULE_PARM_DESC(force_id, "Override the detected device ID"); 43 44 static unsigned short fan_debounce; 45 module_param(fan_debounce, ushort, 0); 46 MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal"); 47 48 #define DRVNAME "nct6775" 49 50 #define NCT6775_PORT_CHIPID 0x58 51 52 /* 53 * ISA constants 54 */ 55 56 #define IOREGION_ALIGNMENT (~7) 57 #define IOREGION_OFFSET 5 58 #define IOREGION_LENGTH 2 59 #define ADDR_REG_OFFSET 0 60 #define DATA_REG_OFFSET 1 61 62 /* 63 * Super-I/O constants and functions 64 */ 65 66 #define NCT6775_LD_ACPI 0x0a 67 #define NCT6775_LD_HWM 0x0b 68 #define NCT6775_LD_VID 0x0d 69 #define NCT6775_LD_12 0x12 70 71 #define SIO_REG_LDSEL 0x07 /* Logical device select */ 72 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */ 73 #define SIO_REG_ENABLE 0x30 /* Logical device enable */ 74 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */ 75 76 #define SIO_NCT6106_ID 0xc450 77 #define SIO_NCT6116_ID 0xd280 78 #define SIO_NCT6775_ID 0xb470 79 #define SIO_NCT6776_ID 0xc330 80 #define SIO_NCT6779_ID 0xc560 81 #define SIO_NCT6791_ID 0xc800 82 #define SIO_NCT6792_ID 0xc910 83 #define SIO_NCT6793_ID 0xd120 84 #define SIO_NCT6795_ID 0xd350 85 #define SIO_NCT6796_ID 0xd420 86 #define SIO_NCT6797_ID 0xd450 87 #define SIO_NCT6798_ID 0xd428 88 #define SIO_ID_MASK 0xFFF8 89 90 /* 91 * Control registers 92 */ 93 #define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0 94 95 struct nct6775_sio_data { 96 int sioreg; 97 int ld; 98 enum kinds kind; 99 enum sensor_access access; 100 101 /* superio_() callbacks */ 102 void (*sio_outb)(struct nct6775_sio_data *sio_data, int reg, int val); 103 int (*sio_inb)(struct nct6775_sio_data *sio_data, int reg); 104 void (*sio_select)(struct nct6775_sio_data *sio_data, int ld); 105 int (*sio_enter)(struct nct6775_sio_data *sio_data); 106 void (*sio_exit)(struct nct6775_sio_data *sio_data); 107 }; 108 109 #define ASUSWMI_METHOD "WMBD" 110 #define ASUSWMI_METHODID_RSIO 0x5253494F 111 #define ASUSWMI_METHODID_WSIO 0x5753494F 112 #define ASUSWMI_METHODID_RHWM 0x5248574D 113 #define ASUSWMI_METHODID_WHWM 0x5748574D 114 #define ASUSWMI_UNSUPPORTED_METHOD 0xFFFFFFFE 115 #define ASUSWMI_DEVICE_HID "PNP0C14" 116 #define ASUSWMI_DEVICE_UID "ASUSWMI" 117 #define ASUSMSI_DEVICE_UID "AsusMbSwInterface" 118 119 #if IS_ENABLED(CONFIG_ACPI) 120 /* 121 * ASUS boards have only one device with WMI "WMBD" method and have provided 122 * access to only one SuperIO chip at 0x0290. 123 */ 124 static struct acpi_device *asus_acpi_dev; 125 #endif 126 127 static int nct6775_asuswmi_evaluate_method(u32 method_id, u8 bank, u8 reg, u8 val, u32 *retval) 128 { 129 #if IS_ENABLED(CONFIG_ACPI) 130 acpi_handle handle = acpi_device_handle(asus_acpi_dev); 131 u32 args = bank | (reg << 8) | (val << 16); 132 struct acpi_object_list input; 133 union acpi_object params[3]; 134 unsigned long long result; 135 acpi_status status; 136 137 params[0].type = ACPI_TYPE_INTEGER; 138 params[0].integer.value = 0; 139 params[1].type = ACPI_TYPE_INTEGER; 140 params[1].integer.value = method_id; 141 params[2].type = ACPI_TYPE_BUFFER; 142 params[2].buffer.length = sizeof(args); 143 params[2].buffer.pointer = (void *)&args; 144 input.count = 3; 145 input.pointer = params; 146 147 status = acpi_evaluate_integer(handle, ASUSWMI_METHOD, &input, &result); 148 if (ACPI_FAILURE(status)) 149 return -EIO; 150 151 if (retval) 152 *retval = (u32)result & 0xFFFFFFFF; 153 154 return 0; 155 #else 156 return -EOPNOTSUPP; 157 #endif 158 } 159 160 static inline int nct6775_asuswmi_write(u8 bank, u8 reg, u8 val) 161 { 162 return nct6775_asuswmi_evaluate_method(ASUSWMI_METHODID_WHWM, bank, 163 reg, val, NULL); 164 } 165 166 static inline int nct6775_asuswmi_read(u8 bank, u8 reg, u8 *val) 167 { 168 u32 ret, tmp = 0; 169 170 ret = nct6775_asuswmi_evaluate_method(ASUSWMI_METHODID_RHWM, bank, 171 reg, 0, &tmp); 172 *val = tmp; 173 return ret; 174 } 175 176 static int superio_wmi_inb(struct nct6775_sio_data *sio_data, int reg) 177 { 178 int tmp = 0; 179 180 nct6775_asuswmi_evaluate_method(ASUSWMI_METHODID_RSIO, sio_data->ld, 181 reg, 0, &tmp); 182 return tmp; 183 } 184 185 static void superio_wmi_outb(struct nct6775_sio_data *sio_data, int reg, int val) 186 { 187 nct6775_asuswmi_evaluate_method(ASUSWMI_METHODID_WSIO, sio_data->ld, 188 reg, val, NULL); 189 } 190 191 static void superio_wmi_select(struct nct6775_sio_data *sio_data, int ld) 192 { 193 sio_data->ld = ld; 194 } 195 196 static int superio_wmi_enter(struct nct6775_sio_data *sio_data) 197 { 198 return 0; 199 } 200 201 static void superio_wmi_exit(struct nct6775_sio_data *sio_data) 202 { 203 } 204 205 static void superio_outb(struct nct6775_sio_data *sio_data, int reg, int val) 206 { 207 int ioreg = sio_data->sioreg; 208 209 outb(reg, ioreg); 210 outb(val, ioreg + 1); 211 } 212 213 static int superio_inb(struct nct6775_sio_data *sio_data, int reg) 214 { 215 int ioreg = sio_data->sioreg; 216 217 outb(reg, ioreg); 218 return inb(ioreg + 1); 219 } 220 221 static void superio_select(struct nct6775_sio_data *sio_data, int ld) 222 { 223 int ioreg = sio_data->sioreg; 224 225 outb(SIO_REG_LDSEL, ioreg); 226 outb(ld, ioreg + 1); 227 } 228 229 static int superio_enter(struct nct6775_sio_data *sio_data) 230 { 231 int ioreg = sio_data->sioreg; 232 233 /* 234 * Try to reserve <ioreg> and <ioreg + 1> for exclusive access. 235 */ 236 if (!request_muxed_region(ioreg, 2, DRVNAME)) 237 return -EBUSY; 238 239 outb(0x87, ioreg); 240 outb(0x87, ioreg); 241 242 return 0; 243 } 244 245 static void superio_exit(struct nct6775_sio_data *sio_data) 246 { 247 int ioreg = sio_data->sioreg; 248 249 outb(0xaa, ioreg); 250 outb(0x02, ioreg); 251 outb(0x02, ioreg + 1); 252 release_region(ioreg, 2); 253 } 254 255 static inline void nct6775_wmi_set_bank(struct nct6775_data *data, u16 reg) 256 { 257 u8 bank = reg >> 8; 258 259 data->bank = bank; 260 } 261 262 static int nct6775_wmi_reg_read(void *ctx, unsigned int reg, unsigned int *val) 263 { 264 struct nct6775_data *data = ctx; 265 int err, word_sized = nct6775_reg_is_word_sized(data, reg); 266 u8 tmp = 0; 267 u16 res; 268 269 nct6775_wmi_set_bank(data, reg); 270 271 err = nct6775_asuswmi_read(data->bank, reg & 0xff, &tmp); 272 if (err) 273 return err; 274 275 res = tmp; 276 if (word_sized) { 277 err = nct6775_asuswmi_read(data->bank, (reg & 0xff) + 1, &tmp); 278 if (err) 279 return err; 280 281 res = (res << 8) + tmp; 282 } 283 *val = res; 284 return 0; 285 } 286 287 static int nct6775_wmi_reg_write(void *ctx, unsigned int reg, unsigned int value) 288 { 289 struct nct6775_data *data = ctx; 290 int res, word_sized = nct6775_reg_is_word_sized(data, reg); 291 292 nct6775_wmi_set_bank(data, reg); 293 294 if (word_sized) { 295 res = nct6775_asuswmi_write(data->bank, reg & 0xff, value >> 8); 296 if (res) 297 return res; 298 299 res = nct6775_asuswmi_write(data->bank, (reg & 0xff) + 1, value); 300 } else { 301 res = nct6775_asuswmi_write(data->bank, reg & 0xff, value); 302 } 303 304 return res; 305 } 306 307 /* 308 * On older chips, only registers 0x50-0x5f are banked. 309 * On more recent chips, all registers are banked. 310 * Assume that is the case and set the bank number for each access. 311 * Cache the bank number so it only needs to be set if it changes. 312 */ 313 static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg) 314 { 315 u8 bank = reg >> 8; 316 317 if (data->bank != bank) { 318 outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET); 319 outb_p(bank, data->addr + DATA_REG_OFFSET); 320 data->bank = bank; 321 } 322 } 323 324 static int nct6775_reg_read(void *ctx, unsigned int reg, unsigned int *val) 325 { 326 struct nct6775_data *data = ctx; 327 int word_sized = nct6775_reg_is_word_sized(data, reg); 328 329 nct6775_set_bank(data, reg); 330 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); 331 *val = inb_p(data->addr + DATA_REG_OFFSET); 332 if (word_sized) { 333 outb_p((reg & 0xff) + 1, 334 data->addr + ADDR_REG_OFFSET); 335 *val = (*val << 8) + inb_p(data->addr + DATA_REG_OFFSET); 336 } 337 return 0; 338 } 339 340 static int nct6775_reg_write(void *ctx, unsigned int reg, unsigned int value) 341 { 342 struct nct6775_data *data = ctx; 343 int word_sized = nct6775_reg_is_word_sized(data, reg); 344 345 nct6775_set_bank(data, reg); 346 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); 347 if (word_sized) { 348 outb_p(value >> 8, data->addr + DATA_REG_OFFSET); 349 outb_p((reg & 0xff) + 1, 350 data->addr + ADDR_REG_OFFSET); 351 } 352 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET); 353 return 0; 354 } 355 356 static void nct6791_enable_io_mapping(struct nct6775_sio_data *sio_data) 357 { 358 int val; 359 360 val = sio_data->sio_inb(sio_data, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE); 361 if (val & 0x10) { 362 pr_info("Enabling hardware monitor logical device mappings.\n"); 363 sio_data->sio_outb(sio_data, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE, 364 val & ~0x10); 365 } 366 } 367 368 static int nct6775_suspend(struct device *dev) 369 { 370 int err; 371 u16 tmp; 372 struct nct6775_data *data = nct6775_update_device(dev); 373 374 if (IS_ERR(data)) 375 return PTR_ERR(data); 376 377 mutex_lock(&data->update_lock); 378 err = nct6775_read_value(data, data->REG_VBAT, &tmp); 379 if (err) 380 goto out; 381 data->vbat = tmp; 382 if (data->kind == nct6775) { 383 err = nct6775_read_value(data, NCT6775_REG_FANDIV1, &tmp); 384 if (err) 385 goto out; 386 data->fandiv1 = tmp; 387 388 err = nct6775_read_value(data, NCT6775_REG_FANDIV2, &tmp); 389 if (err) 390 goto out; 391 data->fandiv2 = tmp; 392 } 393 out: 394 mutex_unlock(&data->update_lock); 395 396 return err; 397 } 398 399 static int nct6775_resume(struct device *dev) 400 { 401 struct nct6775_data *data = dev_get_drvdata(dev); 402 struct nct6775_sio_data *sio_data = dev_get_platdata(dev); 403 int i, j, err = 0; 404 u8 reg; 405 406 mutex_lock(&data->update_lock); 407 data->bank = 0xff; /* Force initial bank selection */ 408 409 err = sio_data->sio_enter(sio_data); 410 if (err) 411 goto abort; 412 413 sio_data->sio_select(sio_data, NCT6775_LD_HWM); 414 reg = sio_data->sio_inb(sio_data, SIO_REG_ENABLE); 415 if (reg != data->sio_reg_enable) 416 sio_data->sio_outb(sio_data, SIO_REG_ENABLE, data->sio_reg_enable); 417 418 if (data->kind == nct6791 || data->kind == nct6792 || 419 data->kind == nct6793 || data->kind == nct6795 || 420 data->kind == nct6796 || data->kind == nct6797 || 421 data->kind == nct6798) 422 nct6791_enable_io_mapping(sio_data); 423 424 sio_data->sio_exit(sio_data); 425 426 /* Restore limits */ 427 for (i = 0; i < data->in_num; i++) { 428 if (!(data->have_in & BIT(i))) 429 continue; 430 431 err = nct6775_write_value(data, data->REG_IN_MINMAX[0][i], data->in[i][1]); 432 if (err) 433 goto abort; 434 err = nct6775_write_value(data, data->REG_IN_MINMAX[1][i], data->in[i][2]); 435 if (err) 436 goto abort; 437 } 438 439 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) { 440 if (!(data->has_fan_min & BIT(i))) 441 continue; 442 443 err = nct6775_write_value(data, data->REG_FAN_MIN[i], data->fan_min[i]); 444 if (err) 445 goto abort; 446 } 447 448 for (i = 0; i < NUM_TEMP; i++) { 449 if (!(data->have_temp & BIT(i))) 450 continue; 451 452 for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++) 453 if (data->reg_temp[j][i]) { 454 err = nct6775_write_temp(data, data->reg_temp[j][i], 455 data->temp[j][i]); 456 if (err) 457 goto abort; 458 } 459 } 460 461 /* Restore other settings */ 462 err = nct6775_write_value(data, data->REG_VBAT, data->vbat); 463 if (err) 464 goto abort; 465 if (data->kind == nct6775) { 466 err = nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1); 467 if (err) 468 goto abort; 469 err = nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2); 470 } 471 472 abort: 473 /* Force re-reading all values */ 474 data->valid = false; 475 mutex_unlock(&data->update_lock); 476 477 return err; 478 } 479 480 static DEFINE_SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume); 481 482 static void 483 nct6775_check_fan_inputs(struct nct6775_data *data, struct nct6775_sio_data *sio_data) 484 { 485 bool fan3pin = false, fan4pin = false, fan4min = false; 486 bool fan5pin = false, fan6pin = false, fan7pin = false; 487 bool pwm3pin = false, pwm4pin = false, pwm5pin = false; 488 bool pwm6pin = false, pwm7pin = false; 489 490 /* Store SIO_REG_ENABLE for use during resume */ 491 sio_data->sio_select(sio_data, NCT6775_LD_HWM); 492 data->sio_reg_enable = sio_data->sio_inb(sio_data, SIO_REG_ENABLE); 493 494 /* fan4 and fan5 share some pins with the GPIO and serial flash */ 495 if (data->kind == nct6775) { 496 int cr2c = sio_data->sio_inb(sio_data, 0x2c); 497 498 fan3pin = cr2c & BIT(6); 499 pwm3pin = cr2c & BIT(7); 500 501 /* On NCT6775, fan4 shares pins with the fdc interface */ 502 fan4pin = !(sio_data->sio_inb(sio_data, 0x2A) & 0x80); 503 } else if (data->kind == nct6776) { 504 bool gpok = sio_data->sio_inb(sio_data, 0x27) & 0x80; 505 const char *board_vendor, *board_name; 506 507 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR); 508 board_name = dmi_get_system_info(DMI_BOARD_NAME); 509 510 if (board_name && board_vendor && 511 !strcmp(board_vendor, "ASRock")) { 512 /* 513 * Auxiliary fan monitoring is not enabled on ASRock 514 * Z77 Pro4-M if booted in UEFI Ultra-FastBoot mode. 515 * Observed with BIOS version 2.00. 516 */ 517 if (!strcmp(board_name, "Z77 Pro4-M")) { 518 if ((data->sio_reg_enable & 0xe0) != 0xe0) { 519 data->sio_reg_enable |= 0xe0; 520 sio_data->sio_outb(sio_data, SIO_REG_ENABLE, 521 data->sio_reg_enable); 522 } 523 } 524 } 525 526 if (data->sio_reg_enable & 0x80) 527 fan3pin = gpok; 528 else 529 fan3pin = !(sio_data->sio_inb(sio_data, 0x24) & 0x40); 530 531 if (data->sio_reg_enable & 0x40) 532 fan4pin = gpok; 533 else 534 fan4pin = sio_data->sio_inb(sio_data, 0x1C) & 0x01; 535 536 if (data->sio_reg_enable & 0x20) 537 fan5pin = gpok; 538 else 539 fan5pin = sio_data->sio_inb(sio_data, 0x1C) & 0x02; 540 541 fan4min = fan4pin; 542 pwm3pin = fan3pin; 543 } else if (data->kind == nct6106) { 544 int cr24 = sio_data->sio_inb(sio_data, 0x24); 545 546 fan3pin = !(cr24 & 0x80); 547 pwm3pin = cr24 & 0x08; 548 } else if (data->kind == nct6116) { 549 int cr1a = sio_data->sio_inb(sio_data, 0x1a); 550 int cr1b = sio_data->sio_inb(sio_data, 0x1b); 551 int cr24 = sio_data->sio_inb(sio_data, 0x24); 552 int cr2a = sio_data->sio_inb(sio_data, 0x2a); 553 int cr2b = sio_data->sio_inb(sio_data, 0x2b); 554 int cr2f = sio_data->sio_inb(sio_data, 0x2f); 555 556 fan3pin = !(cr2b & 0x10); 557 fan4pin = (cr2b & 0x80) || // pin 1(2) 558 (!(cr2f & 0x10) && (cr1a & 0x04)); // pin 65(66) 559 fan5pin = (cr2b & 0x80) || // pin 126(127) 560 (!(cr1b & 0x03) && (cr2a & 0x02)); // pin 94(96) 561 562 pwm3pin = fan3pin && (cr24 & 0x08); 563 pwm4pin = fan4pin; 564 pwm5pin = fan5pin; 565 } else { 566 /* 567 * NCT6779D, NCT6791D, NCT6792D, NCT6793D, NCT6795D, NCT6796D, 568 * NCT6797D, NCT6798D 569 */ 570 int cr1a = sio_data->sio_inb(sio_data, 0x1a); 571 int cr1b = sio_data->sio_inb(sio_data, 0x1b); 572 int cr1c = sio_data->sio_inb(sio_data, 0x1c); 573 int cr1d = sio_data->sio_inb(sio_data, 0x1d); 574 int cr2a = sio_data->sio_inb(sio_data, 0x2a); 575 int cr2b = sio_data->sio_inb(sio_data, 0x2b); 576 int cr2d = sio_data->sio_inb(sio_data, 0x2d); 577 int cr2f = sio_data->sio_inb(sio_data, 0x2f); 578 bool dsw_en = cr2f & BIT(3); 579 bool ddr4_en = cr2f & BIT(4); 580 int cre0; 581 int creb; 582 int cred; 583 584 sio_data->sio_select(sio_data, NCT6775_LD_12); 585 cre0 = sio_data->sio_inb(sio_data, 0xe0); 586 creb = sio_data->sio_inb(sio_data, 0xeb); 587 cred = sio_data->sio_inb(sio_data, 0xed); 588 589 fan3pin = !(cr1c & BIT(5)); 590 fan4pin = !(cr1c & BIT(6)); 591 fan5pin = !(cr1c & BIT(7)); 592 593 pwm3pin = !(cr1c & BIT(0)); 594 pwm4pin = !(cr1c & BIT(1)); 595 pwm5pin = !(cr1c & BIT(2)); 596 597 switch (data->kind) { 598 case nct6791: 599 fan6pin = cr2d & BIT(1); 600 pwm6pin = cr2d & BIT(0); 601 break; 602 case nct6792: 603 fan6pin = !dsw_en && (cr2d & BIT(1)); 604 pwm6pin = !dsw_en && (cr2d & BIT(0)); 605 break; 606 case nct6793: 607 fan5pin |= cr1b & BIT(5); 608 fan5pin |= creb & BIT(5); 609 610 fan6pin = !dsw_en && (cr2d & BIT(1)); 611 fan6pin |= creb & BIT(3); 612 613 pwm5pin |= cr2d & BIT(7); 614 pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0)); 615 616 pwm6pin = !dsw_en && (cr2d & BIT(0)); 617 pwm6pin |= creb & BIT(2); 618 break; 619 case nct6795: 620 fan5pin |= cr1b & BIT(5); 621 fan5pin |= creb & BIT(5); 622 623 fan6pin = (cr2a & BIT(4)) && 624 (!dsw_en || (cred & BIT(4))); 625 fan6pin |= creb & BIT(3); 626 627 pwm5pin |= cr2d & BIT(7); 628 pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0)); 629 630 pwm6pin = (cr2a & BIT(3)) && (cred & BIT(2)); 631 pwm6pin |= creb & BIT(2); 632 break; 633 case nct6796: 634 fan5pin |= cr1b & BIT(5); 635 fan5pin |= (cre0 & BIT(3)) && !(cr1b & BIT(0)); 636 fan5pin |= creb & BIT(5); 637 638 fan6pin = (cr2a & BIT(4)) && 639 (!dsw_en || (cred & BIT(4))); 640 fan6pin |= creb & BIT(3); 641 642 fan7pin = !(cr2b & BIT(2)); 643 644 pwm5pin |= cr2d & BIT(7); 645 pwm5pin |= (cre0 & BIT(4)) && !(cr1b & BIT(0)); 646 pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0)); 647 648 pwm6pin = (cr2a & BIT(3)) && (cred & BIT(2)); 649 pwm6pin |= creb & BIT(2); 650 651 pwm7pin = !(cr1d & (BIT(2) | BIT(3))); 652 break; 653 case nct6797: 654 fan5pin |= !ddr4_en && (cr1b & BIT(5)); 655 fan5pin |= creb & BIT(5); 656 657 fan6pin = cr2a & BIT(4); 658 fan6pin |= creb & BIT(3); 659 660 fan7pin = cr1a & BIT(1); 661 662 pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0)); 663 pwm5pin |= !ddr4_en && (cr2d & BIT(7)); 664 665 pwm6pin = creb & BIT(2); 666 pwm6pin |= cred & BIT(2); 667 668 pwm7pin = cr1d & BIT(4); 669 break; 670 case nct6798: 671 fan6pin = !(cr1b & BIT(0)) && (cre0 & BIT(3)); 672 fan6pin |= cr2a & BIT(4); 673 fan6pin |= creb & BIT(5); 674 675 fan7pin = cr1b & BIT(5); 676 fan7pin |= !(cr2b & BIT(2)); 677 fan7pin |= creb & BIT(3); 678 679 pwm6pin = !(cr1b & BIT(0)) && (cre0 & BIT(4)); 680 pwm6pin |= !(cred & BIT(2)) && (cr2a & BIT(3)); 681 pwm6pin |= (creb & BIT(4)) && !(cr2a & BIT(0)); 682 683 pwm7pin = !(cr1d & (BIT(2) | BIT(3))); 684 pwm7pin |= cr2d & BIT(7); 685 pwm7pin |= creb & BIT(2); 686 break; 687 default: /* NCT6779D */ 688 break; 689 } 690 691 fan4min = fan4pin; 692 } 693 694 /* fan 1 and 2 (0x03) are always present */ 695 data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) | 696 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6); 697 data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) | 698 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6); 699 data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) | 700 (pwm5pin << 4) | (pwm6pin << 5) | (pwm7pin << 6); 701 } 702 703 static ssize_t 704 cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf) 705 { 706 struct nct6775_data *data = dev_get_drvdata(dev); 707 708 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm)); 709 } 710 711 static DEVICE_ATTR_RO(cpu0_vid); 712 713 /* Case open detection */ 714 715 static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee }; 716 static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 }; 717 718 static ssize_t 719 clear_caseopen(struct device *dev, struct device_attribute *attr, 720 const char *buf, size_t count) 721 { 722 struct nct6775_data *data = dev_get_drvdata(dev); 723 struct nct6775_sio_data *sio_data = data->driver_data; 724 int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE; 725 unsigned long val; 726 u8 reg; 727 int ret; 728 729 if (kstrtoul(buf, 10, &val) || val != 0) 730 return -EINVAL; 731 732 mutex_lock(&data->update_lock); 733 734 /* 735 * Use CR registers to clear caseopen status. 736 * The CR registers are the same for all chips, and not all chips 737 * support clearing the caseopen status through "regular" registers. 738 */ 739 ret = sio_data->sio_enter(sio_data); 740 if (ret) { 741 count = ret; 742 goto error; 743 } 744 745 sio_data->sio_select(sio_data, NCT6775_LD_ACPI); 746 reg = sio_data->sio_inb(sio_data, NCT6775_REG_CR_CASEOPEN_CLR[nr]); 747 reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr]; 748 sio_data->sio_outb(sio_data, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg); 749 reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr]; 750 sio_data->sio_outb(sio_data, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg); 751 sio_data->sio_exit(sio_data); 752 753 data->valid = false; /* Force cache refresh */ 754 error: 755 mutex_unlock(&data->update_lock); 756 return count; 757 } 758 759 static SENSOR_DEVICE_ATTR(intrusion0_alarm, 0644, nct6775_show_alarm, 760 clear_caseopen, INTRUSION_ALARM_BASE); 761 static SENSOR_DEVICE_ATTR(intrusion1_alarm, 0644, nct6775_show_alarm, 762 clear_caseopen, INTRUSION_ALARM_BASE + 1); 763 static SENSOR_DEVICE_ATTR(intrusion0_beep, 0644, nct6775_show_beep, 764 nct6775_store_beep, INTRUSION_ALARM_BASE); 765 static SENSOR_DEVICE_ATTR(intrusion1_beep, 0644, nct6775_show_beep, 766 nct6775_store_beep, INTRUSION_ALARM_BASE + 1); 767 static SENSOR_DEVICE_ATTR(beep_enable, 0644, nct6775_show_beep, 768 nct6775_store_beep, BEEP_ENABLE_BASE); 769 770 static umode_t nct6775_other_is_visible(struct kobject *kobj, 771 struct attribute *attr, int index) 772 { 773 struct device *dev = kobj_to_dev(kobj); 774 struct nct6775_data *data = dev_get_drvdata(dev); 775 776 if (index == 0 && !data->have_vid) 777 return 0; 778 779 if (index == 1 || index == 2) { 780 if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0) 781 return 0; 782 } 783 784 if (index == 3 || index == 4) { 785 if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0) 786 return 0; 787 } 788 789 return nct6775_attr_mode(data, attr); 790 } 791 792 /* 793 * nct6775_other_is_visible uses the index into the following array 794 * to determine if attributes should be created or not. 795 * Any change in order or content must be matched. 796 */ 797 static struct attribute *nct6775_attributes_other[] = { 798 &dev_attr_cpu0_vid.attr, /* 0 */ 799 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, /* 1 */ 800 &sensor_dev_attr_intrusion1_alarm.dev_attr.attr, /* 2 */ 801 &sensor_dev_attr_intrusion0_beep.dev_attr.attr, /* 3 */ 802 &sensor_dev_attr_intrusion1_beep.dev_attr.attr, /* 4 */ 803 &sensor_dev_attr_beep_enable.dev_attr.attr, /* 5 */ 804 805 NULL 806 }; 807 808 static const struct attribute_group nct6775_group_other = { 809 .attrs = nct6775_attributes_other, 810 .is_visible = nct6775_other_is_visible, 811 }; 812 813 static int nct6775_platform_probe_init(struct nct6775_data *data) 814 { 815 int err; 816 u8 cr2a; 817 struct nct6775_sio_data *sio_data = data->driver_data; 818 819 err = sio_data->sio_enter(sio_data); 820 if (err) 821 return err; 822 823 cr2a = sio_data->sio_inb(sio_data, 0x2a); 824 switch (data->kind) { 825 case nct6775: 826 data->have_vid = (cr2a & 0x40); 827 break; 828 case nct6776: 829 data->have_vid = (cr2a & 0x60) == 0x40; 830 break; 831 case nct6106: 832 case nct6116: 833 case nct6779: 834 case nct6791: 835 case nct6792: 836 case nct6793: 837 case nct6795: 838 case nct6796: 839 case nct6797: 840 case nct6798: 841 break; 842 } 843 844 /* 845 * Read VID value 846 * We can get the VID input values directly at logical device D 0xe3. 847 */ 848 if (data->have_vid) { 849 sio_data->sio_select(sio_data, NCT6775_LD_VID); 850 data->vid = sio_data->sio_inb(sio_data, 0xe3); 851 data->vrm = vid_which_vrm(); 852 } 853 854 if (fan_debounce) { 855 u8 tmp; 856 857 sio_data->sio_select(sio_data, NCT6775_LD_HWM); 858 tmp = sio_data->sio_inb(sio_data, 859 NCT6775_REG_CR_FAN_DEBOUNCE); 860 switch (data->kind) { 861 case nct6106: 862 case nct6116: 863 tmp |= 0xe0; 864 break; 865 case nct6775: 866 tmp |= 0x1e; 867 break; 868 case nct6776: 869 case nct6779: 870 tmp |= 0x3e; 871 break; 872 case nct6791: 873 case nct6792: 874 case nct6793: 875 case nct6795: 876 case nct6796: 877 case nct6797: 878 case nct6798: 879 tmp |= 0x7e; 880 break; 881 } 882 sio_data->sio_outb(sio_data, NCT6775_REG_CR_FAN_DEBOUNCE, 883 tmp); 884 pr_info("Enabled fan debounce for chip %s\n", data->name); 885 } 886 887 nct6775_check_fan_inputs(data, sio_data); 888 889 sio_data->sio_exit(sio_data); 890 891 return nct6775_add_attr_group(data, &nct6775_group_other); 892 } 893 894 static const struct regmap_config nct6775_regmap_config = { 895 .reg_bits = 16, 896 .val_bits = 16, 897 .reg_read = nct6775_reg_read, 898 .reg_write = nct6775_reg_write, 899 }; 900 901 static const struct regmap_config nct6775_wmi_regmap_config = { 902 .reg_bits = 16, 903 .val_bits = 16, 904 .reg_read = nct6775_wmi_reg_read, 905 .reg_write = nct6775_wmi_reg_write, 906 }; 907 908 static int nct6775_platform_probe(struct platform_device *pdev) 909 { 910 struct device *dev = &pdev->dev; 911 struct nct6775_sio_data *sio_data = dev_get_platdata(dev); 912 struct nct6775_data *data; 913 struct resource *res; 914 const struct regmap_config *regmapcfg; 915 916 if (sio_data->access == access_direct) { 917 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 918 if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH, DRVNAME)) 919 return -EBUSY; 920 } 921 922 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 923 if (!data) 924 return -ENOMEM; 925 926 data->kind = sio_data->kind; 927 data->sioreg = sio_data->sioreg; 928 929 if (sio_data->access == access_direct) { 930 data->addr = res->start; 931 regmapcfg = &nct6775_regmap_config; 932 } else { 933 regmapcfg = &nct6775_wmi_regmap_config; 934 } 935 936 platform_set_drvdata(pdev, data); 937 938 data->driver_data = sio_data; 939 data->driver_init = nct6775_platform_probe_init; 940 941 return nct6775_probe(&pdev->dev, data, regmapcfg); 942 } 943 944 static struct platform_driver nct6775_driver = { 945 .driver = { 946 .name = DRVNAME, 947 .pm = pm_sleep_ptr(&nct6775_dev_pm_ops), 948 }, 949 .probe = nct6775_platform_probe, 950 }; 951 952 /* nct6775_find() looks for a '627 in the Super-I/O config space */ 953 static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data) 954 { 955 u16 val; 956 int err; 957 int addr; 958 959 sio_data->access = access_direct; 960 sio_data->sioreg = sioaddr; 961 962 err = sio_data->sio_enter(sio_data); 963 if (err) 964 return err; 965 966 val = (sio_data->sio_inb(sio_data, SIO_REG_DEVID) << 8) | 967 sio_data->sio_inb(sio_data, SIO_REG_DEVID + 1); 968 if (force_id && val != 0xffff) 969 val = force_id; 970 971 switch (val & SIO_ID_MASK) { 972 case SIO_NCT6106_ID: 973 sio_data->kind = nct6106; 974 break; 975 case SIO_NCT6116_ID: 976 sio_data->kind = nct6116; 977 break; 978 case SIO_NCT6775_ID: 979 sio_data->kind = nct6775; 980 break; 981 case SIO_NCT6776_ID: 982 sio_data->kind = nct6776; 983 break; 984 case SIO_NCT6779_ID: 985 sio_data->kind = nct6779; 986 break; 987 case SIO_NCT6791_ID: 988 sio_data->kind = nct6791; 989 break; 990 case SIO_NCT6792_ID: 991 sio_data->kind = nct6792; 992 break; 993 case SIO_NCT6793_ID: 994 sio_data->kind = nct6793; 995 break; 996 case SIO_NCT6795_ID: 997 sio_data->kind = nct6795; 998 break; 999 case SIO_NCT6796_ID: 1000 sio_data->kind = nct6796; 1001 break; 1002 case SIO_NCT6797_ID: 1003 sio_data->kind = nct6797; 1004 break; 1005 case SIO_NCT6798_ID: 1006 sio_data->kind = nct6798; 1007 break; 1008 default: 1009 if (val != 0xffff) 1010 pr_debug("unsupported chip ID: 0x%04x\n", val); 1011 sio_data->sio_exit(sio_data); 1012 return -ENODEV; 1013 } 1014 1015 /* We have a known chip, find the HWM I/O address */ 1016 sio_data->sio_select(sio_data, NCT6775_LD_HWM); 1017 val = (sio_data->sio_inb(sio_data, SIO_REG_ADDR) << 8) 1018 | sio_data->sio_inb(sio_data, SIO_REG_ADDR + 1); 1019 addr = val & IOREGION_ALIGNMENT; 1020 if (addr == 0) { 1021 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n"); 1022 sio_data->sio_exit(sio_data); 1023 return -ENODEV; 1024 } 1025 1026 /* Activate logical device if needed */ 1027 val = sio_data->sio_inb(sio_data, SIO_REG_ENABLE); 1028 if (!(val & 0x01)) { 1029 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n"); 1030 sio_data->sio_outb(sio_data, SIO_REG_ENABLE, val | 0x01); 1031 } 1032 1033 if (sio_data->kind == nct6791 || sio_data->kind == nct6792 || 1034 sio_data->kind == nct6793 || sio_data->kind == nct6795 || 1035 sio_data->kind == nct6796 || sio_data->kind == nct6797 || 1036 sio_data->kind == nct6798) 1037 nct6791_enable_io_mapping(sio_data); 1038 1039 sio_data->sio_exit(sio_data); 1040 pr_info("Found %s or compatible chip at %#x:%#x\n", 1041 nct6775_sio_names[sio_data->kind], sioaddr, addr); 1042 1043 return addr; 1044 } 1045 1046 /* 1047 * when Super-I/O functions move to a separate file, the Super-I/O 1048 * bus will manage the lifetime of the device and this module will only keep 1049 * track of the nct6775 driver. But since we use platform_device_alloc(), we 1050 * must keep track of the device 1051 */ 1052 static struct platform_device *pdev[2]; 1053 1054 static const char * const asus_wmi_boards[] = { 1055 "PRO H410T", 1056 "ProArt B550-CREATOR", 1057 "ProArt X570-CREATOR WIFI", 1058 "ProArt Z490-CREATOR 10G", 1059 "Pro B550M-C", 1060 "Pro WS X570-ACE", 1061 "PRIME B360-PLUS", 1062 "PRIME B460-PLUS", 1063 "PRIME B550-PLUS", 1064 "PRIME B550M-A", 1065 "PRIME B550M-A (WI-FI)", 1066 "PRIME H410M-R", 1067 "PRIME X570-P", 1068 "PRIME X570-PRO", 1069 "ROG CROSSHAIR VIII DARK HERO", 1070 "ROG CROSSHAIR VIII EXTREME", 1071 "ROG CROSSHAIR VIII FORMULA", 1072 "ROG CROSSHAIR VIII HERO", 1073 "ROG CROSSHAIR VIII HERO (WI-FI)", 1074 "ROG CROSSHAIR VIII IMPACT", 1075 "ROG STRIX B550-A GAMING", 1076 "ROG STRIX B550-E GAMING", 1077 "ROG STRIX B550-F GAMING", 1078 "ROG STRIX B550-F GAMING (WI-FI)", 1079 "ROG STRIX B550-F GAMING WIFI II", 1080 "ROG STRIX B550-I GAMING", 1081 "ROG STRIX B550-XE GAMING (WI-FI)", 1082 "ROG STRIX X570-E GAMING", 1083 "ROG STRIX X570-E GAMING WIFI II", 1084 "ROG STRIX X570-F GAMING", 1085 "ROG STRIX X570-I GAMING", 1086 "ROG STRIX Z390-E GAMING", 1087 "ROG STRIX Z390-F GAMING", 1088 "ROG STRIX Z390-H GAMING", 1089 "ROG STRIX Z390-I GAMING", 1090 "ROG STRIX Z490-A GAMING", 1091 "ROG STRIX Z490-E GAMING", 1092 "ROG STRIX Z490-F GAMING", 1093 "ROG STRIX Z490-G GAMING", 1094 "ROG STRIX Z490-G GAMING (WI-FI)", 1095 "ROG STRIX Z490-H GAMING", 1096 "ROG STRIX Z490-I GAMING", 1097 "TUF GAMING B550M-E", 1098 "TUF GAMING B550M-E (WI-FI)", 1099 "TUF GAMING B550M-PLUS", 1100 "TUF GAMING B550M-PLUS (WI-FI)", 1101 "TUF GAMING B550M-PLUS WIFI II", 1102 "TUF GAMING B550-PLUS", 1103 "TUF GAMING B550-PLUS WIFI II", 1104 "TUF GAMING B550-PRO", 1105 "TUF GAMING X570-PLUS", 1106 "TUF GAMING X570-PLUS (WI-FI)", 1107 "TUF GAMING X570-PRO (WI-FI)", 1108 "TUF GAMING Z490-PLUS", 1109 "TUF GAMING Z490-PLUS (WI-FI)", 1110 }; 1111 1112 static const char * const asus_msi_boards[] = { 1113 "EX-B660M-V5 PRO D4", 1114 "PRIME B650-PLUS", 1115 "PRIME B650M-A", 1116 "PRIME B650M-A AX", 1117 "PRIME B650M-A II", 1118 "PRIME B650M-A WIFI", 1119 "PRIME B650M-A WIFI II", 1120 "PRIME B660M-A D4", 1121 "PRIME B660M-A WIFI D4", 1122 "PRIME X670-P", 1123 "PRIME X670-P WIFI", 1124 "PRIME X670E-PRO WIFI", 1125 "Pro B660M-C-D4", 1126 "ProArt B660-CREATOR D4", 1127 "ProArt X670E-CREATOR WIFI", 1128 "ROG CROSSHAIR X670E EXTREME", 1129 "ROG CROSSHAIR X670E GENE", 1130 "ROG CROSSHAIR X670E HERO", 1131 "ROG MAXIMUS XIII EXTREME GLACIAL", 1132 "ROG MAXIMUS Z690 EXTREME", 1133 "ROG MAXIMUS Z690 EXTREME GLACIAL", 1134 "ROG STRIX B650-A GAMING WIFI", 1135 "ROG STRIX B650E-E GAMING WIFI", 1136 "ROG STRIX B650E-F GAMING WIFI", 1137 "ROG STRIX B650E-I GAMING WIFI", 1138 "ROG STRIX B660-A GAMING WIFI D4", 1139 "ROG STRIX B660-F GAMING WIFI", 1140 "ROG STRIX B660-G GAMING WIFI", 1141 "ROG STRIX B660-I GAMING WIFI", 1142 "ROG STRIX X670E-A GAMING WIFI", 1143 "ROG STRIX X670E-E GAMING WIFI", 1144 "ROG STRIX X670E-F GAMING WIFI", 1145 "ROG STRIX X670E-I GAMING WIFI", 1146 "ROG STRIX Z590-A GAMING WIFI II", 1147 "ROG STRIX Z690-A GAMING WIFI D4", 1148 "TUF GAMING B650-PLUS", 1149 "TUF GAMING B650-PLUS WIFI", 1150 "TUF GAMING B650M-PLUS", 1151 "TUF GAMING B650M-PLUS WIFI", 1152 "TUF GAMING B660M-PLUS WIFI", 1153 "TUF GAMING X670E-PLUS", 1154 "TUF GAMING X670E-PLUS WIFI", 1155 "TUF GAMING Z590-PLUS WIFI", 1156 }; 1157 1158 #if IS_ENABLED(CONFIG_ACPI) 1159 /* 1160 * Callback for acpi_bus_for_each_dev() to find the right device 1161 * by _UID and _HID and return 1 to stop iteration. 1162 */ 1163 static int nct6775_asuswmi_device_match(struct device *dev, void *data) 1164 { 1165 struct acpi_device *adev = to_acpi_device(dev); 1166 const char *uid = acpi_device_uid(adev); 1167 const char *hid = acpi_device_hid(adev); 1168 1169 if (hid && !strcmp(hid, ASUSWMI_DEVICE_HID) && uid && !strcmp(uid, data)) { 1170 asus_acpi_dev = adev; 1171 return 1; 1172 } 1173 1174 return 0; 1175 } 1176 #endif 1177 1178 static enum sensor_access nct6775_determine_access(const char *device_uid) 1179 { 1180 #if IS_ENABLED(CONFIG_ACPI) 1181 u8 tmp; 1182 1183 acpi_bus_for_each_dev(nct6775_asuswmi_device_match, (void *)device_uid); 1184 if (!asus_acpi_dev) 1185 return access_direct; 1186 1187 /* if reading chip id via ACPI succeeds, use WMI "WMBD" method for access */ 1188 if (!nct6775_asuswmi_read(0, NCT6775_PORT_CHIPID, &tmp) && tmp) { 1189 pr_debug("Using Asus WMBD method of %s to access %#x chip.\n", device_uid, tmp); 1190 return access_asuswmi; 1191 } 1192 #endif 1193 1194 return access_direct; 1195 } 1196 1197 static int __init sensors_nct6775_platform_init(void) 1198 { 1199 int i, err; 1200 bool found = false; 1201 int address; 1202 struct resource res; 1203 struct nct6775_sio_data sio_data; 1204 int sioaddr[2] = { 0x2e, 0x4e }; 1205 enum sensor_access access = access_direct; 1206 const char *board_vendor, *board_name; 1207 1208 err = platform_driver_register(&nct6775_driver); 1209 if (err) 1210 return err; 1211 1212 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR); 1213 board_name = dmi_get_system_info(DMI_BOARD_NAME); 1214 1215 if (board_name && board_vendor && 1216 !strcmp(board_vendor, "ASUSTeK COMPUTER INC.")) { 1217 err = match_string(asus_wmi_boards, ARRAY_SIZE(asus_wmi_boards), 1218 board_name); 1219 if (err >= 0) 1220 access = nct6775_determine_access(ASUSWMI_DEVICE_UID); 1221 1222 err = match_string(asus_msi_boards, ARRAY_SIZE(asus_msi_boards), 1223 board_name); 1224 if (err >= 0) 1225 access = nct6775_determine_access(ASUSMSI_DEVICE_UID); 1226 } 1227 1228 /* 1229 * initialize sio_data->kind and sio_data->sioreg. 1230 * 1231 * when Super-I/O functions move to a separate file, the Super-I/O 1232 * driver will probe 0x2e and 0x4e and auto-detect the presence of a 1233 * nct6775 hardware monitor, and call probe() 1234 */ 1235 for (i = 0; i < ARRAY_SIZE(pdev); i++) { 1236 sio_data.sio_outb = superio_outb; 1237 sio_data.sio_inb = superio_inb; 1238 sio_data.sio_select = superio_select; 1239 sio_data.sio_enter = superio_enter; 1240 sio_data.sio_exit = superio_exit; 1241 1242 address = nct6775_find(sioaddr[i], &sio_data); 1243 if (address <= 0) 1244 continue; 1245 1246 found = true; 1247 1248 sio_data.access = access; 1249 1250 if (access == access_asuswmi) { 1251 sio_data.sio_outb = superio_wmi_outb; 1252 sio_data.sio_inb = superio_wmi_inb; 1253 sio_data.sio_select = superio_wmi_select; 1254 sio_data.sio_enter = superio_wmi_enter; 1255 sio_data.sio_exit = superio_wmi_exit; 1256 } 1257 1258 pdev[i] = platform_device_alloc(DRVNAME, address); 1259 if (!pdev[i]) { 1260 err = -ENOMEM; 1261 goto exit_device_unregister; 1262 } 1263 1264 err = platform_device_add_data(pdev[i], &sio_data, 1265 sizeof(struct nct6775_sio_data)); 1266 if (err) 1267 goto exit_device_put; 1268 1269 if (sio_data.access == access_direct) { 1270 memset(&res, 0, sizeof(res)); 1271 res.name = DRVNAME; 1272 res.start = address + IOREGION_OFFSET; 1273 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1; 1274 res.flags = IORESOURCE_IO; 1275 1276 err = acpi_check_resource_conflict(&res); 1277 if (err) { 1278 platform_device_put(pdev[i]); 1279 pdev[i] = NULL; 1280 continue; 1281 } 1282 1283 err = platform_device_add_resources(pdev[i], &res, 1); 1284 if (err) 1285 goto exit_device_put; 1286 } 1287 1288 /* platform_device_add calls probe() */ 1289 err = platform_device_add(pdev[i]); 1290 if (err) 1291 goto exit_device_put; 1292 } 1293 if (!found) { 1294 err = -ENODEV; 1295 goto exit_unregister; 1296 } 1297 1298 return 0; 1299 1300 exit_device_put: 1301 platform_device_put(pdev[i]); 1302 exit_device_unregister: 1303 while (i--) 1304 platform_device_unregister(pdev[i]); 1305 exit_unregister: 1306 platform_driver_unregister(&nct6775_driver); 1307 return err; 1308 } 1309 1310 static void __exit sensors_nct6775_platform_exit(void) 1311 { 1312 int i; 1313 1314 for (i = 0; i < ARRAY_SIZE(pdev); i++) 1315 platform_device_unregister(pdev[i]); 1316 platform_driver_unregister(&nct6775_driver); 1317 } 1318 1319 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>"); 1320 MODULE_DESCRIPTION("Platform driver for NCT6775F and compatible chips"); 1321 MODULE_LICENSE("GPL"); 1322 MODULE_IMPORT_NS(HWMON_NCT6775); 1323 1324 module_init(sensors_nct6775_platform_init); 1325 module_exit(sensors_nct6775_platform_exit); 1326