1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 MaxLinear, Inc. 4 * 5 * This driver is a hardware monitoring driver for PVT controller 6 * (MR75203) which is used to configure & control Moortec embedded 7 * analog IP to enable multiple embedded temperature sensor(TS), 8 * voltage monitor(VM) & process detector(PD) modules. 9 */ 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/hwmon.h> 13 #include <linux/module.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/mutex.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 #include <linux/units.h> 21 22 /* PVT Common register */ 23 #define PVT_IP_CONFIG 0x04 24 #define TS_NUM_MSK GENMASK(4, 0) 25 #define TS_NUM_SFT 0 26 #define PD_NUM_MSK GENMASK(12, 8) 27 #define PD_NUM_SFT 8 28 #define VM_NUM_MSK GENMASK(20, 16) 29 #define VM_NUM_SFT 16 30 #define CH_NUM_MSK GENMASK(31, 24) 31 #define CH_NUM_SFT 24 32 33 /* Macro Common Register */ 34 #define CLK_SYNTH 0x00 35 #define CLK_SYNTH_LO_SFT 0 36 #define CLK_SYNTH_HI_SFT 8 37 #define CLK_SYNTH_HOLD_SFT 16 38 #define CLK_SYNTH_EN BIT(24) 39 #define CLK_SYS_CYCLES_MAX 514 40 #define CLK_SYS_CYCLES_MIN 2 41 42 #define SDIF_DISABLE 0x04 43 44 #define SDIF_STAT 0x08 45 #define SDIF_BUSY BIT(0) 46 #define SDIF_LOCK BIT(1) 47 48 #define SDIF_W 0x0c 49 #define SDIF_PROG BIT(31) 50 #define SDIF_WRN_W BIT(27) 51 #define SDIF_WRN_R 0x00 52 #define SDIF_ADDR_SFT 24 53 54 #define SDIF_HALT 0x10 55 #define SDIF_CTRL 0x14 56 #define SDIF_SMPL_CTRL 0x20 57 58 /* TS & PD Individual Macro Register */ 59 #define COM_REG_SIZE 0x40 60 61 #define SDIF_DONE(n) (COM_REG_SIZE + 0x14 + 0x40 * (n)) 62 #define SDIF_SMPL_DONE BIT(0) 63 64 #define SDIF_DATA(n) (COM_REG_SIZE + 0x18 + 0x40 * (n)) 65 #define SAMPLE_DATA_MSK GENMASK(15, 0) 66 67 #define HILO_RESET(n) (COM_REG_SIZE + 0x2c + 0x40 * (n)) 68 69 /* VM Individual Macro Register */ 70 #define VM_COM_REG_SIZE 0x200 71 #define VM_SDIF_DONE(vm) (VM_COM_REG_SIZE + 0x34 + 0x200 * (vm)) 72 #define VM_SDIF_DATA(vm, ch) \ 73 (VM_COM_REG_SIZE + 0x40 + 0x200 * (vm) + 0x4 * (ch)) 74 75 /* SDA Slave Register */ 76 #define IP_CTRL 0x00 77 #define IP_RST_REL BIT(1) 78 #define IP_RUN_CONT BIT(3) 79 #define IP_AUTO BIT(8) 80 #define IP_VM_MODE BIT(10) 81 82 #define IP_CFG 0x01 83 #define CFG0_MODE_2 BIT(0) 84 #define CFG0_PARALLEL_OUT 0 85 #define CFG0_12_BIT 0 86 #define CFG1_VOL_MEAS_MODE 0 87 #define CFG1_PARALLEL_OUT 0 88 #define CFG1_14_BIT 0 89 90 #define IP_DATA 0x03 91 92 #define IP_POLL 0x04 93 #define VM_CH_INIT BIT(20) 94 #define VM_CH_REQ BIT(21) 95 96 #define IP_TMR 0x05 97 #define POWER_DELAY_CYCLE_256 0x100 98 #define POWER_DELAY_CYCLE_64 0x40 99 100 #define PVT_POLL_DELAY_US 20 101 #define PVT_POLL_TIMEOUT_US 20000 102 #define PVT_H_CONST 100000 103 #define PVT_CAL5_CONST 2047 104 #define PVT_G_CONST 40000 105 #define PVT_CONV_BITS 10 106 #define PVT_N_CONST 90 107 #define PVT_R_CONST 245805 108 109 struct pvt_device { 110 struct regmap *c_map; 111 struct regmap *t_map; 112 struct regmap *p_map; 113 struct regmap *v_map; 114 struct clk *clk; 115 struct reset_control *rst; 116 u32 t_num; 117 u32 p_num; 118 u32 v_num; 119 u32 c_num; 120 u32 ip_freq; 121 u8 *vm_idx; 122 }; 123 124 static umode_t pvt_is_visible(const void *data, enum hwmon_sensor_types type, 125 u32 attr, int channel) 126 { 127 switch (type) { 128 case hwmon_temp: 129 if (attr == hwmon_temp_input) 130 return 0444; 131 break; 132 case hwmon_in: 133 if (attr == hwmon_in_input) 134 return 0444; 135 break; 136 default: 137 break; 138 } 139 return 0; 140 } 141 142 static int pvt_read_temp(struct device *dev, u32 attr, int channel, long *val) 143 { 144 struct pvt_device *pvt = dev_get_drvdata(dev); 145 struct regmap *t_map = pvt->t_map; 146 u32 stat, nbs; 147 int ret; 148 u64 tmp; 149 150 switch (attr) { 151 case hwmon_temp_input: 152 ret = regmap_read_poll_timeout(t_map, SDIF_DONE(channel), 153 stat, stat & SDIF_SMPL_DONE, 154 PVT_POLL_DELAY_US, 155 PVT_POLL_TIMEOUT_US); 156 if (ret) 157 return ret; 158 159 ret = regmap_read(t_map, SDIF_DATA(channel), &nbs); 160 if(ret < 0) 161 return ret; 162 163 nbs &= SAMPLE_DATA_MSK; 164 165 /* 166 * Convert the register value to 167 * degrees centigrade temperature 168 */ 169 tmp = nbs * PVT_H_CONST; 170 do_div(tmp, PVT_CAL5_CONST); 171 *val = tmp - PVT_G_CONST - pvt->ip_freq; 172 173 return 0; 174 default: 175 return -EOPNOTSUPP; 176 } 177 } 178 179 static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val) 180 { 181 struct pvt_device *pvt = dev_get_drvdata(dev); 182 struct regmap *v_map = pvt->v_map; 183 u8 vm_idx, ch_idx; 184 u32 n, stat; 185 int ret; 186 187 if (channel >= pvt->v_num * pvt->c_num) 188 return -EINVAL; 189 190 vm_idx = pvt->vm_idx[channel / pvt->c_num]; 191 ch_idx = channel % pvt->c_num; 192 193 switch (attr) { 194 case hwmon_in_input: 195 ret = regmap_read_poll_timeout(v_map, VM_SDIF_DONE(vm_idx), 196 stat, stat & SDIF_SMPL_DONE, 197 PVT_POLL_DELAY_US, 198 PVT_POLL_TIMEOUT_US); 199 if (ret) 200 return ret; 201 202 ret = regmap_read(v_map, VM_SDIF_DATA(vm_idx, ch_idx), &n); 203 if(ret < 0) 204 return ret; 205 206 n &= SAMPLE_DATA_MSK; 207 /* 208 * Convert the N bitstream count into voltage. 209 * To support negative voltage calculation for 64bit machines 210 * n must be cast to long, since n and *val differ both in 211 * signedness and in size. 212 * Division is used instead of right shift, because for signed 213 * numbers, the sign bit is used to fill the vacated bit 214 * positions, and if the number is negative, 1 is used. 215 * BIT(x) may not be used instead of (1 << x) because it's 216 * unsigned. 217 */ 218 *val = (PVT_N_CONST * (long)n - PVT_R_CONST) / (1 << PVT_CONV_BITS); 219 220 return 0; 221 default: 222 return -EOPNOTSUPP; 223 } 224 } 225 226 static int pvt_read(struct device *dev, enum hwmon_sensor_types type, 227 u32 attr, int channel, long *val) 228 { 229 switch (type) { 230 case hwmon_temp: 231 return pvt_read_temp(dev, attr, channel, val); 232 case hwmon_in: 233 return pvt_read_in(dev, attr, channel, val); 234 default: 235 return -EOPNOTSUPP; 236 } 237 } 238 239 static struct hwmon_channel_info pvt_temp = { 240 .type = hwmon_temp, 241 }; 242 243 static struct hwmon_channel_info pvt_in = { 244 .type = hwmon_in, 245 }; 246 247 static const struct hwmon_ops pvt_hwmon_ops = { 248 .is_visible = pvt_is_visible, 249 .read = pvt_read, 250 }; 251 252 static struct hwmon_chip_info pvt_chip_info = { 253 .ops = &pvt_hwmon_ops, 254 }; 255 256 static int pvt_init(struct pvt_device *pvt) 257 { 258 u16 sys_freq, key, middle, low = 4, high = 8; 259 struct regmap *t_map = pvt->t_map; 260 struct regmap *p_map = pvt->p_map; 261 struct regmap *v_map = pvt->v_map; 262 u32 t_num = pvt->t_num; 263 u32 p_num = pvt->p_num; 264 u32 v_num = pvt->v_num; 265 u32 clk_synth, val; 266 int ret; 267 268 sys_freq = clk_get_rate(pvt->clk) / HZ_PER_MHZ; 269 while (high >= low) { 270 middle = (low + high + 1) / 2; 271 key = DIV_ROUND_CLOSEST(sys_freq, middle); 272 if (key > CLK_SYS_CYCLES_MAX) { 273 low = middle + 1; 274 continue; 275 } else if (key < CLK_SYS_CYCLES_MIN) { 276 high = middle - 1; 277 continue; 278 } else { 279 break; 280 } 281 } 282 283 /* 284 * The system supports 'clk_sys' to 'clk_ip' frequency ratios 285 * from 2:1 to 512:1 286 */ 287 key = clamp_val(key, CLK_SYS_CYCLES_MIN, CLK_SYS_CYCLES_MAX) - 2; 288 289 clk_synth = ((key + 1) >> 1) << CLK_SYNTH_LO_SFT | 290 (key >> 1) << CLK_SYNTH_HI_SFT | 291 (key >> 1) << CLK_SYNTH_HOLD_SFT | CLK_SYNTH_EN; 292 293 pvt->ip_freq = sys_freq * 100 / (key + 2); 294 295 if (t_num) { 296 ret = regmap_write(t_map, SDIF_SMPL_CTRL, 0x0); 297 if(ret < 0) 298 return ret; 299 300 ret = regmap_write(t_map, SDIF_HALT, 0x0); 301 if(ret < 0) 302 return ret; 303 304 ret = regmap_write(t_map, CLK_SYNTH, clk_synth); 305 if(ret < 0) 306 return ret; 307 308 ret = regmap_write(t_map, SDIF_DISABLE, 0x0); 309 if(ret < 0) 310 return ret; 311 312 ret = regmap_read_poll_timeout(t_map, SDIF_STAT, 313 val, !(val & SDIF_BUSY), 314 PVT_POLL_DELAY_US, 315 PVT_POLL_TIMEOUT_US); 316 if (ret) 317 return ret; 318 319 val = CFG0_MODE_2 | CFG0_PARALLEL_OUT | CFG0_12_BIT | 320 IP_CFG << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG; 321 ret = regmap_write(t_map, SDIF_W, val); 322 if(ret < 0) 323 return ret; 324 325 ret = regmap_read_poll_timeout(t_map, SDIF_STAT, 326 val, !(val & SDIF_BUSY), 327 PVT_POLL_DELAY_US, 328 PVT_POLL_TIMEOUT_US); 329 if (ret) 330 return ret; 331 332 val = POWER_DELAY_CYCLE_256 | IP_TMR << SDIF_ADDR_SFT | 333 SDIF_WRN_W | SDIF_PROG; 334 ret = regmap_write(t_map, SDIF_W, val); 335 if(ret < 0) 336 return ret; 337 338 ret = regmap_read_poll_timeout(t_map, SDIF_STAT, 339 val, !(val & SDIF_BUSY), 340 PVT_POLL_DELAY_US, 341 PVT_POLL_TIMEOUT_US); 342 if (ret) 343 return ret; 344 345 val = IP_RST_REL | IP_RUN_CONT | IP_AUTO | 346 IP_CTRL << SDIF_ADDR_SFT | 347 SDIF_WRN_W | SDIF_PROG; 348 ret = regmap_write(t_map, SDIF_W, val); 349 if(ret < 0) 350 return ret; 351 } 352 353 if (p_num) { 354 ret = regmap_write(p_map, SDIF_HALT, 0x0); 355 if(ret < 0) 356 return ret; 357 358 ret = regmap_write(p_map, SDIF_DISABLE, BIT(p_num) - 1); 359 if(ret < 0) 360 return ret; 361 362 ret = regmap_write(p_map, CLK_SYNTH, clk_synth); 363 if(ret < 0) 364 return ret; 365 } 366 367 if (v_num) { 368 ret = regmap_write(v_map, SDIF_SMPL_CTRL, 0x0); 369 if(ret < 0) 370 return ret; 371 372 ret = regmap_write(v_map, SDIF_HALT, 0x0); 373 if(ret < 0) 374 return ret; 375 376 ret = regmap_write(v_map, CLK_SYNTH, clk_synth); 377 if(ret < 0) 378 return ret; 379 380 ret = regmap_write(v_map, SDIF_DISABLE, 0x0); 381 if(ret < 0) 382 return ret; 383 384 ret = regmap_read_poll_timeout(v_map, SDIF_STAT, 385 val, !(val & SDIF_BUSY), 386 PVT_POLL_DELAY_US, 387 PVT_POLL_TIMEOUT_US); 388 if (ret) 389 return ret; 390 391 val = (BIT(pvt->c_num) - 1) | VM_CH_INIT | 392 IP_POLL << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG; 393 ret = regmap_write(v_map, SDIF_W, val); 394 if (ret < 0) 395 return ret; 396 397 ret = regmap_read_poll_timeout(v_map, SDIF_STAT, 398 val, !(val & SDIF_BUSY), 399 PVT_POLL_DELAY_US, 400 PVT_POLL_TIMEOUT_US); 401 if (ret) 402 return ret; 403 404 val = CFG1_VOL_MEAS_MODE | CFG1_PARALLEL_OUT | 405 CFG1_14_BIT | IP_CFG << SDIF_ADDR_SFT | 406 SDIF_WRN_W | SDIF_PROG; 407 ret = regmap_write(v_map, SDIF_W, val); 408 if(ret < 0) 409 return ret; 410 411 ret = regmap_read_poll_timeout(v_map, SDIF_STAT, 412 val, !(val & SDIF_BUSY), 413 PVT_POLL_DELAY_US, 414 PVT_POLL_TIMEOUT_US); 415 if (ret) 416 return ret; 417 418 val = POWER_DELAY_CYCLE_64 | IP_TMR << SDIF_ADDR_SFT | 419 SDIF_WRN_W | SDIF_PROG; 420 ret = regmap_write(v_map, SDIF_W, val); 421 if(ret < 0) 422 return ret; 423 424 ret = regmap_read_poll_timeout(v_map, SDIF_STAT, 425 val, !(val & SDIF_BUSY), 426 PVT_POLL_DELAY_US, 427 PVT_POLL_TIMEOUT_US); 428 if (ret) 429 return ret; 430 431 val = IP_RST_REL | IP_RUN_CONT | IP_AUTO | IP_VM_MODE | 432 IP_CTRL << SDIF_ADDR_SFT | 433 SDIF_WRN_W | SDIF_PROG; 434 ret = regmap_write(v_map, SDIF_W, val); 435 if(ret < 0) 436 return ret; 437 } 438 439 return 0; 440 } 441 442 static struct regmap_config pvt_regmap_config = { 443 .reg_bits = 32, 444 .reg_stride = 4, 445 .val_bits = 32, 446 }; 447 448 static int pvt_get_regmap(struct platform_device *pdev, char *reg_name, 449 struct pvt_device *pvt) 450 { 451 struct device *dev = &pdev->dev; 452 struct regmap **reg_map; 453 void __iomem *io_base; 454 455 if (!strcmp(reg_name, "common")) 456 reg_map = &pvt->c_map; 457 else if (!strcmp(reg_name, "ts")) 458 reg_map = &pvt->t_map; 459 else if (!strcmp(reg_name, "pd")) 460 reg_map = &pvt->p_map; 461 else if (!strcmp(reg_name, "vm")) 462 reg_map = &pvt->v_map; 463 else 464 return -EINVAL; 465 466 io_base = devm_platform_ioremap_resource_byname(pdev, reg_name); 467 if (IS_ERR(io_base)) 468 return PTR_ERR(io_base); 469 470 pvt_regmap_config.name = reg_name; 471 *reg_map = devm_regmap_init_mmio(dev, io_base, &pvt_regmap_config); 472 if (IS_ERR(*reg_map)) { 473 dev_err(dev, "failed to init register map\n"); 474 return PTR_ERR(*reg_map); 475 } 476 477 return 0; 478 } 479 480 static void pvt_clk_disable(void *data) 481 { 482 struct pvt_device *pvt = data; 483 484 clk_disable_unprepare(pvt->clk); 485 } 486 487 static int pvt_clk_enable(struct device *dev, struct pvt_device *pvt) 488 { 489 int ret; 490 491 ret = clk_prepare_enable(pvt->clk); 492 if (ret) 493 return ret; 494 495 return devm_add_action_or_reset(dev, pvt_clk_disable, pvt); 496 } 497 498 static void pvt_reset_control_assert(void *data) 499 { 500 struct pvt_device *pvt = data; 501 502 reset_control_assert(pvt->rst); 503 } 504 505 static int pvt_reset_control_deassert(struct device *dev, struct pvt_device *pvt) 506 { 507 int ret; 508 509 ret = reset_control_deassert(pvt->rst); 510 if (ret) 511 return ret; 512 513 return devm_add_action_or_reset(dev, pvt_reset_control_assert, pvt); 514 } 515 516 static int mr75203_probe(struct platform_device *pdev) 517 { 518 u32 ts_num, vm_num, pd_num, ch_num, val, index, i; 519 const struct hwmon_channel_info **pvt_info; 520 struct device *dev = &pdev->dev; 521 u32 *temp_config, *in_config; 522 struct device *hwmon_dev; 523 struct pvt_device *pvt; 524 int ret; 525 526 pvt = devm_kzalloc(dev, sizeof(*pvt), GFP_KERNEL); 527 if (!pvt) 528 return -ENOMEM; 529 530 ret = pvt_get_regmap(pdev, "common", pvt); 531 if (ret) 532 return ret; 533 534 pvt->clk = devm_clk_get(dev, NULL); 535 if (IS_ERR(pvt->clk)) 536 return dev_err_probe(dev, PTR_ERR(pvt->clk), "failed to get clock\n"); 537 538 ret = pvt_clk_enable(dev, pvt); 539 if (ret) { 540 dev_err(dev, "failed to enable clock\n"); 541 return ret; 542 } 543 544 pvt->rst = devm_reset_control_get_exclusive(dev, NULL); 545 if (IS_ERR(pvt->rst)) 546 return dev_err_probe(dev, PTR_ERR(pvt->rst), 547 "failed to get reset control\n"); 548 549 ret = pvt_reset_control_deassert(dev, pvt); 550 if (ret) 551 return dev_err_probe(dev, ret, "cannot deassert reset control\n"); 552 553 ret = regmap_read(pvt->c_map, PVT_IP_CONFIG, &val); 554 if(ret < 0) 555 return ret; 556 557 ts_num = (val & TS_NUM_MSK) >> TS_NUM_SFT; 558 pd_num = (val & PD_NUM_MSK) >> PD_NUM_SFT; 559 vm_num = (val & VM_NUM_MSK) >> VM_NUM_SFT; 560 ch_num = (val & CH_NUM_MSK) >> CH_NUM_SFT; 561 pvt->t_num = ts_num; 562 pvt->p_num = pd_num; 563 pvt->v_num = vm_num; 564 pvt->c_num = ch_num; 565 val = 0; 566 if (ts_num) 567 val++; 568 if (vm_num) 569 val++; 570 if (!val) 571 return -ENODEV; 572 573 pvt_info = devm_kcalloc(dev, val + 2, sizeof(*pvt_info), GFP_KERNEL); 574 if (!pvt_info) 575 return -ENOMEM; 576 pvt_info[0] = HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ); 577 index = 1; 578 579 if (ts_num) { 580 ret = pvt_get_regmap(pdev, "ts", pvt); 581 if (ret) 582 return ret; 583 584 temp_config = devm_kcalloc(dev, ts_num + 1, 585 sizeof(*temp_config), GFP_KERNEL); 586 if (!temp_config) 587 return -ENOMEM; 588 589 memset32(temp_config, HWMON_T_INPUT, ts_num); 590 pvt_temp.config = temp_config; 591 pvt_info[index++] = &pvt_temp; 592 } 593 594 if (pd_num) { 595 ret = pvt_get_regmap(pdev, "pd", pvt); 596 if (ret) 597 return ret; 598 } 599 600 if (vm_num) { 601 u32 total_ch; 602 603 ret = pvt_get_regmap(pdev, "vm", pvt); 604 if (ret) 605 return ret; 606 607 pvt->vm_idx = devm_kcalloc(dev, vm_num, sizeof(*pvt->vm_idx), 608 GFP_KERNEL); 609 if (!pvt->vm_idx) 610 return -ENOMEM; 611 612 ret = device_property_read_u8_array(dev, "intel,vm-map", 613 pvt->vm_idx, vm_num); 614 if (ret) { 615 /* 616 * Incase intel,vm-map property is not defined, we 617 * assume incremental channel numbers. 618 */ 619 for (i = 0; i < vm_num; i++) 620 pvt->vm_idx[i] = i; 621 } else { 622 for (i = 0; i < vm_num; i++) 623 if (pvt->vm_idx[i] >= vm_num || 624 pvt->vm_idx[i] == 0xff) { 625 pvt->v_num = i; 626 vm_num = i; 627 break; 628 } 629 } 630 631 total_ch = ch_num * vm_num; 632 in_config = devm_kcalloc(dev, total_ch + 1, 633 sizeof(*in_config), GFP_KERNEL); 634 if (!in_config) 635 return -ENOMEM; 636 637 memset32(in_config, HWMON_I_INPUT, total_ch); 638 in_config[total_ch] = 0; 639 pvt_in.config = in_config; 640 641 pvt_info[index++] = &pvt_in; 642 } 643 644 ret = pvt_init(pvt); 645 if (ret) { 646 dev_err(dev, "failed to init pvt: %d\n", ret); 647 return ret; 648 } 649 650 pvt_chip_info.info = pvt_info; 651 hwmon_dev = devm_hwmon_device_register_with_info(dev, "pvt", 652 pvt, 653 &pvt_chip_info, 654 NULL); 655 656 return PTR_ERR_OR_ZERO(hwmon_dev); 657 } 658 659 static const struct of_device_id moortec_pvt_of_match[] = { 660 { .compatible = "moortec,mr75203" }, 661 { } 662 }; 663 MODULE_DEVICE_TABLE(of, moortec_pvt_of_match); 664 665 static struct platform_driver moortec_pvt_driver = { 666 .driver = { 667 .name = "moortec-pvt", 668 .of_match_table = moortec_pvt_of_match, 669 }, 670 .probe = mr75203_probe, 671 }; 672 module_platform_driver(moortec_pvt_driver); 673 674 MODULE_LICENSE("GPL v2"); 675