1 /* 2 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring 3 * 4 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de> 5 * 6 * 7 * This driver is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This driver is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 14 * See the GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this driver; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/err.h> 21 #include <linux/hwmon.h> 22 #include <linux/hwmon-sysfs.h> 23 #include <linux/init.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <asm/amd_nb.h> 28 #include <asm/processor.h> 29 30 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); 31 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); 32 MODULE_LICENSE("GPL"); 33 34 static bool force; 35 module_param(force, bool, 0444); 36 MODULE_PARM_DESC(force, "force loading on processors with erratum 319"); 37 38 /* Provide lock for writing to NB_SMU_IND_ADDR */ 39 static DEFINE_MUTEX(nb_smu_ind_mutex); 40 41 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 42 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3 43 #endif 44 45 /* CPUID function 0x80000001, ebx */ 46 #define CPUID_PKGTYPE_MASK 0xf0000000 47 #define CPUID_PKGTYPE_F 0x00000000 48 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 49 50 /* DRAM controller (PCI function 2) */ 51 #define REG_DCT0_CONFIG_HIGH 0x094 52 #define DDR3_MODE 0x00000100 53 54 /* miscellaneous (PCI function 3) */ 55 #define REG_HARDWARE_THERMAL_CONTROL 0x64 56 #define HTC_ENABLE 0x00000001 57 58 #define REG_REPORTED_TEMPERATURE 0xa4 59 60 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 61 #define NB_CAP_HTC 0x00000400 62 63 /* 64 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL 65 * and REG_REPORTED_TEMPERATURE have been moved to 66 * D0F0xBC_xD820_0C64 [Hardware Temperature Control] 67 * D0F0xBC_xD820_0CA4 [Reported Temperature Control] 68 */ 69 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 70 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 71 72 /* F17h M01h Access througn SMN */ 73 #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800 74 75 struct k10temp_data { 76 struct pci_dev *pdev; 77 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); 78 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); 79 int temp_offset; 80 u32 temp_adjust_mask; 81 bool show_tdie; 82 }; 83 84 struct tctl_offset { 85 u8 model; 86 char const *id; 87 int offset; 88 }; 89 90 static const struct tctl_offset tctl_offset_table[] = { 91 { 0x17, "AMD Ryzen 5 1600X", 20000 }, 92 { 0x17, "AMD Ryzen 7 1700X", 20000 }, 93 { 0x17, "AMD Ryzen 7 1800X", 20000 }, 94 { 0x17, "AMD Ryzen 7 2700X", 10000 }, 95 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */ 96 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */ 97 }; 98 99 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) 100 { 101 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); 102 } 103 104 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) 105 { 106 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); 107 } 108 109 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, 110 unsigned int base, int offset, u32 *val) 111 { 112 mutex_lock(&nb_smu_ind_mutex); 113 pci_bus_write_config_dword(pdev->bus, devfn, 114 base, offset); 115 pci_bus_read_config_dword(pdev->bus, devfn, 116 base + 4, val); 117 mutex_unlock(&nb_smu_ind_mutex); 118 } 119 120 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) 121 { 122 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 123 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); 124 } 125 126 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) 127 { 128 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 129 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); 130 } 131 132 static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval) 133 { 134 amd_smn_read(amd_pci_dev_to_node_id(pdev), 135 F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval); 136 } 137 138 static unsigned int get_raw_temp(struct k10temp_data *data) 139 { 140 unsigned int temp; 141 u32 regval; 142 143 data->read_tempreg(data->pdev, ®val); 144 temp = (regval >> 21) * 125; 145 if (regval & data->temp_adjust_mask) 146 temp -= 49000; 147 return temp; 148 } 149 150 static ssize_t temp1_input_show(struct device *dev, 151 struct device_attribute *attr, char *buf) 152 { 153 struct k10temp_data *data = dev_get_drvdata(dev); 154 unsigned int temp = get_raw_temp(data); 155 156 if (temp > data->temp_offset) 157 temp -= data->temp_offset; 158 else 159 temp = 0; 160 161 return sprintf(buf, "%u\n", temp); 162 } 163 164 static ssize_t temp2_input_show(struct device *dev, 165 struct device_attribute *devattr, char *buf) 166 { 167 struct k10temp_data *data = dev_get_drvdata(dev); 168 unsigned int temp = get_raw_temp(data); 169 170 return sprintf(buf, "%u\n", temp); 171 } 172 173 static ssize_t temp_label_show(struct device *dev, 174 struct device_attribute *devattr, char *buf) 175 { 176 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); 177 178 return sprintf(buf, "%s\n", attr->index ? "Tctl" : "Tdie"); 179 } 180 181 static ssize_t temp1_max_show(struct device *dev, 182 struct device_attribute *attr, char *buf) 183 { 184 return sprintf(buf, "%d\n", 70 * 1000); 185 } 186 187 static ssize_t temp_crit_show(struct device *dev, 188 struct device_attribute *devattr, char *buf) 189 { 190 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); 191 struct k10temp_data *data = dev_get_drvdata(dev); 192 int show_hyst = attr->index; 193 u32 regval; 194 int value; 195 196 data->read_htcreg(data->pdev, ®val); 197 value = ((regval >> 16) & 0x7f) * 500 + 52000; 198 if (show_hyst) 199 value -= ((regval >> 24) & 0xf) * 500; 200 return sprintf(buf, "%d\n", value); 201 } 202 203 static DEVICE_ATTR_RO(temp1_input); 204 static DEVICE_ATTR_RO(temp1_max); 205 static SENSOR_DEVICE_ATTR_RO(temp1_crit, temp_crit, 0); 206 static SENSOR_DEVICE_ATTR_RO(temp1_crit_hyst, temp_crit, 1); 207 208 static SENSOR_DEVICE_ATTR_RO(temp1_label, temp_label, 0); 209 static DEVICE_ATTR_RO(temp2_input); 210 static SENSOR_DEVICE_ATTR_RO(temp2_label, temp_label, 1); 211 212 static umode_t k10temp_is_visible(struct kobject *kobj, 213 struct attribute *attr, int index) 214 { 215 struct device *dev = container_of(kobj, struct device, kobj); 216 struct k10temp_data *data = dev_get_drvdata(dev); 217 struct pci_dev *pdev = data->pdev; 218 u32 reg; 219 220 switch (index) { 221 case 0 ... 1: /* temp1_input, temp1_max */ 222 default: 223 break; 224 case 2 ... 3: /* temp1_crit, temp1_crit_hyst */ 225 if (!data->read_htcreg) 226 return 0; 227 228 pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES, 229 ®); 230 if (!(reg & NB_CAP_HTC)) 231 return 0; 232 233 data->read_htcreg(data->pdev, ®); 234 if (!(reg & HTC_ENABLE)) 235 return 0; 236 break; 237 case 4 ... 6: /* temp1_label, temp2_input, temp2_label */ 238 if (!data->show_tdie) 239 return 0; 240 break; 241 } 242 return attr->mode; 243 } 244 245 static struct attribute *k10temp_attrs[] = { 246 &dev_attr_temp1_input.attr, 247 &dev_attr_temp1_max.attr, 248 &sensor_dev_attr_temp1_crit.dev_attr.attr, 249 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 250 &sensor_dev_attr_temp1_label.dev_attr.attr, 251 &dev_attr_temp2_input.attr, 252 &sensor_dev_attr_temp2_label.dev_attr.attr, 253 NULL 254 }; 255 256 static const struct attribute_group k10temp_group = { 257 .attrs = k10temp_attrs, 258 .is_visible = k10temp_is_visible, 259 }; 260 __ATTRIBUTE_GROUPS(k10temp); 261 262 static bool has_erratum_319(struct pci_dev *pdev) 263 { 264 u32 pkg_type, reg_dram_cfg; 265 266 if (boot_cpu_data.x86 != 0x10) 267 return false; 268 269 /* 270 * Erratum 319: The thermal sensor of Socket F/AM2+ processors 271 * may be unreliable. 272 */ 273 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; 274 if (pkg_type == CPUID_PKGTYPE_F) 275 return true; 276 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) 277 return false; 278 279 /* DDR3 memory implies socket AM3, which is good */ 280 pci_bus_read_config_dword(pdev->bus, 281 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), 282 REG_DCT0_CONFIG_HIGH, ®_dram_cfg); 283 if (reg_dram_cfg & DDR3_MODE) 284 return false; 285 286 /* 287 * Unfortunately it is possible to run a socket AM3 CPU with DDR2 288 * memory. We blacklist all the cores which do exist in socket AM2+ 289 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+ 290 * and AM3 formats, but that's the best we can do. 291 */ 292 return boot_cpu_data.x86_model < 4 || 293 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2); 294 } 295 296 static int k10temp_probe(struct pci_dev *pdev, 297 const struct pci_device_id *id) 298 { 299 int unreliable = has_erratum_319(pdev); 300 struct device *dev = &pdev->dev; 301 struct k10temp_data *data; 302 struct device *hwmon_dev; 303 int i; 304 305 if (unreliable) { 306 if (!force) { 307 dev_err(dev, 308 "unreliable CPU thermal sensor; monitoring disabled\n"); 309 return -ENODEV; 310 } 311 dev_warn(dev, 312 "unreliable CPU thermal sensor; check erratum 319\n"); 313 } 314 315 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 316 if (!data) 317 return -ENOMEM; 318 319 data->pdev = pdev; 320 321 if (boot_cpu_data.x86 == 0x15 && 322 ((boot_cpu_data.x86_model & 0xf0) == 0x60 || 323 (boot_cpu_data.x86_model & 0xf0) == 0x70)) { 324 data->read_htcreg = read_htcreg_nb_f15; 325 data->read_tempreg = read_tempreg_nb_f15; 326 } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) { 327 data->temp_adjust_mask = 0x80000; 328 data->read_tempreg = read_tempreg_nb_f17; 329 data->show_tdie = true; 330 } else { 331 data->read_htcreg = read_htcreg_pci; 332 data->read_tempreg = read_tempreg_pci; 333 } 334 335 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) { 336 const struct tctl_offset *entry = &tctl_offset_table[i]; 337 338 if (boot_cpu_data.x86 == entry->model && 339 strstr(boot_cpu_data.x86_model_id, entry->id)) { 340 data->temp_offset = entry->offset; 341 break; 342 } 343 } 344 345 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data, 346 k10temp_groups); 347 return PTR_ERR_OR_ZERO(hwmon_dev); 348 } 349 350 static const struct pci_device_id k10temp_id_table[] = { 351 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, 352 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, 353 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, 354 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, 355 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, 356 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, 357 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, 358 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) }, 359 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, 360 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, 361 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 362 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) }, 363 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) }, 364 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 365 {} 366 }; 367 MODULE_DEVICE_TABLE(pci, k10temp_id_table); 368 369 static struct pci_driver k10temp_driver = { 370 .name = "k10temp", 371 .id_table = k10temp_id_table, 372 .probe = k10temp_probe, 373 }; 374 375 module_pci_driver(k10temp_driver); 376