1 /* 2 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring 3 * 4 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de> 5 * 6 * 7 * This driver is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This driver is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 14 * See the GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this driver; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/err.h> 21 #include <linux/hwmon.h> 22 #include <linux/hwmon-sysfs.h> 23 #include <linux/init.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <asm/amd_nb.h> 27 #include <asm/processor.h> 28 29 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); 30 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); 31 MODULE_LICENSE("GPL"); 32 33 static bool force; 34 module_param(force, bool, 0444); 35 MODULE_PARM_DESC(force, "force loading on processors with erratum 319"); 36 37 /* Provide lock for writing to NB_SMU_IND_ADDR */ 38 static DEFINE_MUTEX(nb_smu_ind_mutex); 39 40 #ifndef PCI_DEVICE_ID_AMD_17H_DF_F3 41 #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463 42 #endif 43 44 #ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 45 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb 46 #endif 47 48 /* CPUID function 0x80000001, ebx */ 49 #define CPUID_PKGTYPE_MASK 0xf0000000 50 #define CPUID_PKGTYPE_F 0x00000000 51 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 52 53 /* DRAM controller (PCI function 2) */ 54 #define REG_DCT0_CONFIG_HIGH 0x094 55 #define DDR3_MODE 0x00000100 56 57 /* miscellaneous (PCI function 3) */ 58 #define REG_HARDWARE_THERMAL_CONTROL 0x64 59 #define HTC_ENABLE 0x00000001 60 61 #define REG_REPORTED_TEMPERATURE 0xa4 62 63 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 64 #define NB_CAP_HTC 0x00000400 65 66 /* 67 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL 68 * and REG_REPORTED_TEMPERATURE have been moved to 69 * D0F0xBC_xD820_0C64 [Hardware Temperature Control] 70 * D0F0xBC_xD820_0CA4 [Reported Temperature Control] 71 */ 72 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 73 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 74 75 /* F17h M01h Access througn SMN */ 76 #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800 77 78 struct k10temp_data { 79 struct pci_dev *pdev; 80 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); 81 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); 82 int temp_offset; 83 u32 temp_adjust_mask; 84 }; 85 86 struct tctl_offset { 87 u8 model; 88 char const *id; 89 int offset; 90 }; 91 92 static const struct tctl_offset tctl_offset_table[] = { 93 { 0x17, "AMD Ryzen 5 1600X", 20000 }, 94 { 0x17, "AMD Ryzen 7 1700X", 20000 }, 95 { 0x17, "AMD Ryzen 7 1800X", 20000 }, 96 { 0x17, "AMD Ryzen 7 2700X", 10000 }, 97 { 0x17, "AMD Ryzen Threadripper 1950X", 27000 }, 98 { 0x17, "AMD Ryzen Threadripper 1920X", 27000 }, 99 { 0x17, "AMD Ryzen Threadripper 1900X", 27000 }, 100 { 0x17, "AMD Ryzen Threadripper 1950", 10000 }, 101 { 0x17, "AMD Ryzen Threadripper 1920", 10000 }, 102 { 0x17, "AMD Ryzen Threadripper 1910", 10000 }, 103 }; 104 105 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) 106 { 107 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); 108 } 109 110 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) 111 { 112 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); 113 } 114 115 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, 116 unsigned int base, int offset, u32 *val) 117 { 118 mutex_lock(&nb_smu_ind_mutex); 119 pci_bus_write_config_dword(pdev->bus, devfn, 120 base, offset); 121 pci_bus_read_config_dword(pdev->bus, devfn, 122 base + 4, val); 123 mutex_unlock(&nb_smu_ind_mutex); 124 } 125 126 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) 127 { 128 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 129 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); 130 } 131 132 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) 133 { 134 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 135 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); 136 } 137 138 static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval) 139 { 140 amd_smn_read(amd_pci_dev_to_node_id(pdev), 141 F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval); 142 } 143 144 static ssize_t temp1_input_show(struct device *dev, 145 struct device_attribute *attr, char *buf) 146 { 147 struct k10temp_data *data = dev_get_drvdata(dev); 148 u32 regval; 149 unsigned int temp; 150 151 data->read_tempreg(data->pdev, ®val); 152 temp = (regval >> 21) * 125; 153 if (regval & data->temp_adjust_mask) 154 temp -= 49000; 155 if (temp > data->temp_offset) 156 temp -= data->temp_offset; 157 else 158 temp = 0; 159 160 return sprintf(buf, "%u\n", temp); 161 } 162 163 static ssize_t temp1_max_show(struct device *dev, 164 struct device_attribute *attr, char *buf) 165 { 166 return sprintf(buf, "%d\n", 70 * 1000); 167 } 168 169 static ssize_t show_temp_crit(struct device *dev, 170 struct device_attribute *devattr, char *buf) 171 { 172 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); 173 struct k10temp_data *data = dev_get_drvdata(dev); 174 int show_hyst = attr->index; 175 u32 regval; 176 int value; 177 178 data->read_htcreg(data->pdev, ®val); 179 value = ((regval >> 16) & 0x7f) * 500 + 52000; 180 if (show_hyst) 181 value -= ((regval >> 24) & 0xf) * 500; 182 return sprintf(buf, "%d\n", value); 183 } 184 185 static DEVICE_ATTR_RO(temp1_input); 186 static DEVICE_ATTR_RO(temp1_max); 187 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0); 188 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1); 189 190 static umode_t k10temp_is_visible(struct kobject *kobj, 191 struct attribute *attr, int index) 192 { 193 struct device *dev = container_of(kobj, struct device, kobj); 194 struct k10temp_data *data = dev_get_drvdata(dev); 195 struct pci_dev *pdev = data->pdev; 196 197 if (index >= 2) { 198 u32 reg; 199 200 if (!data->read_htcreg) 201 return 0; 202 203 pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES, 204 ®); 205 if (!(reg & NB_CAP_HTC)) 206 return 0; 207 208 data->read_htcreg(data->pdev, ®); 209 if (!(reg & HTC_ENABLE)) 210 return 0; 211 } 212 return attr->mode; 213 } 214 215 static struct attribute *k10temp_attrs[] = { 216 &dev_attr_temp1_input.attr, 217 &dev_attr_temp1_max.attr, 218 &sensor_dev_attr_temp1_crit.dev_attr.attr, 219 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 220 NULL 221 }; 222 223 static const struct attribute_group k10temp_group = { 224 .attrs = k10temp_attrs, 225 .is_visible = k10temp_is_visible, 226 }; 227 __ATTRIBUTE_GROUPS(k10temp); 228 229 static bool has_erratum_319(struct pci_dev *pdev) 230 { 231 u32 pkg_type, reg_dram_cfg; 232 233 if (boot_cpu_data.x86 != 0x10) 234 return false; 235 236 /* 237 * Erratum 319: The thermal sensor of Socket F/AM2+ processors 238 * may be unreliable. 239 */ 240 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; 241 if (pkg_type == CPUID_PKGTYPE_F) 242 return true; 243 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) 244 return false; 245 246 /* DDR3 memory implies socket AM3, which is good */ 247 pci_bus_read_config_dword(pdev->bus, 248 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), 249 REG_DCT0_CONFIG_HIGH, ®_dram_cfg); 250 if (reg_dram_cfg & DDR3_MODE) 251 return false; 252 253 /* 254 * Unfortunately it is possible to run a socket AM3 CPU with DDR2 255 * memory. We blacklist all the cores which do exist in socket AM2+ 256 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+ 257 * and AM3 formats, but that's the best we can do. 258 */ 259 return boot_cpu_data.x86_model < 4 || 260 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2); 261 } 262 263 static int k10temp_probe(struct pci_dev *pdev, 264 const struct pci_device_id *id) 265 { 266 int unreliable = has_erratum_319(pdev); 267 struct device *dev = &pdev->dev; 268 struct k10temp_data *data; 269 struct device *hwmon_dev; 270 int i; 271 272 if (unreliable) { 273 if (!force) { 274 dev_err(dev, 275 "unreliable CPU thermal sensor; monitoring disabled\n"); 276 return -ENODEV; 277 } 278 dev_warn(dev, 279 "unreliable CPU thermal sensor; check erratum 319\n"); 280 } 281 282 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 283 if (!data) 284 return -ENOMEM; 285 286 data->pdev = pdev; 287 288 if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 || 289 boot_cpu_data.x86_model == 0x70)) { 290 data->read_htcreg = read_htcreg_nb_f15; 291 data->read_tempreg = read_tempreg_nb_f15; 292 } else if (boot_cpu_data.x86 == 0x17) { 293 data->temp_adjust_mask = 0x80000; 294 data->read_tempreg = read_tempreg_nb_f17; 295 } else { 296 data->read_htcreg = read_htcreg_pci; 297 data->read_tempreg = read_tempreg_pci; 298 } 299 300 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) { 301 const struct tctl_offset *entry = &tctl_offset_table[i]; 302 303 if (boot_cpu_data.x86 == entry->model && 304 strstr(boot_cpu_data.x86_model_id, entry->id)) { 305 data->temp_offset = entry->offset; 306 break; 307 } 308 } 309 310 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data, 311 k10temp_groups); 312 return PTR_ERR_OR_ZERO(hwmon_dev); 313 } 314 315 static const struct pci_device_id k10temp_id_table[] = { 316 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, 317 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, 318 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, 319 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, 320 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, 321 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, 322 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, 323 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, 324 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, 325 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 326 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) }, 327 {} 328 }; 329 MODULE_DEVICE_TABLE(pci, k10temp_id_table); 330 331 static struct pci_driver k10temp_driver = { 332 .name = "k10temp", 333 .id_table = k10temp_id_table, 334 .probe = k10temp_probe, 335 }; 336 337 module_pci_driver(k10temp_driver); 338