1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h 4 * processor hardware monitoring 5 * 6 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de> 7 * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net> 8 * 9 * Implementation notes: 10 * - CCD register address information as well as the calculation to 11 * convert raw register values is from https://github.com/ocerman/zenpower. 12 * The information is not confirmed from chip datasheets, but experiments 13 * suggest that it provides reasonable temperature values. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/err.h> 18 #include <linux/hwmon.h> 19 #include <linux/init.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/pci_ids.h> 23 #include <asm/amd_nb.h> 24 #include <asm/processor.h> 25 26 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); 27 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); 28 MODULE_LICENSE("GPL"); 29 30 static bool force; 31 module_param(force, bool, 0444); 32 MODULE_PARM_DESC(force, "force loading on processors with erratum 319"); 33 34 /* Provide lock for writing to NB_SMU_IND_ADDR */ 35 static DEFINE_MUTEX(nb_smu_ind_mutex); 36 37 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 38 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3 39 #endif 40 41 /* CPUID function 0x80000001, ebx */ 42 #define CPUID_PKGTYPE_MASK GENMASK(31, 28) 43 #define CPUID_PKGTYPE_F 0x00000000 44 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 45 46 /* DRAM controller (PCI function 2) */ 47 #define REG_DCT0_CONFIG_HIGH 0x094 48 #define DDR3_MODE BIT(8) 49 50 /* miscellaneous (PCI function 3) */ 51 #define REG_HARDWARE_THERMAL_CONTROL 0x64 52 #define HTC_ENABLE BIT(0) 53 54 #define REG_REPORTED_TEMPERATURE 0xa4 55 56 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 57 #define NB_CAP_HTC BIT(10) 58 59 /* 60 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL 61 * and REG_REPORTED_TEMPERATURE have been moved to 62 * D0F0xBC_xD820_0C64 [Hardware Temperature Control] 63 * D0F0xBC_xD820_0CA4 [Reported Temperature Control] 64 */ 65 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 66 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 67 68 /* Common for Zen CPU families (Family 17h and 18h) */ 69 #define ZEN_REPORTED_TEMP_CTRL_OFFSET 0x00059800 70 71 #define ZEN_CCD_TEMP(x) (0x00059954 + ((x) * 4)) 72 #define ZEN_CCD_TEMP_VALID BIT(11) 73 #define ZEN_CCD_TEMP_MASK GENMASK(10, 0) 74 75 #define ZEN_CUR_TEMP_SHIFT 21 76 #define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19) 77 78 #define ZEN_SVI_BASE 0x0005A000 79 80 /* F17h thermal registers through SMN */ 81 #define F17H_M01H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0xc) 82 #define F17H_M01H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) 83 #define F17H_M31H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14) 84 #define F17H_M31H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) 85 86 #define F17H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */ 87 #define F17H_M01H_CFACTOR_ISOC 250000 /* 0.25A / LSB */ 88 #define F17H_M31H_CFACTOR_ICORE 1000000 /* 1A / LSB */ 89 #define F17H_M31H_CFACTOR_ISOC 310000 /* 0.31A / LSB */ 90 91 /* F19h thermal registers through SMN */ 92 #define F19H_M01_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14) 93 #define F19H_M01_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) 94 95 #define F19H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */ 96 #define F19H_M01H_CFACTOR_ISOC 310000 /* 0.31A / LSB */ 97 98 struct k10temp_data { 99 struct pci_dev *pdev; 100 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); 101 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); 102 int temp_offset; 103 u32 temp_adjust_mask; 104 u32 show_temp; 105 bool is_zen; 106 }; 107 108 #define TCTL_BIT 0 109 #define TDIE_BIT 1 110 #define TCCD_BIT(x) ((x) + 2) 111 112 #define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel)) 113 #define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT) 114 115 struct tctl_offset { 116 u8 model; 117 char const *id; 118 int offset; 119 }; 120 121 static const struct tctl_offset tctl_offset_table[] = { 122 { 0x17, "AMD Ryzen 5 1600X", 20000 }, 123 { 0x17, "AMD Ryzen 7 1700X", 20000 }, 124 { 0x17, "AMD Ryzen 7 1800X", 20000 }, 125 { 0x17, "AMD Ryzen 7 2700X", 10000 }, 126 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */ 127 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */ 128 }; 129 130 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) 131 { 132 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); 133 } 134 135 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) 136 { 137 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); 138 } 139 140 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, 141 unsigned int base, int offset, u32 *val) 142 { 143 mutex_lock(&nb_smu_ind_mutex); 144 pci_bus_write_config_dword(pdev->bus, devfn, 145 base, offset); 146 pci_bus_read_config_dword(pdev->bus, devfn, 147 base + 4, val); 148 mutex_unlock(&nb_smu_ind_mutex); 149 } 150 151 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) 152 { 153 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 154 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); 155 } 156 157 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) 158 { 159 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 160 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); 161 } 162 163 static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval) 164 { 165 amd_smn_read(amd_pci_dev_to_node_id(pdev), 166 ZEN_REPORTED_TEMP_CTRL_OFFSET, regval); 167 } 168 169 static long get_raw_temp(struct k10temp_data *data) 170 { 171 u32 regval; 172 long temp; 173 174 data->read_tempreg(data->pdev, ®val); 175 temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125; 176 if (regval & data->temp_adjust_mask) 177 temp -= 49000; 178 return temp; 179 } 180 181 static const char *k10temp_temp_label[] = { 182 "Tctl", 183 "Tdie", 184 "Tccd1", 185 "Tccd2", 186 "Tccd3", 187 "Tccd4", 188 "Tccd5", 189 "Tccd6", 190 "Tccd7", 191 "Tccd8", 192 }; 193 194 static int k10temp_read_labels(struct device *dev, 195 enum hwmon_sensor_types type, 196 u32 attr, int channel, const char **str) 197 { 198 switch (type) { 199 case hwmon_temp: 200 *str = k10temp_temp_label[channel]; 201 break; 202 default: 203 return -EOPNOTSUPP; 204 } 205 return 0; 206 } 207 208 static int k10temp_read_temp(struct device *dev, u32 attr, int channel, 209 long *val) 210 { 211 struct k10temp_data *data = dev_get_drvdata(dev); 212 u32 regval; 213 214 switch (attr) { 215 case hwmon_temp_input: 216 switch (channel) { 217 case 0: /* Tctl */ 218 *val = get_raw_temp(data); 219 if (*val < 0) 220 *val = 0; 221 break; 222 case 1: /* Tdie */ 223 *val = get_raw_temp(data) - data->temp_offset; 224 if (*val < 0) 225 *val = 0; 226 break; 227 case 2 ... 9: /* Tccd{1-8} */ 228 amd_smn_read(amd_pci_dev_to_node_id(data->pdev), 229 ZEN_CCD_TEMP(channel - 2), ®val); 230 *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000; 231 break; 232 default: 233 return -EOPNOTSUPP; 234 } 235 break; 236 case hwmon_temp_max: 237 *val = 70 * 1000; 238 break; 239 case hwmon_temp_crit: 240 data->read_htcreg(data->pdev, ®val); 241 *val = ((regval >> 16) & 0x7f) * 500 + 52000; 242 break; 243 case hwmon_temp_crit_hyst: 244 data->read_htcreg(data->pdev, ®val); 245 *val = (((regval >> 16) & 0x7f) 246 - ((regval >> 24) & 0xf)) * 500 + 52000; 247 break; 248 default: 249 return -EOPNOTSUPP; 250 } 251 return 0; 252 } 253 254 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, 255 u32 attr, int channel, long *val) 256 { 257 switch (type) { 258 case hwmon_temp: 259 return k10temp_read_temp(dev, attr, channel, val); 260 default: 261 return -EOPNOTSUPP; 262 } 263 } 264 265 static umode_t k10temp_is_visible(const void *_data, 266 enum hwmon_sensor_types type, 267 u32 attr, int channel) 268 { 269 const struct k10temp_data *data = _data; 270 struct pci_dev *pdev = data->pdev; 271 u32 reg; 272 273 switch (type) { 274 case hwmon_temp: 275 switch (attr) { 276 case hwmon_temp_input: 277 if (!HAVE_TEMP(data, channel)) 278 return 0; 279 break; 280 case hwmon_temp_max: 281 if (channel || data->is_zen) 282 return 0; 283 break; 284 case hwmon_temp_crit: 285 case hwmon_temp_crit_hyst: 286 if (channel || !data->read_htcreg) 287 return 0; 288 289 pci_read_config_dword(pdev, 290 REG_NORTHBRIDGE_CAPABILITIES, 291 ®); 292 if (!(reg & NB_CAP_HTC)) 293 return 0; 294 295 data->read_htcreg(data->pdev, ®); 296 if (!(reg & HTC_ENABLE)) 297 return 0; 298 break; 299 case hwmon_temp_label: 300 /* Show temperature labels only on Zen CPUs */ 301 if (!data->is_zen || !HAVE_TEMP(data, channel)) 302 return 0; 303 break; 304 default: 305 return 0; 306 } 307 break; 308 default: 309 return 0; 310 } 311 return 0444; 312 } 313 314 static bool has_erratum_319(struct pci_dev *pdev) 315 { 316 u32 pkg_type, reg_dram_cfg; 317 318 if (boot_cpu_data.x86 != 0x10) 319 return false; 320 321 /* 322 * Erratum 319: The thermal sensor of Socket F/AM2+ processors 323 * may be unreliable. 324 */ 325 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; 326 if (pkg_type == CPUID_PKGTYPE_F) 327 return true; 328 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) 329 return false; 330 331 /* DDR3 memory implies socket AM3, which is good */ 332 pci_bus_read_config_dword(pdev->bus, 333 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), 334 REG_DCT0_CONFIG_HIGH, ®_dram_cfg); 335 if (reg_dram_cfg & DDR3_MODE) 336 return false; 337 338 /* 339 * Unfortunately it is possible to run a socket AM3 CPU with DDR2 340 * memory. We blacklist all the cores which do exist in socket AM2+ 341 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+ 342 * and AM3 formats, but that's the best we can do. 343 */ 344 return boot_cpu_data.x86_model < 4 || 345 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2); 346 } 347 348 static const struct hwmon_channel_info *k10temp_info[] = { 349 HWMON_CHANNEL_INFO(temp, 350 HWMON_T_INPUT | HWMON_T_MAX | 351 HWMON_T_CRIT | HWMON_T_CRIT_HYST | 352 HWMON_T_LABEL, 353 HWMON_T_INPUT | HWMON_T_LABEL, 354 HWMON_T_INPUT | HWMON_T_LABEL, 355 HWMON_T_INPUT | HWMON_T_LABEL, 356 HWMON_T_INPUT | HWMON_T_LABEL, 357 HWMON_T_INPUT | HWMON_T_LABEL, 358 HWMON_T_INPUT | HWMON_T_LABEL, 359 HWMON_T_INPUT | HWMON_T_LABEL, 360 HWMON_T_INPUT | HWMON_T_LABEL, 361 HWMON_T_INPUT | HWMON_T_LABEL), 362 HWMON_CHANNEL_INFO(in, 363 HWMON_I_INPUT | HWMON_I_LABEL, 364 HWMON_I_INPUT | HWMON_I_LABEL), 365 HWMON_CHANNEL_INFO(curr, 366 HWMON_C_INPUT | HWMON_C_LABEL, 367 HWMON_C_INPUT | HWMON_C_LABEL), 368 NULL 369 }; 370 371 static const struct hwmon_ops k10temp_hwmon_ops = { 372 .is_visible = k10temp_is_visible, 373 .read = k10temp_read, 374 .read_string = k10temp_read_labels, 375 }; 376 377 static const struct hwmon_chip_info k10temp_chip_info = { 378 .ops = &k10temp_hwmon_ops, 379 .info = k10temp_info, 380 }; 381 382 static void k10temp_get_ccd_support(struct pci_dev *pdev, 383 struct k10temp_data *data, int limit) 384 { 385 u32 regval; 386 int i; 387 388 for (i = 0; i < limit; i++) { 389 amd_smn_read(amd_pci_dev_to_node_id(pdev), 390 ZEN_CCD_TEMP(i), ®val); 391 if (regval & ZEN_CCD_TEMP_VALID) 392 data->show_temp |= BIT(TCCD_BIT(i)); 393 } 394 } 395 396 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) 397 { 398 int unreliable = has_erratum_319(pdev); 399 struct device *dev = &pdev->dev; 400 struct k10temp_data *data; 401 struct device *hwmon_dev; 402 int i; 403 404 if (unreliable) { 405 if (!force) { 406 dev_err(dev, 407 "unreliable CPU thermal sensor; monitoring disabled\n"); 408 return -ENODEV; 409 } 410 dev_warn(dev, 411 "unreliable CPU thermal sensor; check erratum 319\n"); 412 } 413 414 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 415 if (!data) 416 return -ENOMEM; 417 418 data->pdev = pdev; 419 data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */ 420 421 if (boot_cpu_data.x86 == 0x15 && 422 ((boot_cpu_data.x86_model & 0xf0) == 0x60 || 423 (boot_cpu_data.x86_model & 0xf0) == 0x70)) { 424 data->read_htcreg = read_htcreg_nb_f15; 425 data->read_tempreg = read_tempreg_nb_f15; 426 } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) { 427 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; 428 data->read_tempreg = read_tempreg_nb_zen; 429 data->show_temp |= BIT(TDIE_BIT); /* show Tdie */ 430 data->is_zen = true; 431 432 switch (boot_cpu_data.x86_model) { 433 case 0x1: /* Zen */ 434 case 0x8: /* Zen+ */ 435 case 0x11: /* Zen APU */ 436 case 0x18: /* Zen+ APU */ 437 k10temp_get_ccd_support(pdev, data, 4); 438 break; 439 case 0x31: /* Zen2 Threadripper */ 440 case 0x71: /* Zen2 */ 441 k10temp_get_ccd_support(pdev, data, 8); 442 break; 443 } 444 } else if (boot_cpu_data.x86 == 0x19) { 445 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; 446 data->read_tempreg = read_tempreg_nb_zen; 447 data->show_temp |= BIT(TDIE_BIT); 448 data->is_zen = true; 449 450 switch (boot_cpu_data.x86_model) { 451 case 0x0 ... 0x1: /* Zen3 */ 452 k10temp_get_ccd_support(pdev, data, 8); 453 break; 454 } 455 } else { 456 data->read_htcreg = read_htcreg_pci; 457 data->read_tempreg = read_tempreg_pci; 458 } 459 460 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) { 461 const struct tctl_offset *entry = &tctl_offset_table[i]; 462 463 if (boot_cpu_data.x86 == entry->model && 464 strstr(boot_cpu_data.x86_model_id, entry->id)) { 465 data->temp_offset = entry->offset; 466 break; 467 } 468 } 469 470 hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data, 471 &k10temp_chip_info, 472 NULL); 473 return PTR_ERR_OR_ZERO(hwmon_dev); 474 } 475 476 static const struct pci_device_id k10temp_id_table[] = { 477 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, 478 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, 479 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, 480 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, 481 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, 482 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, 483 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, 484 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) }, 485 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, 486 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, 487 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 488 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) }, 489 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) }, 490 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) }, 491 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) }, 492 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) }, 493 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 494 {} 495 }; 496 MODULE_DEVICE_TABLE(pci, k10temp_id_table); 497 498 static struct pci_driver k10temp_driver = { 499 .name = "k10temp", 500 .id_table = k10temp_id_table, 501 .probe = k10temp_probe, 502 }; 503 504 module_pci_driver(k10temp_driver); 505