1 /* 2 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring 3 * 4 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de> 5 * 6 * 7 * This driver is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This driver is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 14 * See the GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this driver; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/err.h> 21 #include <linux/hwmon.h> 22 #include <linux/hwmon-sysfs.h> 23 #include <linux/init.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <asm/processor.h> 27 28 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); 29 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); 30 MODULE_LICENSE("GPL"); 31 32 static bool force; 33 module_param(force, bool, 0444); 34 MODULE_PARM_DESC(force, "force loading on processors with erratum 319"); 35 36 /* Provide lock for writing to NB_SMU_IND_ADDR */ 37 static DEFINE_MUTEX(nb_smu_ind_mutex); 38 39 #ifndef PCI_DEVICE_ID_AMD_17H_DF_F3 40 #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463 41 #endif 42 43 #ifndef PCI_DEVICE_ID_AMD_17H_RR_NB 44 #define PCI_DEVICE_ID_AMD_17H_RR_NB 0x15d0 45 #endif 46 47 /* CPUID function 0x80000001, ebx */ 48 #define CPUID_PKGTYPE_MASK 0xf0000000 49 #define CPUID_PKGTYPE_F 0x00000000 50 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 51 52 /* DRAM controller (PCI function 2) */ 53 #define REG_DCT0_CONFIG_HIGH 0x094 54 #define DDR3_MODE 0x00000100 55 56 /* miscellaneous (PCI function 3) */ 57 #define REG_HARDWARE_THERMAL_CONTROL 0x64 58 #define HTC_ENABLE 0x00000001 59 60 #define REG_REPORTED_TEMPERATURE 0xa4 61 62 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 63 #define NB_CAP_HTC 0x00000400 64 65 /* 66 * For F15h M60h, functionality of REG_REPORTED_TEMPERATURE 67 * has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature 68 * Control] 69 */ 70 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 71 72 /* F17h M01h Access througn SMN */ 73 #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800 74 75 struct k10temp_data { 76 struct pci_dev *pdev; 77 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); 78 int temp_offset; 79 u32 temp_adjust_mask; 80 }; 81 82 struct tctl_offset { 83 u8 model; 84 char const *id; 85 int offset; 86 }; 87 88 static const struct tctl_offset tctl_offset_table[] = { 89 { 0x17, "AMD Ryzen 5 1600X", 20000 }, 90 { 0x17, "AMD Ryzen 7 1700X", 20000 }, 91 { 0x17, "AMD Ryzen 7 1800X", 20000 }, 92 { 0x17, "AMD Ryzen 7 2700X", 10000 }, 93 { 0x17, "AMD Ryzen Threadripper 1950X", 27000 }, 94 { 0x17, "AMD Ryzen Threadripper 1920X", 27000 }, 95 { 0x17, "AMD Ryzen Threadripper 1900X", 27000 }, 96 { 0x17, "AMD Ryzen Threadripper 1950", 10000 }, 97 { 0x17, "AMD Ryzen Threadripper 1920", 10000 }, 98 { 0x17, "AMD Ryzen Threadripper 1910", 10000 }, 99 }; 100 101 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) 102 { 103 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); 104 } 105 106 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, 107 unsigned int base, int offset, u32 *val) 108 { 109 mutex_lock(&nb_smu_ind_mutex); 110 pci_bus_write_config_dword(pdev->bus, devfn, 111 base, offset); 112 pci_bus_read_config_dword(pdev->bus, devfn, 113 base + 4, val); 114 mutex_unlock(&nb_smu_ind_mutex); 115 } 116 117 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) 118 { 119 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 120 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); 121 } 122 123 static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval) 124 { 125 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0x60, 126 F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval); 127 } 128 129 static ssize_t temp1_input_show(struct device *dev, 130 struct device_attribute *attr, char *buf) 131 { 132 struct k10temp_data *data = dev_get_drvdata(dev); 133 u32 regval; 134 unsigned int temp; 135 136 data->read_tempreg(data->pdev, ®val); 137 temp = (regval >> 21) * 125; 138 if (regval & data->temp_adjust_mask) 139 temp -= 49000; 140 if (temp > data->temp_offset) 141 temp -= data->temp_offset; 142 else 143 temp = 0; 144 145 return sprintf(buf, "%u\n", temp); 146 } 147 148 static ssize_t temp1_max_show(struct device *dev, 149 struct device_attribute *attr, char *buf) 150 { 151 return sprintf(buf, "%d\n", 70 * 1000); 152 } 153 154 static ssize_t show_temp_crit(struct device *dev, 155 struct device_attribute *devattr, char *buf) 156 { 157 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); 158 struct k10temp_data *data = dev_get_drvdata(dev); 159 int show_hyst = attr->index; 160 u32 regval; 161 int value; 162 163 pci_read_config_dword(data->pdev, 164 REG_HARDWARE_THERMAL_CONTROL, ®val); 165 value = ((regval >> 16) & 0x7f) * 500 + 52000; 166 if (show_hyst) 167 value -= ((regval >> 24) & 0xf) * 500; 168 return sprintf(buf, "%d\n", value); 169 } 170 171 static DEVICE_ATTR_RO(temp1_input); 172 static DEVICE_ATTR_RO(temp1_max); 173 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0); 174 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1); 175 176 static umode_t k10temp_is_visible(struct kobject *kobj, 177 struct attribute *attr, int index) 178 { 179 struct device *dev = container_of(kobj, struct device, kobj); 180 struct k10temp_data *data = dev_get_drvdata(dev); 181 struct pci_dev *pdev = data->pdev; 182 183 if (index >= 2) { 184 u32 reg_caps, reg_htc; 185 186 pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES, 187 ®_caps); 188 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, 189 ®_htc); 190 if (!(reg_caps & NB_CAP_HTC) || !(reg_htc & HTC_ENABLE)) 191 return 0; 192 } 193 return attr->mode; 194 } 195 196 static struct attribute *k10temp_attrs[] = { 197 &dev_attr_temp1_input.attr, 198 &dev_attr_temp1_max.attr, 199 &sensor_dev_attr_temp1_crit.dev_attr.attr, 200 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 201 NULL 202 }; 203 204 static const struct attribute_group k10temp_group = { 205 .attrs = k10temp_attrs, 206 .is_visible = k10temp_is_visible, 207 }; 208 __ATTRIBUTE_GROUPS(k10temp); 209 210 static bool has_erratum_319(struct pci_dev *pdev) 211 { 212 u32 pkg_type, reg_dram_cfg; 213 214 if (boot_cpu_data.x86 != 0x10) 215 return false; 216 217 /* 218 * Erratum 319: The thermal sensor of Socket F/AM2+ processors 219 * may be unreliable. 220 */ 221 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; 222 if (pkg_type == CPUID_PKGTYPE_F) 223 return true; 224 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) 225 return false; 226 227 /* DDR3 memory implies socket AM3, which is good */ 228 pci_bus_read_config_dword(pdev->bus, 229 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), 230 REG_DCT0_CONFIG_HIGH, ®_dram_cfg); 231 if (reg_dram_cfg & DDR3_MODE) 232 return false; 233 234 /* 235 * Unfortunately it is possible to run a socket AM3 CPU with DDR2 236 * memory. We blacklist all the cores which do exist in socket AM2+ 237 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+ 238 * and AM3 formats, but that's the best we can do. 239 */ 240 return boot_cpu_data.x86_model < 4 || 241 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2); 242 } 243 244 static int k10temp_probe(struct pci_dev *pdev, 245 const struct pci_device_id *id) 246 { 247 int unreliable = has_erratum_319(pdev); 248 struct device *dev = &pdev->dev; 249 struct k10temp_data *data; 250 struct device *hwmon_dev; 251 int i; 252 253 if (unreliable) { 254 if (!force) { 255 dev_err(dev, 256 "unreliable CPU thermal sensor; monitoring disabled\n"); 257 return -ENODEV; 258 } 259 dev_warn(dev, 260 "unreliable CPU thermal sensor; check erratum 319\n"); 261 } 262 263 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 264 if (!data) 265 return -ENOMEM; 266 267 data->pdev = pdev; 268 269 if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 || 270 boot_cpu_data.x86_model == 0x70)) { 271 data->read_tempreg = read_tempreg_nb_f15; 272 } else if (boot_cpu_data.x86 == 0x17) { 273 data->temp_adjust_mask = 0x80000; 274 data->read_tempreg = read_tempreg_nb_f17; 275 } else { 276 data->read_tempreg = read_tempreg_pci; 277 } 278 279 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) { 280 const struct tctl_offset *entry = &tctl_offset_table[i]; 281 282 if (boot_cpu_data.x86 == entry->model && 283 strstr(boot_cpu_data.x86_model_id, entry->id)) { 284 data->temp_offset = entry->offset; 285 break; 286 } 287 } 288 289 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data, 290 k10temp_groups); 291 return PTR_ERR_OR_ZERO(hwmon_dev); 292 } 293 294 static const struct pci_device_id k10temp_id_table[] = { 295 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, 296 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, 297 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, 298 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, 299 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, 300 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, 301 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, 302 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, 303 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, 304 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 305 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_RR_NB) }, 306 {} 307 }; 308 MODULE_DEVICE_TABLE(pci, k10temp_id_table); 309 310 static struct pci_driver k10temp_driver = { 311 .name = "k10temp", 312 .id_table = k10temp_id_table, 313 .probe = k10temp_probe, 314 }; 315 316 module_pci_driver(k10temp_driver); 317