13c57e89bSClemens Ladisch /* 230b146d1SWei Hu * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring 33c57e89bSClemens Ladisch * 43c57e89bSClemens Ladisch * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de> 53c57e89bSClemens Ladisch * 63c57e89bSClemens Ladisch * 73c57e89bSClemens Ladisch * This driver is free software; you can redistribute it and/or 83c57e89bSClemens Ladisch * modify it under the terms of the GNU General Public License; either 93c57e89bSClemens Ladisch * version 2 of the License, or (at your option) any later version. 103c57e89bSClemens Ladisch * 113c57e89bSClemens Ladisch * This driver is distributed in the hope that it will be useful, 123c57e89bSClemens Ladisch * but WITHOUT ANY WARRANTY; without even the implied warranty of 133c57e89bSClemens Ladisch * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 143c57e89bSClemens Ladisch * See the GNU General Public License for more details. 153c57e89bSClemens Ladisch * 163c57e89bSClemens Ladisch * You should have received a copy of the GNU General Public License 173c57e89bSClemens Ladisch * along with this driver; if not, see <http://www.gnu.org/licenses/>. 183c57e89bSClemens Ladisch */ 193c57e89bSClemens Ladisch 203c57e89bSClemens Ladisch #include <linux/err.h> 213c57e89bSClemens Ladisch #include <linux/hwmon.h> 223c57e89bSClemens Ladisch #include <linux/hwmon-sysfs.h> 233c57e89bSClemens Ladisch #include <linux/init.h> 243c57e89bSClemens Ladisch #include <linux/module.h> 253c57e89bSClemens Ladisch #include <linux/pci.h> 263c57e89bSClemens Ladisch #include <asm/processor.h> 273c57e89bSClemens Ladisch 289e581311SAndre Przywara MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); 293c57e89bSClemens Ladisch MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); 303c57e89bSClemens Ladisch MODULE_LICENSE("GPL"); 313c57e89bSClemens Ladisch 323c57e89bSClemens Ladisch static bool force; 333c57e89bSClemens Ladisch module_param(force, bool, 0444); 343c57e89bSClemens Ladisch MODULE_PARM_DESC(force, "force loading on processors with erratum 319"); 353c57e89bSClemens Ladisch 36f89ce270SAravind Gopalakrishnan /* Provide lock for writing to NB_SMU_IND_ADDR */ 37f89ce270SAravind Gopalakrishnan static DEFINE_MUTEX(nb_smu_ind_mutex); 38f89ce270SAravind Gopalakrishnan 399af0a9aeSGuenter Roeck #ifndef PCI_DEVICE_ID_AMD_17H_DF_F3 409af0a9aeSGuenter Roeck #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463 419af0a9aeSGuenter Roeck #endif 429af0a9aeSGuenter Roeck 43877d8948SGuenter Roeck #ifndef PCI_DEVICE_ID_AMD_17H_RR_NB 44877d8948SGuenter Roeck #define PCI_DEVICE_ID_AMD_17H_RR_NB 0x15d0 45877d8948SGuenter Roeck #endif 46877d8948SGuenter Roeck 47c5114a1cSClemens Ladisch /* CPUID function 0x80000001, ebx */ 48c5114a1cSClemens Ladisch #define CPUID_PKGTYPE_MASK 0xf0000000 49c5114a1cSClemens Ladisch #define CPUID_PKGTYPE_F 0x00000000 50c5114a1cSClemens Ladisch #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 51c5114a1cSClemens Ladisch 52c5114a1cSClemens Ladisch /* DRAM controller (PCI function 2) */ 53c5114a1cSClemens Ladisch #define REG_DCT0_CONFIG_HIGH 0x094 54c5114a1cSClemens Ladisch #define DDR3_MODE 0x00000100 55c5114a1cSClemens Ladisch 56c5114a1cSClemens Ladisch /* miscellaneous (PCI function 3) */ 573c57e89bSClemens Ladisch #define REG_HARDWARE_THERMAL_CONTROL 0x64 583c57e89bSClemens Ladisch #define HTC_ENABLE 0x00000001 593c57e89bSClemens Ladisch 603c57e89bSClemens Ladisch #define REG_REPORTED_TEMPERATURE 0xa4 613c57e89bSClemens Ladisch 623c57e89bSClemens Ladisch #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 633c57e89bSClemens Ladisch #define NB_CAP_HTC 0x00000400 643c57e89bSClemens Ladisch 65f89ce270SAravind Gopalakrishnan /* 6640626a1bSGuenter Roeck * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL 6740626a1bSGuenter Roeck * and REG_REPORTED_TEMPERATURE have been moved to 6840626a1bSGuenter Roeck * D0F0xBC_xD820_0C64 [Hardware Temperature Control] 6940626a1bSGuenter Roeck * D0F0xBC_xD820_0CA4 [Reported Temperature Control] 70f89ce270SAravind Gopalakrishnan */ 7140626a1bSGuenter Roeck #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 72f89ce270SAravind Gopalakrishnan #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 73f89ce270SAravind Gopalakrishnan 749af0a9aeSGuenter Roeck /* F17h M01h Access througn SMN */ 759af0a9aeSGuenter Roeck #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800 769af0a9aeSGuenter Roeck 7768546abfSGuenter Roeck struct k10temp_data { 7868546abfSGuenter Roeck struct pci_dev *pdev; 7940626a1bSGuenter Roeck void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); 8068546abfSGuenter Roeck void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); 811b50b776SGuenter Roeck int temp_offset; 821b597889SGuenter Roeck u32 temp_adjust_mask; 831b50b776SGuenter Roeck }; 841b50b776SGuenter Roeck 851b50b776SGuenter Roeck struct tctl_offset { 861b50b776SGuenter Roeck u8 model; 871b50b776SGuenter Roeck char const *id; 881b50b776SGuenter Roeck int offset; 891b50b776SGuenter Roeck }; 901b50b776SGuenter Roeck 911b50b776SGuenter Roeck static const struct tctl_offset tctl_offset_table[] = { 92ab5ee246SGuenter Roeck { 0x17, "AMD Ryzen 5 1600X", 20000 }, 931b50b776SGuenter Roeck { 0x17, "AMD Ryzen 7 1700X", 20000 }, 941b50b776SGuenter Roeck { 0x17, "AMD Ryzen 7 1800X", 20000 }, 951b597889SGuenter Roeck { 0x17, "AMD Ryzen 7 2700X", 10000 }, 961b50b776SGuenter Roeck { 0x17, "AMD Ryzen Threadripper 1950X", 27000 }, 971b50b776SGuenter Roeck { 0x17, "AMD Ryzen Threadripper 1920X", 27000 }, 986509614fSGuenter Roeck { 0x17, "AMD Ryzen Threadripper 1900X", 27000 }, 991b50b776SGuenter Roeck { 0x17, "AMD Ryzen Threadripper 1950", 10000 }, 1001b50b776SGuenter Roeck { 0x17, "AMD Ryzen Threadripper 1920", 10000 }, 1011b50b776SGuenter Roeck { 0x17, "AMD Ryzen Threadripper 1910", 10000 }, 10268546abfSGuenter Roeck }; 10368546abfSGuenter Roeck 10440626a1bSGuenter Roeck static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) 10540626a1bSGuenter Roeck { 10640626a1bSGuenter Roeck pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); 10740626a1bSGuenter Roeck } 10840626a1bSGuenter Roeck 10968546abfSGuenter Roeck static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) 11068546abfSGuenter Roeck { 11168546abfSGuenter Roeck pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); 11268546abfSGuenter Roeck } 11368546abfSGuenter Roeck 11468546abfSGuenter Roeck static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, 11568546abfSGuenter Roeck unsigned int base, int offset, u32 *val) 116f89ce270SAravind Gopalakrishnan { 117f89ce270SAravind Gopalakrishnan mutex_lock(&nb_smu_ind_mutex); 118f89ce270SAravind Gopalakrishnan pci_bus_write_config_dword(pdev->bus, devfn, 11968546abfSGuenter Roeck base, offset); 120f89ce270SAravind Gopalakrishnan pci_bus_read_config_dword(pdev->bus, devfn, 12168546abfSGuenter Roeck base + 4, val); 122f89ce270SAravind Gopalakrishnan mutex_unlock(&nb_smu_ind_mutex); 123f89ce270SAravind Gopalakrishnan } 124f89ce270SAravind Gopalakrishnan 12540626a1bSGuenter Roeck static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) 12640626a1bSGuenter Roeck { 12740626a1bSGuenter Roeck amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 12840626a1bSGuenter Roeck F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); 12940626a1bSGuenter Roeck } 13040626a1bSGuenter Roeck 13168546abfSGuenter Roeck static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) 13268546abfSGuenter Roeck { 13368546abfSGuenter Roeck amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 13468546abfSGuenter Roeck F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); 13568546abfSGuenter Roeck } 13668546abfSGuenter Roeck 1379af0a9aeSGuenter Roeck static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval) 1389af0a9aeSGuenter Roeck { 1399af0a9aeSGuenter Roeck amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0x60, 1409af0a9aeSGuenter Roeck F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval); 1419af0a9aeSGuenter Roeck } 1429af0a9aeSGuenter Roeck 1430c36d72eSJulia Lawall static ssize_t temp1_input_show(struct device *dev, 1443c57e89bSClemens Ladisch struct device_attribute *attr, char *buf) 1453c57e89bSClemens Ladisch { 14668546abfSGuenter Roeck struct k10temp_data *data = dev_get_drvdata(dev); 1473c57e89bSClemens Ladisch u32 regval; 14868546abfSGuenter Roeck unsigned int temp; 1493c57e89bSClemens Ladisch 15068546abfSGuenter Roeck data->read_tempreg(data->pdev, ®val); 15168546abfSGuenter Roeck temp = (regval >> 21) * 125; 1521b597889SGuenter Roeck if (regval & data->temp_adjust_mask) 1531b597889SGuenter Roeck temp -= 49000; 154aef17ca1SGuenter Roeck if (temp > data->temp_offset) 1551b50b776SGuenter Roeck temp -= data->temp_offset; 156aef17ca1SGuenter Roeck else 157aef17ca1SGuenter Roeck temp = 0; 15868546abfSGuenter Roeck 15968546abfSGuenter Roeck return sprintf(buf, "%u\n", temp); 1603c57e89bSClemens Ladisch } 1613c57e89bSClemens Ladisch 1620c36d72eSJulia Lawall static ssize_t temp1_max_show(struct device *dev, 1633c57e89bSClemens Ladisch struct device_attribute *attr, char *buf) 1643c57e89bSClemens Ladisch { 1653c57e89bSClemens Ladisch return sprintf(buf, "%d\n", 70 * 1000); 1663c57e89bSClemens Ladisch } 1673c57e89bSClemens Ladisch 1683c57e89bSClemens Ladisch static ssize_t show_temp_crit(struct device *dev, 1693c57e89bSClemens Ladisch struct device_attribute *devattr, char *buf) 1703c57e89bSClemens Ladisch { 1713c57e89bSClemens Ladisch struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); 17268546abfSGuenter Roeck struct k10temp_data *data = dev_get_drvdata(dev); 1733c57e89bSClemens Ladisch int show_hyst = attr->index; 1743c57e89bSClemens Ladisch u32 regval; 1753c57e89bSClemens Ladisch int value; 1763c57e89bSClemens Ladisch 17740626a1bSGuenter Roeck data->read_htcreg(data->pdev, ®val); 1783c57e89bSClemens Ladisch value = ((regval >> 16) & 0x7f) * 500 + 52000; 1793c57e89bSClemens Ladisch if (show_hyst) 1803c57e89bSClemens Ladisch value -= ((regval >> 24) & 0xf) * 500; 1813c57e89bSClemens Ladisch return sprintf(buf, "%d\n", value); 1823c57e89bSClemens Ladisch } 1833c57e89bSClemens Ladisch 1840c36d72eSJulia Lawall static DEVICE_ATTR_RO(temp1_input); 1850c36d72eSJulia Lawall static DEVICE_ATTR_RO(temp1_max); 1863c57e89bSClemens Ladisch static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0); 1873c57e89bSClemens Ladisch static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1); 1883e3e1022SGuenter Roeck 1893e3e1022SGuenter Roeck static umode_t k10temp_is_visible(struct kobject *kobj, 1903e3e1022SGuenter Roeck struct attribute *attr, int index) 1913e3e1022SGuenter Roeck { 1923e3e1022SGuenter Roeck struct device *dev = container_of(kobj, struct device, kobj); 19368546abfSGuenter Roeck struct k10temp_data *data = dev_get_drvdata(dev); 19468546abfSGuenter Roeck struct pci_dev *pdev = data->pdev; 1953e3e1022SGuenter Roeck 1963e3e1022SGuenter Roeck if (index >= 2) { 19740626a1bSGuenter Roeck u32 reg; 19840626a1bSGuenter Roeck 19940626a1bSGuenter Roeck if (!data->read_htcreg) 20040626a1bSGuenter Roeck return 0; 2013e3e1022SGuenter Roeck 2023e3e1022SGuenter Roeck pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES, 20340626a1bSGuenter Roeck ®); 20440626a1bSGuenter Roeck if (!(reg & NB_CAP_HTC)) 20540626a1bSGuenter Roeck return 0; 20640626a1bSGuenter Roeck 20740626a1bSGuenter Roeck data->read_htcreg(data->pdev, ®); 20840626a1bSGuenter Roeck if (!(reg & HTC_ENABLE)) 2093e3e1022SGuenter Roeck return 0; 2103e3e1022SGuenter Roeck } 2113e3e1022SGuenter Roeck return attr->mode; 2123e3e1022SGuenter Roeck } 2133e3e1022SGuenter Roeck 2143e3e1022SGuenter Roeck static struct attribute *k10temp_attrs[] = { 2153e3e1022SGuenter Roeck &dev_attr_temp1_input.attr, 2163e3e1022SGuenter Roeck &dev_attr_temp1_max.attr, 2173e3e1022SGuenter Roeck &sensor_dev_attr_temp1_crit.dev_attr.attr, 2183e3e1022SGuenter Roeck &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 2193e3e1022SGuenter Roeck NULL 2203e3e1022SGuenter Roeck }; 2213e3e1022SGuenter Roeck 2223e3e1022SGuenter Roeck static const struct attribute_group k10temp_group = { 2233e3e1022SGuenter Roeck .attrs = k10temp_attrs, 2243e3e1022SGuenter Roeck .is_visible = k10temp_is_visible, 2253e3e1022SGuenter Roeck }; 2263e3e1022SGuenter Roeck __ATTRIBUTE_GROUPS(k10temp); 2273c57e89bSClemens Ladisch 2286c931ae1SBill Pemberton static bool has_erratum_319(struct pci_dev *pdev) 2293c57e89bSClemens Ladisch { 230c5114a1cSClemens Ladisch u32 pkg_type, reg_dram_cfg; 231c5114a1cSClemens Ladisch 232c5114a1cSClemens Ladisch if (boot_cpu_data.x86 != 0x10) 233c5114a1cSClemens Ladisch return false; 234c5114a1cSClemens Ladisch 2353c57e89bSClemens Ladisch /* 236c5114a1cSClemens Ladisch * Erratum 319: The thermal sensor of Socket F/AM2+ processors 237c5114a1cSClemens Ladisch * may be unreliable. 2383c57e89bSClemens Ladisch */ 239c5114a1cSClemens Ladisch pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; 240c5114a1cSClemens Ladisch if (pkg_type == CPUID_PKGTYPE_F) 241c5114a1cSClemens Ladisch return true; 242c5114a1cSClemens Ladisch if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) 243c5114a1cSClemens Ladisch return false; 244c5114a1cSClemens Ladisch 245eefc2d9eSJean Delvare /* DDR3 memory implies socket AM3, which is good */ 246c5114a1cSClemens Ladisch pci_bus_read_config_dword(pdev->bus, 247c5114a1cSClemens Ladisch PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), 248c5114a1cSClemens Ladisch REG_DCT0_CONFIG_HIGH, ®_dram_cfg); 249eefc2d9eSJean Delvare if (reg_dram_cfg & DDR3_MODE) 250eefc2d9eSJean Delvare return false; 251eefc2d9eSJean Delvare 252eefc2d9eSJean Delvare /* 253eefc2d9eSJean Delvare * Unfortunately it is possible to run a socket AM3 CPU with DDR2 254eefc2d9eSJean Delvare * memory. We blacklist all the cores which do exist in socket AM2+ 255eefc2d9eSJean Delvare * format. It still isn't perfect, as RB-C2 cores exist in both AM2+ 256eefc2d9eSJean Delvare * and AM3 formats, but that's the best we can do. 257eefc2d9eSJean Delvare */ 258eefc2d9eSJean Delvare return boot_cpu_data.x86_model < 4 || 259b399151cSJia Zhang (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2); 2603c57e89bSClemens Ladisch } 2613c57e89bSClemens Ladisch 2626c931ae1SBill Pemberton static int k10temp_probe(struct pci_dev *pdev, 2633c57e89bSClemens Ladisch const struct pci_device_id *id) 2643c57e89bSClemens Ladisch { 265c5114a1cSClemens Ladisch int unreliable = has_erratum_319(pdev); 2663e3e1022SGuenter Roeck struct device *dev = &pdev->dev; 26768546abfSGuenter Roeck struct k10temp_data *data; 2683e3e1022SGuenter Roeck struct device *hwmon_dev; 2691b50b776SGuenter Roeck int i; 2703c57e89bSClemens Ladisch 2713e3e1022SGuenter Roeck if (unreliable) { 2723e3e1022SGuenter Roeck if (!force) { 2733e3e1022SGuenter Roeck dev_err(dev, 2743c57e89bSClemens Ladisch "unreliable CPU thermal sensor; monitoring disabled\n"); 2753e3e1022SGuenter Roeck return -ENODEV; 2763c57e89bSClemens Ladisch } 2773e3e1022SGuenter Roeck dev_warn(dev, 2783c57e89bSClemens Ladisch "unreliable CPU thermal sensor; check erratum 319\n"); 2793c57e89bSClemens Ladisch } 2803c57e89bSClemens Ladisch 28168546abfSGuenter Roeck data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 28268546abfSGuenter Roeck if (!data) 28368546abfSGuenter Roeck return -ENOMEM; 28468546abfSGuenter Roeck 28568546abfSGuenter Roeck data->pdev = pdev; 28668546abfSGuenter Roeck 28768546abfSGuenter Roeck if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 || 2881b597889SGuenter Roeck boot_cpu_data.x86_model == 0x70)) { 28940626a1bSGuenter Roeck data->read_htcreg = read_htcreg_nb_f15; 29068546abfSGuenter Roeck data->read_tempreg = read_tempreg_nb_f15; 2911b597889SGuenter Roeck } else if (boot_cpu_data.x86 == 0x17) { 2921b597889SGuenter Roeck data->temp_adjust_mask = 0x80000; 2939af0a9aeSGuenter Roeck data->read_tempreg = read_tempreg_nb_f17; 2941b597889SGuenter Roeck } else { 29540626a1bSGuenter Roeck data->read_htcreg = read_htcreg_pci; 29668546abfSGuenter Roeck data->read_tempreg = read_tempreg_pci; 2971b597889SGuenter Roeck } 29868546abfSGuenter Roeck 2991b50b776SGuenter Roeck for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) { 3001b50b776SGuenter Roeck const struct tctl_offset *entry = &tctl_offset_table[i]; 3011b50b776SGuenter Roeck 3021b50b776SGuenter Roeck if (boot_cpu_data.x86 == entry->model && 3031b50b776SGuenter Roeck strstr(boot_cpu_data.x86_model_id, entry->id)) { 3041b50b776SGuenter Roeck data->temp_offset = entry->offset; 3051b50b776SGuenter Roeck break; 3061b50b776SGuenter Roeck } 3071b50b776SGuenter Roeck } 3081b50b776SGuenter Roeck 30968546abfSGuenter Roeck hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data, 3103e3e1022SGuenter Roeck k10temp_groups); 3113e3e1022SGuenter Roeck return PTR_ERR_OR_ZERO(hwmon_dev); 3123c57e89bSClemens Ladisch } 3133c57e89bSClemens Ladisch 314cd9bb056SJingoo Han static const struct pci_device_id k10temp_id_table[] = { 3153c57e89bSClemens Ladisch { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, 3163c57e89bSClemens Ladisch { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, 317aa4790a6SClemens Ladisch { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, 3189e581311SAndre Przywara { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, 31924214449SBorislav Petkov { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, 320d303b1b5SPhil Pokorny { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, 321f89ce270SAravind Gopalakrishnan { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, 32230b146d1SWei Hu { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, 323ec015950SAravind Gopalakrishnan { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, 3249af0a9aeSGuenter Roeck { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 325877d8948SGuenter Roeck { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_RR_NB) }, 3263c57e89bSClemens Ladisch {} 3273c57e89bSClemens Ladisch }; 3283c57e89bSClemens Ladisch MODULE_DEVICE_TABLE(pci, k10temp_id_table); 3293c57e89bSClemens Ladisch 3303c57e89bSClemens Ladisch static struct pci_driver k10temp_driver = { 3313c57e89bSClemens Ladisch .name = "k10temp", 3323c57e89bSClemens Ladisch .id_table = k10temp_id_table, 3333c57e89bSClemens Ladisch .probe = k10temp_probe, 3343c57e89bSClemens Ladisch }; 3353c57e89bSClemens Ladisch 336f71f5a55SAxel Lin module_pci_driver(k10temp_driver); 337