1 /* 2 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors 3 * 4 * Copyright (c) 2010 Ericsson AB. 5 * 6 * Derived from lm77.c by Andras BALI <drewie@freemail.hu>. 7 * 8 * JC42.4 compliant temperature sensors are typically used on memory modules. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #include <linux/module.h> 26 #include <linux/init.h> 27 #include <linux/slab.h> 28 #include <linux/jiffies.h> 29 #include <linux/i2c.h> 30 #include <linux/hwmon.h> 31 #include <linux/err.h> 32 #include <linux/mutex.h> 33 #include <linux/of.h> 34 35 /* Addresses to scan */ 36 static const unsigned short normal_i2c[] = { 37 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END }; 38 39 /* JC42 registers. All registers are 16 bit. */ 40 #define JC42_REG_CAP 0x00 41 #define JC42_REG_CONFIG 0x01 42 #define JC42_REG_TEMP_UPPER 0x02 43 #define JC42_REG_TEMP_LOWER 0x03 44 #define JC42_REG_TEMP_CRITICAL 0x04 45 #define JC42_REG_TEMP 0x05 46 #define JC42_REG_MANID 0x06 47 #define JC42_REG_DEVICEID 0x07 48 49 /* Status bits in temperature register */ 50 #define JC42_ALARM_CRIT_BIT 15 51 #define JC42_ALARM_MAX_BIT 14 52 #define JC42_ALARM_MIN_BIT 13 53 54 /* Configuration register defines */ 55 #define JC42_CFG_CRIT_ONLY (1 << 2) 56 #define JC42_CFG_TCRIT_LOCK (1 << 6) 57 #define JC42_CFG_EVENT_LOCK (1 << 7) 58 #define JC42_CFG_SHUTDOWN (1 << 8) 59 #define JC42_CFG_HYST_SHIFT 9 60 #define JC42_CFG_HYST_MASK (0x03 << 9) 61 62 /* Capabilities */ 63 #define JC42_CAP_RANGE (1 << 2) 64 65 /* Manufacturer IDs */ 66 #define ADT_MANID 0x11d4 /* Analog Devices */ 67 #define ATMEL_MANID 0x001f /* Atmel */ 68 #define ATMEL_MANID2 0x1114 /* Atmel */ 69 #define MAX_MANID 0x004d /* Maxim */ 70 #define IDT_MANID 0x00b3 /* IDT */ 71 #define MCP_MANID 0x0054 /* Microchip */ 72 #define NXP_MANID 0x1131 /* NXP Semiconductors */ 73 #define ONS_MANID 0x1b09 /* ON Semiconductor */ 74 #define STM_MANID 0x104a /* ST Microelectronics */ 75 #define GT_MANID 0x1c68 /* Giantec */ 76 #define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */ 77 78 /* Supported chips */ 79 80 /* Analog Devices */ 81 #define ADT7408_DEVID 0x0801 82 #define ADT7408_DEVID_MASK 0xffff 83 84 /* Atmel */ 85 #define AT30TS00_DEVID 0x8201 86 #define AT30TS00_DEVID_MASK 0xffff 87 88 #define AT30TSE004_DEVID 0x2200 89 #define AT30TSE004_DEVID_MASK 0xffff 90 91 /* Giantec */ 92 #define GT30TS00_DEVID 0x2200 93 #define GT30TS00_DEVID_MASK 0xff00 94 95 #define GT34TS02_DEVID 0x3300 96 #define GT34TS02_DEVID_MASK 0xff00 97 98 /* IDT */ 99 #define TSE2004_DEVID 0x2200 100 #define TSE2004_DEVID_MASK 0xff00 101 102 #define TS3000_DEVID 0x2900 /* Also matches TSE2002 */ 103 #define TS3000_DEVID_MASK 0xff00 104 105 #define TS3001_DEVID 0x3000 106 #define TS3001_DEVID_MASK 0xff00 107 108 /* Maxim */ 109 #define MAX6604_DEVID 0x3e00 110 #define MAX6604_DEVID_MASK 0xffff 111 112 /* Microchip */ 113 #define MCP9804_DEVID 0x0200 114 #define MCP9804_DEVID_MASK 0xfffc 115 116 #define MCP9808_DEVID 0x0400 117 #define MCP9808_DEVID_MASK 0xfffc 118 119 #define MCP98242_DEVID 0x2000 120 #define MCP98242_DEVID_MASK 0xfffc 121 122 #define MCP98243_DEVID 0x2100 123 #define MCP98243_DEVID_MASK 0xfffc 124 125 #define MCP98244_DEVID 0x2200 126 #define MCP98244_DEVID_MASK 0xfffc 127 128 #define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */ 129 #define MCP9843_DEVID_MASK 0xfffe 130 131 /* NXP */ 132 #define SE97_DEVID 0xa200 133 #define SE97_DEVID_MASK 0xfffc 134 135 #define SE98_DEVID 0xa100 136 #define SE98_DEVID_MASK 0xfffc 137 138 /* ON Semiconductor */ 139 #define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */ 140 #define CAT6095_DEVID_MASK 0xffe0 141 142 #define CAT34TS04_DEVID 0x2200 143 #define CAT34TS04_DEVID_MASK 0xfff0 144 145 /* ST Microelectronics */ 146 #define STTS424_DEVID 0x0101 147 #define STTS424_DEVID_MASK 0xffff 148 149 #define STTS424E_DEVID 0x0000 150 #define STTS424E_DEVID_MASK 0xfffe 151 152 #define STTS2002_DEVID 0x0300 153 #define STTS2002_DEVID_MASK 0xffff 154 155 #define STTS2004_DEVID 0x2201 156 #define STTS2004_DEVID_MASK 0xffff 157 158 #define STTS3000_DEVID 0x0200 159 #define STTS3000_DEVID_MASK 0xffff 160 161 static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 }; 162 163 struct jc42_chips { 164 u16 manid; 165 u16 devid; 166 u16 devid_mask; 167 }; 168 169 static struct jc42_chips jc42_chips[] = { 170 { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK }, 171 { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK }, 172 { ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK }, 173 { GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK }, 174 { GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK }, 175 { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK }, 176 { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK }, 177 { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK }, 178 { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK }, 179 { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK }, 180 { MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK }, 181 { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK }, 182 { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK }, 183 { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK }, 184 { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK }, 185 { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK }, 186 { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK }, 187 { ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK }, 188 { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK }, 189 { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK }, 190 { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK }, 191 { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK }, 192 { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK }, 193 { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK }, 194 }; 195 196 enum temp_index { 197 t_input = 0, 198 t_crit, 199 t_min, 200 t_max, 201 t_num_temp 202 }; 203 204 static const u8 temp_regs[t_num_temp] = { 205 [t_input] = JC42_REG_TEMP, 206 [t_crit] = JC42_REG_TEMP_CRITICAL, 207 [t_min] = JC42_REG_TEMP_LOWER, 208 [t_max] = JC42_REG_TEMP_UPPER, 209 }; 210 211 /* Each client has this additional data */ 212 struct jc42_data { 213 struct i2c_client *client; 214 struct mutex update_lock; /* protect register access */ 215 bool extended; /* true if extended range supported */ 216 bool valid; 217 unsigned long last_updated; /* In jiffies */ 218 u16 orig_config; /* original configuration */ 219 u16 config; /* current configuration */ 220 u16 temp[t_num_temp];/* Temperatures */ 221 }; 222 223 #define JC42_TEMP_MIN_EXTENDED (-40000) 224 #define JC42_TEMP_MIN 0 225 #define JC42_TEMP_MAX 125000 226 227 static u16 jc42_temp_to_reg(long temp, bool extended) 228 { 229 int ntemp = clamp_val(temp, 230 extended ? JC42_TEMP_MIN_EXTENDED : 231 JC42_TEMP_MIN, JC42_TEMP_MAX); 232 233 /* convert from 0.001 to 0.0625 resolution */ 234 return (ntemp * 2 / 125) & 0x1fff; 235 } 236 237 static int jc42_temp_from_reg(s16 reg) 238 { 239 reg = sign_extend32(reg, 12); 240 241 /* convert from 0.0625 to 0.001 resolution */ 242 return reg * 125 / 2; 243 } 244 245 static struct jc42_data *jc42_update_device(struct device *dev) 246 { 247 struct jc42_data *data = dev_get_drvdata(dev); 248 struct i2c_client *client = data->client; 249 struct jc42_data *ret = data; 250 int i, val; 251 252 mutex_lock(&data->update_lock); 253 254 if (time_after(jiffies, data->last_updated + HZ) || !data->valid) { 255 for (i = 0; i < t_num_temp; i++) { 256 val = i2c_smbus_read_word_swapped(client, temp_regs[i]); 257 if (val < 0) { 258 ret = ERR_PTR(val); 259 goto abort; 260 } 261 data->temp[i] = val; 262 } 263 data->last_updated = jiffies; 264 data->valid = true; 265 } 266 abort: 267 mutex_unlock(&data->update_lock); 268 return ret; 269 } 270 271 static int jc42_read(struct device *dev, enum hwmon_sensor_types type, 272 u32 attr, int channel, long *val) 273 { 274 struct jc42_data *data = jc42_update_device(dev); 275 int temp, hyst; 276 277 if (IS_ERR(data)) 278 return PTR_ERR(data); 279 280 switch (attr) { 281 case hwmon_temp_input: 282 *val = jc42_temp_from_reg(data->temp[t_input]); 283 return 0; 284 case hwmon_temp_min: 285 *val = jc42_temp_from_reg(data->temp[t_min]); 286 return 0; 287 case hwmon_temp_max: 288 *val = jc42_temp_from_reg(data->temp[t_max]); 289 return 0; 290 case hwmon_temp_crit: 291 *val = jc42_temp_from_reg(data->temp[t_crit]); 292 return 0; 293 case hwmon_temp_max_hyst: 294 temp = jc42_temp_from_reg(data->temp[t_max]); 295 hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK) 296 >> JC42_CFG_HYST_SHIFT]; 297 *val = temp - hyst; 298 return 0; 299 case hwmon_temp_crit_hyst: 300 temp = jc42_temp_from_reg(data->temp[t_crit]); 301 hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK) 302 >> JC42_CFG_HYST_SHIFT]; 303 *val = temp - hyst; 304 return 0; 305 case hwmon_temp_min_alarm: 306 *val = (data->temp[t_input] >> JC42_ALARM_MIN_BIT) & 1; 307 return 0; 308 case hwmon_temp_max_alarm: 309 *val = (data->temp[t_input] >> JC42_ALARM_MAX_BIT) & 1; 310 return 0; 311 case hwmon_temp_crit_alarm: 312 *val = (data->temp[t_input] >> JC42_ALARM_CRIT_BIT) & 1; 313 return 0; 314 default: 315 return -EOPNOTSUPP; 316 } 317 } 318 319 static int jc42_write(struct device *dev, enum hwmon_sensor_types type, 320 u32 attr, int channel, long val) 321 { 322 struct jc42_data *data = dev_get_drvdata(dev); 323 struct i2c_client *client = data->client; 324 int diff, hyst; 325 int ret; 326 327 mutex_lock(&data->update_lock); 328 329 switch (attr) { 330 case hwmon_temp_min: 331 data->temp[t_min] = jc42_temp_to_reg(val, data->extended); 332 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_min], 333 data->temp[t_min]); 334 break; 335 case hwmon_temp_max: 336 data->temp[t_max] = jc42_temp_to_reg(val, data->extended); 337 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_max], 338 data->temp[t_max]); 339 break; 340 case hwmon_temp_crit: 341 data->temp[t_crit] = jc42_temp_to_reg(val, data->extended); 342 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_crit], 343 data->temp[t_crit]); 344 break; 345 case hwmon_temp_crit_hyst: 346 /* 347 * JC42.4 compliant chips only support four hysteresis values. 348 * Pick best choice and go from there. 349 */ 350 val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED 351 : JC42_TEMP_MIN) - 6000, 352 JC42_TEMP_MAX); 353 diff = jc42_temp_from_reg(data->temp[t_crit]) - val; 354 hyst = 0; 355 if (diff > 0) { 356 if (diff < 2250) 357 hyst = 1; /* 1.5 degrees C */ 358 else if (diff < 4500) 359 hyst = 2; /* 3.0 degrees C */ 360 else 361 hyst = 3; /* 6.0 degrees C */ 362 } 363 data->config = (data->config & ~JC42_CFG_HYST_MASK) | 364 (hyst << JC42_CFG_HYST_SHIFT); 365 ret = i2c_smbus_write_word_swapped(data->client, 366 JC42_REG_CONFIG, 367 data->config); 368 break; 369 default: 370 ret = -EOPNOTSUPP; 371 break; 372 } 373 374 mutex_unlock(&data->update_lock); 375 376 return ret; 377 } 378 379 static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type, 380 u32 attr, int channel) 381 { 382 const struct jc42_data *data = _data; 383 unsigned int config = data->config; 384 umode_t mode = S_IRUGO; 385 386 switch (attr) { 387 case hwmon_temp_min: 388 case hwmon_temp_max: 389 if (!(config & JC42_CFG_EVENT_LOCK)) 390 mode |= S_IWUSR; 391 break; 392 case hwmon_temp_crit: 393 if (!(config & JC42_CFG_TCRIT_LOCK)) 394 mode |= S_IWUSR; 395 break; 396 case hwmon_temp_crit_hyst: 397 if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK))) 398 mode |= S_IWUSR; 399 break; 400 case hwmon_temp_input: 401 case hwmon_temp_max_hyst: 402 case hwmon_temp_min_alarm: 403 case hwmon_temp_max_alarm: 404 case hwmon_temp_crit_alarm: 405 break; 406 default: 407 mode = 0; 408 break; 409 } 410 return mode; 411 } 412 413 /* Return 0 if detection is successful, -ENODEV otherwise */ 414 static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info) 415 { 416 struct i2c_adapter *adapter = client->adapter; 417 int i, config, cap, manid, devid; 418 419 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | 420 I2C_FUNC_SMBUS_WORD_DATA)) 421 return -ENODEV; 422 423 cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP); 424 config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG); 425 manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID); 426 devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID); 427 428 if (cap < 0 || config < 0 || manid < 0 || devid < 0) 429 return -ENODEV; 430 431 if ((cap & 0xff00) || (config & 0xf800)) 432 return -ENODEV; 433 434 for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) { 435 struct jc42_chips *chip = &jc42_chips[i]; 436 if (manid == chip->manid && 437 (devid & chip->devid_mask) == chip->devid) { 438 strlcpy(info->type, "jc42", I2C_NAME_SIZE); 439 return 0; 440 } 441 } 442 return -ENODEV; 443 } 444 445 static const u32 jc42_temp_config[] = { 446 HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | HWMON_T_CRIT | 447 HWMON_T_MAX_HYST | HWMON_T_CRIT_HYST | 448 HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM, 449 0 450 }; 451 452 static const struct hwmon_channel_info jc42_temp = { 453 .type = hwmon_temp, 454 .config = jc42_temp_config, 455 }; 456 457 static const struct hwmon_channel_info *jc42_info[] = { 458 &jc42_temp, 459 NULL 460 }; 461 462 static const struct hwmon_ops jc42_hwmon_ops = { 463 .is_visible = jc42_is_visible, 464 .read = jc42_read, 465 .write = jc42_write, 466 }; 467 468 static const struct hwmon_chip_info jc42_chip_info = { 469 .ops = &jc42_hwmon_ops, 470 .info = jc42_info, 471 }; 472 473 static int jc42_probe(struct i2c_client *client, const struct i2c_device_id *id) 474 { 475 struct device *dev = &client->dev; 476 struct device *hwmon_dev; 477 struct jc42_data *data; 478 int config, cap; 479 480 data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL); 481 if (!data) 482 return -ENOMEM; 483 484 data->client = client; 485 i2c_set_clientdata(client, data); 486 mutex_init(&data->update_lock); 487 488 cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP); 489 if (cap < 0) 490 return cap; 491 492 data->extended = !!(cap & JC42_CAP_RANGE); 493 494 config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG); 495 if (config < 0) 496 return config; 497 498 data->orig_config = config; 499 if (config & JC42_CFG_SHUTDOWN) { 500 config &= ~JC42_CFG_SHUTDOWN; 501 i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config); 502 } 503 data->config = config; 504 505 hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, 506 data, &jc42_chip_info, 507 NULL); 508 return PTR_ERR_OR_ZERO(hwmon_dev); 509 } 510 511 static int jc42_remove(struct i2c_client *client) 512 { 513 struct jc42_data *data = i2c_get_clientdata(client); 514 515 /* Restore original configuration except hysteresis */ 516 if ((data->config & ~JC42_CFG_HYST_MASK) != 517 (data->orig_config & ~JC42_CFG_HYST_MASK)) { 518 int config; 519 520 config = (data->orig_config & ~JC42_CFG_HYST_MASK) 521 | (data->config & JC42_CFG_HYST_MASK); 522 i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config); 523 } 524 return 0; 525 } 526 527 #ifdef CONFIG_PM 528 529 static int jc42_suspend(struct device *dev) 530 { 531 struct jc42_data *data = dev_get_drvdata(dev); 532 533 data->config |= JC42_CFG_SHUTDOWN; 534 i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG, 535 data->config); 536 return 0; 537 } 538 539 static int jc42_resume(struct device *dev) 540 { 541 struct jc42_data *data = dev_get_drvdata(dev); 542 543 data->config &= ~JC42_CFG_SHUTDOWN; 544 i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG, 545 data->config); 546 return 0; 547 } 548 549 static const struct dev_pm_ops jc42_dev_pm_ops = { 550 .suspend = jc42_suspend, 551 .resume = jc42_resume, 552 }; 553 554 #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops) 555 #else 556 #define JC42_DEV_PM_OPS NULL 557 #endif /* CONFIG_PM */ 558 559 static const struct i2c_device_id jc42_id[] = { 560 { "jc42", 0 }, 561 { } 562 }; 563 MODULE_DEVICE_TABLE(i2c, jc42_id); 564 565 #ifdef CONFIG_OF 566 static const struct of_device_id jc42_of_ids[] = { 567 { .compatible = "jedec,jc-42.4-temp", }, 568 { } 569 }; 570 MODULE_DEVICE_TABLE(of, jc42_of_ids); 571 #endif 572 573 static struct i2c_driver jc42_driver = { 574 .class = I2C_CLASS_SPD | I2C_CLASS_HWMON, 575 .driver = { 576 .name = "jc42", 577 .pm = JC42_DEV_PM_OPS, 578 .of_match_table = of_match_ptr(jc42_of_ids), 579 }, 580 .probe = jc42_probe, 581 .remove = jc42_remove, 582 .id_table = jc42_id, 583 .detect = jc42_detect, 584 .address_list = normal_i2c, 585 }; 586 587 module_i2c_driver(jc42_driver); 588 589 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>"); 590 MODULE_DESCRIPTION("JC42 driver"); 591 MODULE_LICENSE("GPL"); 592