1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * it87.c - Part of lm_sensors, Linux kernel modules for hardware 4 * monitoring. 5 * 6 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a 7 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in 8 * addition to an Environment Controller (Enhanced Hardware Monitor and 9 * Fan Controller) 10 * 11 * This driver supports only the Environment Controller in the IT8705F and 12 * similar parts. The other devices are supported by different drivers. 13 * 14 * Supports: IT8603E Super I/O chip w/LPC interface 15 * IT8620E Super I/O chip w/LPC interface 16 * IT8622E Super I/O chip w/LPC interface 17 * IT8623E Super I/O chip w/LPC interface 18 * IT8628E Super I/O chip w/LPC interface 19 * IT8705F Super I/O chip w/LPC interface 20 * IT8712F Super I/O chip w/LPC interface 21 * IT8716F Super I/O chip w/LPC interface 22 * IT8718F Super I/O chip w/LPC interface 23 * IT8720F Super I/O chip w/LPC interface 24 * IT8721F Super I/O chip w/LPC interface 25 * IT8726F Super I/O chip w/LPC interface 26 * IT8728F Super I/O chip w/LPC interface 27 * IT8732F Super I/O chip w/LPC interface 28 * IT8758E Super I/O chip w/LPC interface 29 * IT8771E Super I/O chip w/LPC interface 30 * IT8772E Super I/O chip w/LPC interface 31 * IT8781F Super I/O chip w/LPC interface 32 * IT8782F Super I/O chip w/LPC interface 33 * IT8783E/F Super I/O chip w/LPC interface 34 * IT8786E Super I/O chip w/LPC interface 35 * IT8790E Super I/O chip w/LPC interface 36 * IT8792E Super I/O chip w/LPC interface 37 * IT87952E Super I/O chip w/LPC interface 38 * Sis950 A clone of the IT8705F 39 * 40 * Copyright (C) 2001 Chris Gauthron 41 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de> 42 */ 43 44 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 45 46 #include <linux/bitops.h> 47 #include <linux/module.h> 48 #include <linux/init.h> 49 #include <linux/slab.h> 50 #include <linux/jiffies.h> 51 #include <linux/platform_device.h> 52 #include <linux/hwmon.h> 53 #include <linux/hwmon-sysfs.h> 54 #include <linux/hwmon-vid.h> 55 #include <linux/err.h> 56 #include <linux/mutex.h> 57 #include <linux/sysfs.h> 58 #include <linux/string.h> 59 #include <linux/dmi.h> 60 #include <linux/acpi.h> 61 #include <linux/io.h> 62 63 #define DRVNAME "it87" 64 65 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732, 66 it8771, it8772, it8781, it8782, it8783, it8786, it8790, 67 it8792, it8603, it8620, it8622, it8628, it87952 }; 68 69 static struct platform_device *it87_pdev[2]; 70 71 #define REG_2E 0x2e /* The register to read/write */ 72 #define REG_4E 0x4e /* Secondary register to read/write */ 73 74 #define DEV 0x07 /* Register: Logical device select */ 75 #define PME 0x04 /* The device with the fan registers in it */ 76 77 /* The device with the IT8718F/IT8720F VID value in it */ 78 #define GPIO 0x07 79 80 #define DEVID 0x20 /* Register: Device ID */ 81 #define DEVREV 0x22 /* Register: Device Revision */ 82 83 static inline void __superio_enter(int ioreg) 84 { 85 outb(0x87, ioreg); 86 outb(0x01, ioreg); 87 outb(0x55, ioreg); 88 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg); 89 } 90 91 static inline int superio_inb(int ioreg, int reg) 92 { 93 outb(reg, ioreg); 94 return inb(ioreg + 1); 95 } 96 97 static inline void superio_outb(int ioreg, int reg, int val) 98 { 99 outb(reg, ioreg); 100 outb(val, ioreg + 1); 101 } 102 103 static int superio_inw(int ioreg, int reg) 104 { 105 int val; 106 107 outb(reg++, ioreg); 108 val = inb(ioreg + 1) << 8; 109 outb(reg, ioreg); 110 val |= inb(ioreg + 1); 111 return val; 112 } 113 114 static inline void superio_select(int ioreg, int ldn) 115 { 116 outb(DEV, ioreg); 117 outb(ldn, ioreg + 1); 118 } 119 120 static inline int superio_enter(int ioreg) 121 { 122 /* 123 * Try to reserve ioreg and ioreg + 1 for exclusive access. 124 */ 125 if (!request_muxed_region(ioreg, 2, DRVNAME)) 126 return -EBUSY; 127 128 __superio_enter(ioreg); 129 return 0; 130 } 131 132 static inline void superio_exit(int ioreg, bool noexit) 133 { 134 if (!noexit) { 135 outb(0x02, ioreg); 136 outb(0x02, ioreg + 1); 137 } 138 release_region(ioreg, 2); 139 } 140 141 /* Logical device 4 registers */ 142 #define IT8712F_DEVID 0x8712 143 #define IT8705F_DEVID 0x8705 144 #define IT8716F_DEVID 0x8716 145 #define IT8718F_DEVID 0x8718 146 #define IT8720F_DEVID 0x8720 147 #define IT8721F_DEVID 0x8721 148 #define IT8726F_DEVID 0x8726 149 #define IT8728F_DEVID 0x8728 150 #define IT8732F_DEVID 0x8732 151 #define IT8792E_DEVID 0x8733 152 #define IT8771E_DEVID 0x8771 153 #define IT8772E_DEVID 0x8772 154 #define IT8781F_DEVID 0x8781 155 #define IT8782F_DEVID 0x8782 156 #define IT8783E_DEVID 0x8783 157 #define IT8786E_DEVID 0x8786 158 #define IT8790E_DEVID 0x8790 159 #define IT8603E_DEVID 0x8603 160 #define IT8620E_DEVID 0x8620 161 #define IT8622E_DEVID 0x8622 162 #define IT8623E_DEVID 0x8623 163 #define IT8628E_DEVID 0x8628 164 #define IT87952E_DEVID 0x8695 165 166 /* Logical device 4 (Environmental Monitor) registers */ 167 #define IT87_ACT_REG 0x30 168 #define IT87_BASE_REG 0x60 169 #define IT87_SPECIAL_CFG_REG 0xf3 /* special configuration register */ 170 171 /* Logical device 7 registers (IT8712F and later) */ 172 #define IT87_SIO_GPIO1_REG 0x25 173 #define IT87_SIO_GPIO2_REG 0x26 174 #define IT87_SIO_GPIO3_REG 0x27 175 #define IT87_SIO_GPIO4_REG 0x28 176 #define IT87_SIO_GPIO5_REG 0x29 177 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */ 178 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */ 179 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */ 180 #define IT87_SIO_VID_REG 0xfc /* VID value */ 181 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */ 182 183 /* Force chip IDs to specified values. Should only be used for testing */ 184 static unsigned short force_id[2]; 185 static unsigned int force_id_cnt; 186 187 /* ACPI resource conflicts are ignored if this parameter is set to 1 */ 188 static bool ignore_resource_conflict; 189 190 /* Update battery voltage after every reading if true */ 191 static bool update_vbat; 192 193 /* Not all BIOSes properly configure the PWM registers */ 194 static bool fix_pwm_polarity; 195 196 /* Many IT87 constants specified below */ 197 198 /* Length of ISA address segment */ 199 #define IT87_EXTENT 8 200 201 /* Length of ISA address segment for Environmental Controller */ 202 #define IT87_EC_EXTENT 2 203 204 /* Offset of EC registers from ISA base address */ 205 #define IT87_EC_OFFSET 5 206 207 /* Where are the ISA address/data registers relative to the EC base address */ 208 #define IT87_ADDR_REG_OFFSET 0 209 #define IT87_DATA_REG_OFFSET 1 210 211 /*----- The IT87 registers -----*/ 212 213 #define IT87_REG_CONFIG 0x00 214 215 #define IT87_REG_ALARM1 0x01 216 #define IT87_REG_ALARM2 0x02 217 #define IT87_REG_ALARM3 0x03 218 219 /* 220 * The IT8718F and IT8720F have the VID value in a different register, in 221 * Super-I/O configuration space. 222 */ 223 #define IT87_REG_VID 0x0a 224 /* 225 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b 226 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer 227 * mode. 228 */ 229 #define IT87_REG_FAN_DIV 0x0b 230 #define IT87_REG_FAN_16BIT 0x0c 231 232 /* 233 * Monitors: 234 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12) 235 * - up to 6 temp (1 to 6) 236 * - up to 6 fan (1 to 6) 237 */ 238 239 static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c }; 240 static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e }; 241 static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d }; 242 static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f }; 243 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 }; 244 245 #define IT87_REG_FAN_MAIN_CTRL 0x13 246 #define IT87_REG_FAN_CTL 0x14 247 static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf }; 248 static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab }; 249 250 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 251 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e }; 252 253 #define IT87_REG_TEMP(nr) (0x29 + (nr)) 254 255 #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2) 256 #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2) 257 #define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2) 258 #define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2) 259 260 #define IT87_REG_VIN_ENABLE 0x50 261 #define IT87_REG_TEMP_ENABLE 0x51 262 #define IT87_REG_TEMP_EXTRA 0x55 263 #define IT87_REG_BEEP_ENABLE 0x5c 264 265 #define IT87_REG_CHIPID 0x58 266 267 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 }; 268 269 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i)) 270 #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i)) 271 272 #define IT87_REG_TEMP456_ENABLE 0x77 273 274 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN) 275 #define NUM_VIN_LIMIT 8 276 #define NUM_TEMP 6 277 #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET) 278 #define NUM_TEMP_LIMIT 3 279 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN) 280 #define NUM_FAN_DIV 3 281 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM) 282 #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM) 283 284 struct it87_devices { 285 const char *name; 286 const char * const model; 287 u32 features; 288 u8 peci_mask; 289 u8 old_peci_mask; 290 u8 smbus_bitmap; /* SMBus enable bits in extra config register */ 291 u8 ec_special_config; 292 }; 293 294 #define FEAT_12MV_ADC BIT(0) 295 #define FEAT_NEWER_AUTOPWM BIT(1) 296 #define FEAT_OLD_AUTOPWM BIT(2) 297 #define FEAT_16BIT_FANS BIT(3) 298 #define FEAT_TEMP_OFFSET BIT(4) 299 #define FEAT_TEMP_PECI BIT(5) 300 #define FEAT_TEMP_OLD_PECI BIT(6) 301 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */ 302 #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */ 303 #define FEAT_VID BIT(9) /* Set if chip supports VID */ 304 #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */ 305 #define FEAT_SIX_FANS BIT(11) /* Supports six fans */ 306 #define FEAT_10_9MV_ADC BIT(12) 307 #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */ 308 #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */ 309 #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */ 310 #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */ 311 #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */ 312 #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */ 313 /* 314 * Disabling configuration mode on some chips can result in system 315 * hang-ups and access failures to the Super-IO chip at the 316 * second SIO address. Never exit configuration mode on these 317 * chips to avoid the problem. 318 */ 319 #define FEAT_CONF_NOEXIT BIT(19) /* Chip should not exit conf mode */ 320 #define FEAT_FOUR_FANS BIT(20) /* Supports four fans */ 321 #define FEAT_FOUR_PWM BIT(21) /* Supports four fan controls */ 322 #define FEAT_FOUR_TEMP BIT(22) 323 #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */ 324 325 static const struct it87_devices it87_devices[] = { 326 [it87] = { 327 .name = "it87", 328 .model = "IT87F", 329 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF, 330 /* may need to overwrite */ 331 }, 332 [it8712] = { 333 .name = "it8712", 334 .model = "IT8712F", 335 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF, 336 /* may need to overwrite */ 337 }, 338 [it8716] = { 339 .name = "it8716", 340 .model = "IT8716F", 341 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 342 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2 343 | FEAT_FANCTL_ONOFF, 344 }, 345 [it8718] = { 346 .name = "it8718", 347 .model = "IT8718F", 348 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 349 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS 350 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 351 .old_peci_mask = 0x4, 352 }, 353 [it8720] = { 354 .name = "it8720", 355 .model = "IT8720F", 356 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 357 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS 358 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 359 .old_peci_mask = 0x4, 360 }, 361 [it8721] = { 362 .name = "it8721", 363 .model = "IT8721F", 364 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 365 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 366 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL 367 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 368 .peci_mask = 0x05, 369 .old_peci_mask = 0x02, /* Actually reports PCH */ 370 }, 371 [it8728] = { 372 .name = "it8728", 373 .model = "IT8728F", 374 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 375 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS 376 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 377 | FEAT_FANCTL_ONOFF, 378 .peci_mask = 0x07, 379 }, 380 [it8732] = { 381 .name = "it8732", 382 .model = "IT8732F", 383 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 384 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 385 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS 386 | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF, 387 .peci_mask = 0x07, 388 .old_peci_mask = 0x02, /* Actually reports PCH */ 389 }, 390 [it8771] = { 391 .name = "it8771", 392 .model = "IT8771E", 393 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 394 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 395 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 396 /* PECI: guesswork */ 397 /* 12mV ADC (OHM) */ 398 /* 16 bit fans (OHM) */ 399 /* three fans, always 16 bit (guesswork) */ 400 .peci_mask = 0x07, 401 }, 402 [it8772] = { 403 .name = "it8772", 404 .model = "IT8772E", 405 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 406 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 407 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 408 /* PECI (coreboot) */ 409 /* 12mV ADC (HWSensors4, OHM) */ 410 /* 16 bit fans (HWSensors4, OHM) */ 411 /* three fans, always 16 bit (datasheet) */ 412 .peci_mask = 0x07, 413 }, 414 [it8781] = { 415 .name = "it8781", 416 .model = "IT8781F", 417 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 418 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 419 | FEAT_FANCTL_ONOFF, 420 .old_peci_mask = 0x4, 421 }, 422 [it8782] = { 423 .name = "it8782", 424 .model = "IT8782F", 425 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 426 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 427 | FEAT_FANCTL_ONOFF, 428 .old_peci_mask = 0x4, 429 }, 430 [it8783] = { 431 .name = "it8783", 432 .model = "IT8783E/F", 433 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 434 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 435 | FEAT_FANCTL_ONOFF, 436 .old_peci_mask = 0x4, 437 }, 438 [it8786] = { 439 .name = "it8786", 440 .model = "IT8786E", 441 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 442 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 443 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 444 .peci_mask = 0x07, 445 }, 446 [it8790] = { 447 .name = "it8790", 448 .model = "IT8790E", 449 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 450 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 451 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF | FEAT_CONF_NOEXIT, 452 .peci_mask = 0x07, 453 }, 454 [it8792] = { 455 .name = "it8792", 456 .model = "IT8792E/IT8795E", 457 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 458 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 459 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FANCTL_ONOFF 460 | FEAT_CONF_NOEXIT, 461 .peci_mask = 0x07, 462 .old_peci_mask = 0x02, /* Actually reports PCH */ 463 }, 464 [it8603] = { 465 .name = "it8603", 466 .model = "IT8603E", 467 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 468 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 469 | FEAT_AVCC3 | FEAT_PWM_FREQ2, 470 .peci_mask = 0x07, 471 }, 472 [it8620] = { 473 .name = "it8620", 474 .model = "IT8620E", 475 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 476 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS 477 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 478 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_FANCTL_ONOFF, 479 .peci_mask = 0x07, 480 }, 481 [it8622] = { 482 .name = "it8622", 483 .model = "IT8622E", 484 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 485 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS 486 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 487 | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_FOUR_TEMP, 488 .peci_mask = 0x07, 489 .smbus_bitmap = BIT(1) | BIT(2), 490 }, 491 [it8628] = { 492 .name = "it8628", 493 .model = "IT8628E", 494 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 495 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS 496 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 497 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_FANCTL_ONOFF, 498 .peci_mask = 0x07, 499 }, 500 [it87952] = { 501 .name = "it87952", 502 .model = "IT87952E", 503 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 504 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 505 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FANCTL_ONOFF 506 | FEAT_CONF_NOEXIT, 507 .peci_mask = 0x07, 508 .old_peci_mask = 0x02, /* Actually reports PCH */ 509 }, 510 }; 511 512 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS) 513 #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC) 514 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC) 515 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM) 516 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM) 517 #define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET) 518 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \ 519 ((data)->peci_mask & BIT(nr))) 520 #define has_temp_old_peci(data, nr) \ 521 (((data)->features & FEAT_TEMP_OLD_PECI) && \ 522 ((data)->old_peci_mask & BIT(nr))) 523 #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG) 524 #define has_four_fans(data) ((data)->features & (FEAT_FOUR_FANS | \ 525 FEAT_FIVE_FANS | \ 526 FEAT_SIX_FANS)) 527 #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \ 528 FEAT_SIX_FANS)) 529 #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS) 530 #define has_vid(data) ((data)->features & FEAT_VID) 531 #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL) 532 #define has_avcc3(data) ((data)->features & FEAT_AVCC3) 533 #define has_four_pwm(data) ((data)->features & (FEAT_FOUR_PWM | \ 534 FEAT_FIVE_PWM | \ 535 FEAT_SIX_PWM)) 536 #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM | \ 537 FEAT_SIX_PWM)) 538 #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM) 539 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2) 540 #define has_four_temp(data) ((data)->features & FEAT_FOUR_TEMP) 541 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP) 542 #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V) 543 #define has_conf_noexit(data) ((data)->features & FEAT_CONF_NOEXIT) 544 #define has_scaling(data) ((data)->features & (FEAT_12MV_ADC | \ 545 FEAT_10_9MV_ADC)) 546 #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF) 547 548 struct it87_sio_data { 549 int sioaddr; 550 enum chips type; 551 /* Values read from Super-I/O config space */ 552 u8 revision; 553 u8 vid_value; 554 u8 beep_pin; 555 u8 internal; /* Internal sensors can be labeled */ 556 bool need_in7_reroute; 557 /* Features skipped based on config or DMI */ 558 u16 skip_in; 559 u8 skip_vid; 560 u8 skip_fan; 561 u8 skip_pwm; 562 u8 skip_temp; 563 u8 smbus_bitmap; 564 u8 ec_special_config; 565 }; 566 567 /* 568 * For each registered chip, we need to keep some data in memory. 569 * The structure is dynamically allocated. 570 */ 571 struct it87_data { 572 const struct attribute_group *groups[7]; 573 int sioaddr; 574 enum chips type; 575 u32 features; 576 u8 peci_mask; 577 u8 old_peci_mask; 578 579 u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */ 580 u8 ec_special_config; /* EC special config register restore value */ 581 582 unsigned short addr; 583 const char *name; 584 struct mutex update_lock; 585 bool valid; /* true if following fields are valid */ 586 unsigned long last_updated; /* In jiffies */ 587 588 u16 in_scaled; /* Internal voltage sensors are scaled */ 589 u16 in_internal; /* Bitfield, internal sensors (for labels) */ 590 u16 has_in; /* Bitfield, voltage sensors enabled */ 591 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */ 592 bool need_in7_reroute; 593 u8 has_fan; /* Bitfield, fans enabled */ 594 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */ 595 u8 has_temp; /* Bitfield, temp sensors enabled */ 596 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */ 597 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */ 598 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */ 599 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */ 600 bool has_vid; /* True if VID supported */ 601 u8 vid; /* Register encoding, combined */ 602 u8 vrm; 603 u32 alarms; /* Register encoding, combined */ 604 bool has_beep; /* true if beep supported */ 605 u8 beeps; /* Register encoding */ 606 u8 fan_main_ctrl; /* Register value */ 607 u8 fan_ctl; /* Register value */ 608 609 /* 610 * The following 3 arrays correspond to the same registers up to 611 * the IT8720F. The meaning of bits 6-0 depends on the value of bit 612 * 7, and we want to preserve settings on mode changes, so we have 613 * to track all values separately. 614 * Starting with the IT8721F, the manual PWM duty cycles are stored 615 * in separate registers (8-bit values), so the separate tracking 616 * is no longer needed, but it is still done to keep the driver 617 * simple. 618 */ 619 u8 has_pwm; /* Bitfield, pwm control enabled */ 620 u8 pwm_ctrl[NUM_PWM]; /* Register value */ 621 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */ 622 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */ 623 624 /* Automatic fan speed control registers */ 625 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */ 626 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */ 627 }; 628 629 /* Board specific settings from DMI matching */ 630 struct it87_dmi_data { 631 u8 skip_pwm; /* pwm channels to skip for this board */ 632 }; 633 634 /* Global for results from DMI matching, if needed */ 635 static struct it87_dmi_data *dmi_data; 636 637 static int adc_lsb(const struct it87_data *data, int nr) 638 { 639 int lsb; 640 641 if (has_12mv_adc(data)) 642 lsb = 120; 643 else if (has_10_9mv_adc(data)) 644 lsb = 109; 645 else 646 lsb = 160; 647 if (data->in_scaled & BIT(nr)) 648 lsb <<= 1; 649 return lsb; 650 } 651 652 static u8 in_to_reg(const struct it87_data *data, int nr, long val) 653 { 654 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr)); 655 return clamp_val(val, 0, 255); 656 } 657 658 static int in_from_reg(const struct it87_data *data, int nr, int val) 659 { 660 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10); 661 } 662 663 static inline u8 FAN_TO_REG(long rpm, int div) 664 { 665 if (rpm == 0) 666 return 255; 667 rpm = clamp_val(rpm, 1, 1000000); 668 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254); 669 } 670 671 static inline u16 FAN16_TO_REG(long rpm) 672 { 673 if (rpm == 0) 674 return 0xffff; 675 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe); 676 } 677 678 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \ 679 1350000 / ((val) * (div))) 680 /* The divider is fixed to 2 in 16-bit mode */ 681 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \ 682 1350000 / ((val) * 2)) 683 684 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \ 685 ((val) + 500) / 1000), -128, 127)) 686 #define TEMP_FROM_REG(val) ((val) * 1000) 687 688 static u8 pwm_to_reg(const struct it87_data *data, long val) 689 { 690 if (has_newer_autopwm(data)) 691 return val; 692 else 693 return val >> 1; 694 } 695 696 static int pwm_from_reg(const struct it87_data *data, u8 reg) 697 { 698 if (has_newer_autopwm(data)) 699 return reg; 700 else 701 return (reg & 0x7f) << 1; 702 } 703 704 static int DIV_TO_REG(int val) 705 { 706 int answer = 0; 707 708 while (answer < 7 && (val >>= 1)) 709 answer++; 710 return answer; 711 } 712 713 #define DIV_FROM_REG(val) BIT(val) 714 715 /* 716 * PWM base frequencies. The frequency has to be divided by either 128 or 256, 717 * depending on the chip type, to calculate the actual PWM frequency. 718 * 719 * Some of the chip datasheets suggest a base frequency of 51 kHz instead 720 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency 721 * of 200 Hz. Sometimes both PWM frequency select registers are affected, 722 * sometimes just one. It is unknown if this is a datasheet error or real, 723 * so this is ignored for now. 724 */ 725 static const unsigned int pwm_freq[8] = { 726 48000000, 727 24000000, 728 12000000, 729 8000000, 730 6000000, 731 3000000, 732 1500000, 733 750000, 734 }; 735 736 static int smbus_disable(struct it87_data *data) 737 { 738 int err; 739 740 if (data->smbus_bitmap) { 741 err = superio_enter(data->sioaddr); 742 if (err) 743 return err; 744 superio_select(data->sioaddr, PME); 745 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG, 746 data->ec_special_config & ~data->smbus_bitmap); 747 superio_exit(data->sioaddr, has_conf_noexit(data)); 748 } 749 return 0; 750 } 751 752 static int smbus_enable(struct it87_data *data) 753 { 754 int err; 755 756 if (data->smbus_bitmap) { 757 err = superio_enter(data->sioaddr); 758 if (err) 759 return err; 760 761 superio_select(data->sioaddr, PME); 762 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG, 763 data->ec_special_config); 764 superio_exit(data->sioaddr, has_conf_noexit(data)); 765 } 766 return 0; 767 } 768 769 /* 770 * Must be called with data->update_lock held, except during initialization. 771 * Must be called with SMBus accesses disabled. 772 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, 773 * would slow down the IT87 access and should not be necessary. 774 */ 775 static int it87_read_value(struct it87_data *data, u8 reg) 776 { 777 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); 778 return inb_p(data->addr + IT87_DATA_REG_OFFSET); 779 } 780 781 /* 782 * Must be called with data->update_lock held, except during initialization. 783 * Must be called with SMBus accesses disabled. 784 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, 785 * would slow down the IT87 access and should not be necessary. 786 */ 787 static void it87_write_value(struct it87_data *data, u8 reg, u8 value) 788 { 789 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); 790 outb_p(value, data->addr + IT87_DATA_REG_OFFSET); 791 } 792 793 static void it87_update_pwm_ctrl(struct it87_data *data, int nr) 794 { 795 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]); 796 if (has_newer_autopwm(data)) { 797 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; 798 data->pwm_duty[nr] = it87_read_value(data, 799 IT87_REG_PWM_DUTY[nr]); 800 } else { 801 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */ 802 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; 803 else /* Manual mode */ 804 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f; 805 } 806 807 if (has_old_autopwm(data)) { 808 int i; 809 810 for (i = 0; i < 5 ; i++) 811 data->auto_temp[nr][i] = it87_read_value(data, 812 IT87_REG_AUTO_TEMP(nr, i)); 813 for (i = 0; i < 3 ; i++) 814 data->auto_pwm[nr][i] = it87_read_value(data, 815 IT87_REG_AUTO_PWM(nr, i)); 816 } else if (has_newer_autopwm(data)) { 817 int i; 818 819 /* 820 * 0: temperature hysteresis (base + 5) 821 * 1: fan off temperature (base + 0) 822 * 2: fan start temperature (base + 1) 823 * 3: fan max temperature (base + 2) 824 */ 825 data->auto_temp[nr][0] = 826 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5)); 827 828 for (i = 0; i < 3 ; i++) 829 data->auto_temp[nr][i + 1] = 830 it87_read_value(data, 831 IT87_REG_AUTO_TEMP(nr, i)); 832 /* 833 * 0: start pwm value (base + 3) 834 * 1: pwm slope (base + 4, 1/8th pwm) 835 */ 836 data->auto_pwm[nr][0] = 837 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3)); 838 data->auto_pwm[nr][1] = 839 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4)); 840 } 841 } 842 843 static int it87_lock(struct it87_data *data) 844 { 845 int err; 846 847 mutex_lock(&data->update_lock); 848 err = smbus_disable(data); 849 if (err) 850 mutex_unlock(&data->update_lock); 851 return err; 852 } 853 854 static void it87_unlock(struct it87_data *data) 855 { 856 smbus_enable(data); 857 mutex_unlock(&data->update_lock); 858 } 859 860 static struct it87_data *it87_update_device(struct device *dev) 861 { 862 struct it87_data *data = dev_get_drvdata(dev); 863 struct it87_data *ret = data; 864 int err; 865 int i; 866 867 mutex_lock(&data->update_lock); 868 869 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) || 870 !data->valid) { 871 err = smbus_disable(data); 872 if (err) { 873 ret = ERR_PTR(err); 874 goto unlock; 875 } 876 if (update_vbat) { 877 /* 878 * Cleared after each update, so reenable. Value 879 * returned by this read will be previous value 880 */ 881 it87_write_value(data, IT87_REG_CONFIG, 882 it87_read_value(data, IT87_REG_CONFIG) | 0x40); 883 } 884 for (i = 0; i < NUM_VIN; i++) { 885 if (!(data->has_in & BIT(i))) 886 continue; 887 888 data->in[i][0] = 889 it87_read_value(data, IT87_REG_VIN[i]); 890 891 /* VBAT and AVCC don't have limit registers */ 892 if (i >= NUM_VIN_LIMIT) 893 continue; 894 895 data->in[i][1] = 896 it87_read_value(data, IT87_REG_VIN_MIN(i)); 897 data->in[i][2] = 898 it87_read_value(data, IT87_REG_VIN_MAX(i)); 899 } 900 901 for (i = 0; i < NUM_FAN; i++) { 902 /* Skip disabled fans */ 903 if (!(data->has_fan & BIT(i))) 904 continue; 905 906 data->fan[i][1] = 907 it87_read_value(data, IT87_REG_FAN_MIN[i]); 908 data->fan[i][0] = it87_read_value(data, 909 IT87_REG_FAN[i]); 910 /* Add high byte if in 16-bit mode */ 911 if (has_16bit_fans(data)) { 912 data->fan[i][0] |= it87_read_value(data, 913 IT87_REG_FANX[i]) << 8; 914 data->fan[i][1] |= it87_read_value(data, 915 IT87_REG_FANX_MIN[i]) << 8; 916 } 917 } 918 for (i = 0; i < NUM_TEMP; i++) { 919 if (!(data->has_temp & BIT(i))) 920 continue; 921 data->temp[i][0] = 922 it87_read_value(data, IT87_REG_TEMP(i)); 923 924 if (has_temp_offset(data) && i < NUM_TEMP_OFFSET) 925 data->temp[i][3] = 926 it87_read_value(data, 927 IT87_REG_TEMP_OFFSET[i]); 928 929 if (i >= NUM_TEMP_LIMIT) 930 continue; 931 932 data->temp[i][1] = 933 it87_read_value(data, IT87_REG_TEMP_LOW(i)); 934 data->temp[i][2] = 935 it87_read_value(data, IT87_REG_TEMP_HIGH(i)); 936 } 937 938 /* Newer chips don't have clock dividers */ 939 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) { 940 i = it87_read_value(data, IT87_REG_FAN_DIV); 941 data->fan_div[0] = i & 0x07; 942 data->fan_div[1] = (i >> 3) & 0x07; 943 data->fan_div[2] = (i & 0x40) ? 3 : 1; 944 } 945 946 data->alarms = 947 it87_read_value(data, IT87_REG_ALARM1) | 948 (it87_read_value(data, IT87_REG_ALARM2) << 8) | 949 (it87_read_value(data, IT87_REG_ALARM3) << 16); 950 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); 951 952 data->fan_main_ctrl = it87_read_value(data, 953 IT87_REG_FAN_MAIN_CTRL); 954 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL); 955 for (i = 0; i < NUM_PWM; i++) { 956 if (!(data->has_pwm & BIT(i))) 957 continue; 958 it87_update_pwm_ctrl(data, i); 959 } 960 961 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); 962 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); 963 /* 964 * The IT8705F does not have VID capability. 965 * The IT8718F and later don't use IT87_REG_VID for the 966 * same purpose. 967 */ 968 if (data->type == it8712 || data->type == it8716) { 969 data->vid = it87_read_value(data, IT87_REG_VID); 970 /* 971 * The older IT8712F revisions had only 5 VID pins, 972 * but we assume it is always safe to read 6 bits. 973 */ 974 data->vid &= 0x3f; 975 } 976 data->last_updated = jiffies; 977 data->valid = true; 978 smbus_enable(data); 979 } 980 unlock: 981 mutex_unlock(&data->update_lock); 982 return ret; 983 } 984 985 static ssize_t show_in(struct device *dev, struct device_attribute *attr, 986 char *buf) 987 { 988 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 989 struct it87_data *data = it87_update_device(dev); 990 int index = sattr->index; 991 int nr = sattr->nr; 992 993 if (IS_ERR(data)) 994 return PTR_ERR(data); 995 996 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index])); 997 } 998 999 static ssize_t set_in(struct device *dev, struct device_attribute *attr, 1000 const char *buf, size_t count) 1001 { 1002 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1003 struct it87_data *data = dev_get_drvdata(dev); 1004 int index = sattr->index; 1005 int nr = sattr->nr; 1006 unsigned long val; 1007 int err; 1008 1009 if (kstrtoul(buf, 10, &val) < 0) 1010 return -EINVAL; 1011 1012 err = it87_lock(data); 1013 if (err) 1014 return err; 1015 1016 data->in[nr][index] = in_to_reg(data, nr, val); 1017 it87_write_value(data, 1018 index == 1 ? IT87_REG_VIN_MIN(nr) 1019 : IT87_REG_VIN_MAX(nr), 1020 data->in[nr][index]); 1021 it87_unlock(data); 1022 return count; 1023 } 1024 1025 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0); 1026 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in, 1027 0, 1); 1028 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in, 1029 0, 2); 1030 1031 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0); 1032 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in, 1033 1, 1); 1034 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in, 1035 1, 2); 1036 1037 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0); 1038 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in, 1039 2, 1); 1040 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in, 1041 2, 2); 1042 1043 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0); 1044 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in, 1045 3, 1); 1046 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in, 1047 3, 2); 1048 1049 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0); 1050 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in, 1051 4, 1); 1052 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in, 1053 4, 2); 1054 1055 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0); 1056 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in, 1057 5, 1); 1058 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in, 1059 5, 2); 1060 1061 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0); 1062 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in, 1063 6, 1); 1064 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in, 1065 6, 2); 1066 1067 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0); 1068 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in, 1069 7, 1); 1070 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in, 1071 7, 2); 1072 1073 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0); 1074 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0); 1075 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0); 1076 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0); 1077 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0); 1078 1079 /* Up to 6 temperatures */ 1080 static ssize_t show_temp(struct device *dev, struct device_attribute *attr, 1081 char *buf) 1082 { 1083 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1084 int nr = sattr->nr; 1085 int index = sattr->index; 1086 struct it87_data *data = it87_update_device(dev); 1087 1088 if (IS_ERR(data)) 1089 return PTR_ERR(data); 1090 1091 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index])); 1092 } 1093 1094 static ssize_t set_temp(struct device *dev, struct device_attribute *attr, 1095 const char *buf, size_t count) 1096 { 1097 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1098 int nr = sattr->nr; 1099 int index = sattr->index; 1100 struct it87_data *data = dev_get_drvdata(dev); 1101 long val; 1102 u8 reg, regval; 1103 int err; 1104 1105 if (kstrtol(buf, 10, &val) < 0) 1106 return -EINVAL; 1107 1108 err = it87_lock(data); 1109 if (err) 1110 return err; 1111 1112 switch (index) { 1113 default: 1114 case 1: 1115 reg = IT87_REG_TEMP_LOW(nr); 1116 break; 1117 case 2: 1118 reg = IT87_REG_TEMP_HIGH(nr); 1119 break; 1120 case 3: 1121 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE); 1122 if (!(regval & 0x80)) { 1123 regval |= 0x80; 1124 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval); 1125 } 1126 data->valid = false; 1127 reg = IT87_REG_TEMP_OFFSET[nr]; 1128 break; 1129 } 1130 1131 data->temp[nr][index] = TEMP_TO_REG(val); 1132 it87_write_value(data, reg, data->temp[nr][index]); 1133 it87_unlock(data); 1134 return count; 1135 } 1136 1137 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0); 1138 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 1139 0, 1); 1140 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 1141 0, 2); 1142 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp, 1143 set_temp, 0, 3); 1144 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0); 1145 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 1146 1, 1); 1147 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 1148 1, 2); 1149 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp, 1150 set_temp, 1, 3); 1151 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0); 1152 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 1153 2, 1); 1154 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 1155 2, 2); 1156 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp, 1157 set_temp, 2, 3); 1158 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0); 1159 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0); 1160 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0); 1161 1162 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr, 1163 char *buf) 1164 { 1165 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1166 int nr = sensor_attr->index; 1167 struct it87_data *data = it87_update_device(dev); 1168 u8 reg, extra; 1169 1170 if (IS_ERR(data)) 1171 return PTR_ERR(data); 1172 1173 reg = data->sensor; /* In case value is updated while used */ 1174 extra = data->extra; 1175 1176 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) || 1177 (has_temp_old_peci(data, nr) && (extra & 0x80))) 1178 return sprintf(buf, "6\n"); /* Intel PECI */ 1179 if (reg & (1 << nr)) 1180 return sprintf(buf, "3\n"); /* thermal diode */ 1181 if (reg & (8 << nr)) 1182 return sprintf(buf, "4\n"); /* thermistor */ 1183 return sprintf(buf, "0\n"); /* disabled */ 1184 } 1185 1186 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr, 1187 const char *buf, size_t count) 1188 { 1189 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1190 int nr = sensor_attr->index; 1191 1192 struct it87_data *data = dev_get_drvdata(dev); 1193 long val; 1194 u8 reg, extra; 1195 int err; 1196 1197 if (kstrtol(buf, 10, &val) < 0) 1198 return -EINVAL; 1199 1200 err = it87_lock(data); 1201 if (err) 1202 return err; 1203 1204 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); 1205 reg &= ~(1 << nr); 1206 reg &= ~(8 << nr); 1207 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6)) 1208 reg &= 0x3f; 1209 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); 1210 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6)) 1211 extra &= 0x7f; 1212 if (val == 2) { /* backwards compatibility */ 1213 dev_warn(dev, 1214 "Sensor type 2 is deprecated, please use 4 instead\n"); 1215 val = 4; 1216 } 1217 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */ 1218 if (val == 3) 1219 reg |= 1 << nr; 1220 else if (val == 4) 1221 reg |= 8 << nr; 1222 else if (has_temp_peci(data, nr) && val == 6) 1223 reg |= (nr + 1) << 6; 1224 else if (has_temp_old_peci(data, nr) && val == 6) 1225 extra |= 0x80; 1226 else if (val != 0) { 1227 count = -EINVAL; 1228 goto unlock; 1229 } 1230 1231 data->sensor = reg; 1232 data->extra = extra; 1233 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor); 1234 if (has_temp_old_peci(data, nr)) 1235 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); 1236 data->valid = false; /* Force cache refresh */ 1237 unlock: 1238 it87_unlock(data); 1239 return count; 1240 } 1241 1242 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type, 1243 set_temp_type, 0); 1244 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type, 1245 set_temp_type, 1); 1246 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type, 1247 set_temp_type, 2); 1248 1249 /* 6 Fans */ 1250 1251 static int pwm_mode(const struct it87_data *data, int nr) 1252 { 1253 if (has_fanctl_onoff(data) && nr < 3 && 1254 !(data->fan_main_ctrl & BIT(nr))) 1255 return 0; /* Full speed */ 1256 if (data->pwm_ctrl[nr] & 0x80) 1257 return 2; /* Automatic mode */ 1258 if ((!has_fanctl_onoff(data) || nr >= 3) && 1259 data->pwm_duty[nr] == pwm_to_reg(data, 0xff)) 1260 return 0; /* Full speed */ 1261 1262 return 1; /* Manual mode */ 1263 } 1264 1265 static ssize_t show_fan(struct device *dev, struct device_attribute *attr, 1266 char *buf) 1267 { 1268 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1269 int nr = sattr->nr; 1270 int index = sattr->index; 1271 int speed; 1272 struct it87_data *data = it87_update_device(dev); 1273 1274 if (IS_ERR(data)) 1275 return PTR_ERR(data); 1276 1277 speed = has_16bit_fans(data) ? 1278 FAN16_FROM_REG(data->fan[nr][index]) : 1279 FAN_FROM_REG(data->fan[nr][index], 1280 DIV_FROM_REG(data->fan_div[nr])); 1281 return sprintf(buf, "%d\n", speed); 1282 } 1283 1284 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr, 1285 char *buf) 1286 { 1287 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1288 struct it87_data *data = it87_update_device(dev); 1289 int nr = sensor_attr->index; 1290 1291 if (IS_ERR(data)) 1292 return PTR_ERR(data); 1293 1294 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr])); 1295 } 1296 1297 static ssize_t show_pwm_enable(struct device *dev, 1298 struct device_attribute *attr, char *buf) 1299 { 1300 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1301 struct it87_data *data = it87_update_device(dev); 1302 int nr = sensor_attr->index; 1303 1304 if (IS_ERR(data)) 1305 return PTR_ERR(data); 1306 1307 return sprintf(buf, "%d\n", pwm_mode(data, nr)); 1308 } 1309 1310 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, 1311 char *buf) 1312 { 1313 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1314 struct it87_data *data = it87_update_device(dev); 1315 int nr = sensor_attr->index; 1316 1317 if (IS_ERR(data)) 1318 return PTR_ERR(data); 1319 1320 return sprintf(buf, "%d\n", 1321 pwm_from_reg(data, data->pwm_duty[nr])); 1322 } 1323 1324 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr, 1325 char *buf) 1326 { 1327 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1328 struct it87_data *data = it87_update_device(dev); 1329 int nr = sensor_attr->index; 1330 unsigned int freq; 1331 int index; 1332 1333 if (IS_ERR(data)) 1334 return PTR_ERR(data); 1335 1336 if (has_pwm_freq2(data) && nr == 1) 1337 index = (data->extra >> 4) & 0x07; 1338 else 1339 index = (data->fan_ctl >> 4) & 0x07; 1340 1341 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128); 1342 1343 return sprintf(buf, "%u\n", freq); 1344 } 1345 1346 static ssize_t set_fan(struct device *dev, struct device_attribute *attr, 1347 const char *buf, size_t count) 1348 { 1349 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1350 int nr = sattr->nr; 1351 int index = sattr->index; 1352 1353 struct it87_data *data = dev_get_drvdata(dev); 1354 long val; 1355 int err; 1356 u8 reg; 1357 1358 if (kstrtol(buf, 10, &val) < 0) 1359 return -EINVAL; 1360 1361 err = it87_lock(data); 1362 if (err) 1363 return err; 1364 1365 if (has_16bit_fans(data)) { 1366 data->fan[nr][index] = FAN16_TO_REG(val); 1367 it87_write_value(data, IT87_REG_FAN_MIN[nr], 1368 data->fan[nr][index] & 0xff); 1369 it87_write_value(data, IT87_REG_FANX_MIN[nr], 1370 data->fan[nr][index] >> 8); 1371 } else { 1372 reg = it87_read_value(data, IT87_REG_FAN_DIV); 1373 switch (nr) { 1374 case 0: 1375 data->fan_div[nr] = reg & 0x07; 1376 break; 1377 case 1: 1378 data->fan_div[nr] = (reg >> 3) & 0x07; 1379 break; 1380 case 2: 1381 data->fan_div[nr] = (reg & 0x40) ? 3 : 1; 1382 break; 1383 } 1384 data->fan[nr][index] = 1385 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); 1386 it87_write_value(data, IT87_REG_FAN_MIN[nr], 1387 data->fan[nr][index]); 1388 } 1389 1390 it87_unlock(data); 1391 return count; 1392 } 1393 1394 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr, 1395 const char *buf, size_t count) 1396 { 1397 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1398 struct it87_data *data = dev_get_drvdata(dev); 1399 int nr = sensor_attr->index; 1400 unsigned long val; 1401 int min, err; 1402 u8 old; 1403 1404 if (kstrtoul(buf, 10, &val) < 0) 1405 return -EINVAL; 1406 1407 err = it87_lock(data); 1408 if (err) 1409 return err; 1410 1411 old = it87_read_value(data, IT87_REG_FAN_DIV); 1412 1413 /* Save fan min limit */ 1414 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr])); 1415 1416 switch (nr) { 1417 case 0: 1418 case 1: 1419 data->fan_div[nr] = DIV_TO_REG(val); 1420 break; 1421 case 2: 1422 if (val < 8) 1423 data->fan_div[nr] = 1; 1424 else 1425 data->fan_div[nr] = 3; 1426 } 1427 val = old & 0x80; 1428 val |= (data->fan_div[0] & 0x07); 1429 val |= (data->fan_div[1] & 0x07) << 3; 1430 if (data->fan_div[2] == 3) 1431 val |= 0x1 << 6; 1432 it87_write_value(data, IT87_REG_FAN_DIV, val); 1433 1434 /* Restore fan min limit */ 1435 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr])); 1436 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]); 1437 1438 it87_unlock(data); 1439 return count; 1440 } 1441 1442 /* Returns 0 if OK, -EINVAL otherwise */ 1443 static int check_trip_points(struct device *dev, int nr) 1444 { 1445 const struct it87_data *data = dev_get_drvdata(dev); 1446 int i, err = 0; 1447 1448 if (has_old_autopwm(data)) { 1449 for (i = 0; i < 3; i++) { 1450 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) 1451 err = -EINVAL; 1452 } 1453 for (i = 0; i < 2; i++) { 1454 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1]) 1455 err = -EINVAL; 1456 } 1457 } else if (has_newer_autopwm(data)) { 1458 for (i = 1; i < 3; i++) { 1459 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) 1460 err = -EINVAL; 1461 } 1462 } 1463 1464 if (err) { 1465 dev_err(dev, 1466 "Inconsistent trip points, not switching to automatic mode\n"); 1467 dev_err(dev, "Adjust the trip points and try again\n"); 1468 } 1469 return err; 1470 } 1471 1472 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr, 1473 const char *buf, size_t count) 1474 { 1475 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1476 struct it87_data *data = dev_get_drvdata(dev); 1477 int nr = sensor_attr->index; 1478 long val; 1479 int err; 1480 1481 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2) 1482 return -EINVAL; 1483 1484 /* Check trip points before switching to automatic mode */ 1485 if (val == 2) { 1486 if (check_trip_points(dev, nr) < 0) 1487 return -EINVAL; 1488 } 1489 1490 err = it87_lock(data); 1491 if (err) 1492 return err; 1493 1494 if (val == 0) { 1495 if (nr < 3 && has_fanctl_onoff(data)) { 1496 int tmp; 1497 /* make sure the fan is on when in on/off mode */ 1498 tmp = it87_read_value(data, IT87_REG_FAN_CTL); 1499 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr)); 1500 /* set on/off mode */ 1501 data->fan_main_ctrl &= ~BIT(nr); 1502 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 1503 data->fan_main_ctrl); 1504 } else { 1505 u8 ctrl; 1506 1507 /* No on/off mode, set maximum pwm value */ 1508 data->pwm_duty[nr] = pwm_to_reg(data, 0xff); 1509 it87_write_value(data, IT87_REG_PWM_DUTY[nr], 1510 data->pwm_duty[nr]); 1511 /* and set manual mode */ 1512 if (has_newer_autopwm(data)) { 1513 ctrl = (data->pwm_ctrl[nr] & 0x7c) | 1514 data->pwm_temp_map[nr]; 1515 } else { 1516 ctrl = data->pwm_duty[nr]; 1517 } 1518 data->pwm_ctrl[nr] = ctrl; 1519 it87_write_value(data, IT87_REG_PWM[nr], ctrl); 1520 } 1521 } else { 1522 u8 ctrl; 1523 1524 if (has_newer_autopwm(data)) { 1525 ctrl = (data->pwm_ctrl[nr] & 0x7c) | 1526 data->pwm_temp_map[nr]; 1527 if (val != 1) 1528 ctrl |= 0x80; 1529 } else { 1530 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80); 1531 } 1532 data->pwm_ctrl[nr] = ctrl; 1533 it87_write_value(data, IT87_REG_PWM[nr], ctrl); 1534 1535 if (has_fanctl_onoff(data) && nr < 3) { 1536 /* set SmartGuardian mode */ 1537 data->fan_main_ctrl |= BIT(nr); 1538 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 1539 data->fan_main_ctrl); 1540 } 1541 } 1542 1543 it87_unlock(data); 1544 return count; 1545 } 1546 1547 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, 1548 const char *buf, size_t count) 1549 { 1550 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1551 struct it87_data *data = dev_get_drvdata(dev); 1552 int nr = sensor_attr->index; 1553 long val; 1554 int err; 1555 1556 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) 1557 return -EINVAL; 1558 1559 err = it87_lock(data); 1560 if (err) 1561 return err; 1562 1563 it87_update_pwm_ctrl(data, nr); 1564 if (has_newer_autopwm(data)) { 1565 /* 1566 * If we are in automatic mode, the PWM duty cycle register 1567 * is read-only so we can't write the value. 1568 */ 1569 if (data->pwm_ctrl[nr] & 0x80) { 1570 count = -EBUSY; 1571 goto unlock; 1572 } 1573 data->pwm_duty[nr] = pwm_to_reg(data, val); 1574 it87_write_value(data, IT87_REG_PWM_DUTY[nr], 1575 data->pwm_duty[nr]); 1576 } else { 1577 data->pwm_duty[nr] = pwm_to_reg(data, val); 1578 /* 1579 * If we are in manual mode, write the duty cycle immediately; 1580 * otherwise, just store it for later use. 1581 */ 1582 if (!(data->pwm_ctrl[nr] & 0x80)) { 1583 data->pwm_ctrl[nr] = data->pwm_duty[nr]; 1584 it87_write_value(data, IT87_REG_PWM[nr], 1585 data->pwm_ctrl[nr]); 1586 } 1587 } 1588 unlock: 1589 it87_unlock(data); 1590 return count; 1591 } 1592 1593 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr, 1594 const char *buf, size_t count) 1595 { 1596 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1597 struct it87_data *data = dev_get_drvdata(dev); 1598 int nr = sensor_attr->index; 1599 unsigned long val; 1600 int err; 1601 int i; 1602 1603 if (kstrtoul(buf, 10, &val) < 0) 1604 return -EINVAL; 1605 1606 val = clamp_val(val, 0, 1000000); 1607 val *= has_newer_autopwm(data) ? 256 : 128; 1608 1609 /* Search for the nearest available frequency */ 1610 for (i = 0; i < 7; i++) { 1611 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2) 1612 break; 1613 } 1614 1615 err = it87_lock(data); 1616 if (err) 1617 return err; 1618 1619 if (nr == 0) { 1620 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f; 1621 data->fan_ctl |= i << 4; 1622 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl); 1623 } else { 1624 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f; 1625 data->extra |= i << 4; 1626 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); 1627 } 1628 it87_unlock(data); 1629 1630 return count; 1631 } 1632 1633 static ssize_t show_pwm_temp_map(struct device *dev, 1634 struct device_attribute *attr, char *buf) 1635 { 1636 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1637 struct it87_data *data = it87_update_device(dev); 1638 int nr = sensor_attr->index; 1639 int map; 1640 1641 if (IS_ERR(data)) 1642 return PTR_ERR(data); 1643 1644 map = data->pwm_temp_map[nr]; 1645 if (map >= 3) 1646 map = 0; /* Should never happen */ 1647 if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */ 1648 map += 3; 1649 1650 return sprintf(buf, "%d\n", (int)BIT(map)); 1651 } 1652 1653 static ssize_t set_pwm_temp_map(struct device *dev, 1654 struct device_attribute *attr, const char *buf, 1655 size_t count) 1656 { 1657 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1658 struct it87_data *data = dev_get_drvdata(dev); 1659 int nr = sensor_attr->index; 1660 long val; 1661 int err; 1662 u8 reg; 1663 1664 if (kstrtol(buf, 10, &val) < 0) 1665 return -EINVAL; 1666 1667 if (nr >= 3) 1668 val -= 3; 1669 1670 switch (val) { 1671 case BIT(0): 1672 reg = 0x00; 1673 break; 1674 case BIT(1): 1675 reg = 0x01; 1676 break; 1677 case BIT(2): 1678 reg = 0x02; 1679 break; 1680 default: 1681 return -EINVAL; 1682 } 1683 1684 err = it87_lock(data); 1685 if (err) 1686 return err; 1687 1688 it87_update_pwm_ctrl(data, nr); 1689 data->pwm_temp_map[nr] = reg; 1690 /* 1691 * If we are in automatic mode, write the temp mapping immediately; 1692 * otherwise, just store it for later use. 1693 */ 1694 if (data->pwm_ctrl[nr] & 0x80) { 1695 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) | 1696 data->pwm_temp_map[nr]; 1697 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]); 1698 } 1699 it87_unlock(data); 1700 return count; 1701 } 1702 1703 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr, 1704 char *buf) 1705 { 1706 struct it87_data *data = it87_update_device(dev); 1707 struct sensor_device_attribute_2 *sensor_attr = 1708 to_sensor_dev_attr_2(attr); 1709 int nr = sensor_attr->nr; 1710 int point = sensor_attr->index; 1711 1712 if (IS_ERR(data)) 1713 return PTR_ERR(data); 1714 1715 return sprintf(buf, "%d\n", 1716 pwm_from_reg(data, data->auto_pwm[nr][point])); 1717 } 1718 1719 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr, 1720 const char *buf, size_t count) 1721 { 1722 struct it87_data *data = dev_get_drvdata(dev); 1723 struct sensor_device_attribute_2 *sensor_attr = 1724 to_sensor_dev_attr_2(attr); 1725 int nr = sensor_attr->nr; 1726 int point = sensor_attr->index; 1727 int regaddr; 1728 long val; 1729 int err; 1730 1731 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) 1732 return -EINVAL; 1733 1734 err = it87_lock(data); 1735 if (err) 1736 return err; 1737 1738 data->auto_pwm[nr][point] = pwm_to_reg(data, val); 1739 if (has_newer_autopwm(data)) 1740 regaddr = IT87_REG_AUTO_TEMP(nr, 3); 1741 else 1742 regaddr = IT87_REG_AUTO_PWM(nr, point); 1743 it87_write_value(data, regaddr, data->auto_pwm[nr][point]); 1744 it87_unlock(data); 1745 return count; 1746 } 1747 1748 static ssize_t show_auto_pwm_slope(struct device *dev, 1749 struct device_attribute *attr, char *buf) 1750 { 1751 struct it87_data *data = it87_update_device(dev); 1752 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1753 int nr = sensor_attr->index; 1754 1755 if (IS_ERR(data)) 1756 return PTR_ERR(data); 1757 1758 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f); 1759 } 1760 1761 static ssize_t set_auto_pwm_slope(struct device *dev, 1762 struct device_attribute *attr, 1763 const char *buf, size_t count) 1764 { 1765 struct it87_data *data = dev_get_drvdata(dev); 1766 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1767 int nr = sensor_attr->index; 1768 unsigned long val; 1769 int err; 1770 1771 if (kstrtoul(buf, 10, &val) < 0 || val > 127) 1772 return -EINVAL; 1773 1774 err = it87_lock(data); 1775 if (err) 1776 return err; 1777 1778 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val; 1779 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4), 1780 data->auto_pwm[nr][1]); 1781 it87_unlock(data); 1782 return count; 1783 } 1784 1785 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr, 1786 char *buf) 1787 { 1788 struct it87_data *data = it87_update_device(dev); 1789 struct sensor_device_attribute_2 *sensor_attr = 1790 to_sensor_dev_attr_2(attr); 1791 int nr = sensor_attr->nr; 1792 int point = sensor_attr->index; 1793 int reg; 1794 1795 if (IS_ERR(data)) 1796 return PTR_ERR(data); 1797 1798 if (has_old_autopwm(data) || point) 1799 reg = data->auto_temp[nr][point]; 1800 else 1801 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f); 1802 1803 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg)); 1804 } 1805 1806 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr, 1807 const char *buf, size_t count) 1808 { 1809 struct it87_data *data = dev_get_drvdata(dev); 1810 struct sensor_device_attribute_2 *sensor_attr = 1811 to_sensor_dev_attr_2(attr); 1812 int nr = sensor_attr->nr; 1813 int point = sensor_attr->index; 1814 long val; 1815 int reg; 1816 int err; 1817 1818 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000) 1819 return -EINVAL; 1820 1821 err = it87_lock(data); 1822 if (err) 1823 return err; 1824 1825 if (has_newer_autopwm(data) && !point) { 1826 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val); 1827 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0); 1828 data->auto_temp[nr][0] = reg; 1829 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg); 1830 } else { 1831 reg = TEMP_TO_REG(val); 1832 data->auto_temp[nr][point] = reg; 1833 if (has_newer_autopwm(data)) 1834 point--; 1835 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg); 1836 } 1837 it87_unlock(data); 1838 return count; 1839 } 1840 1841 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0); 1842 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1843 0, 1); 1844 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div, 1845 set_fan_div, 0); 1846 1847 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0); 1848 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1849 1, 1); 1850 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div, 1851 set_fan_div, 1); 1852 1853 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0); 1854 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1855 2, 1); 1856 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div, 1857 set_fan_div, 2); 1858 1859 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0); 1860 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1861 3, 1); 1862 1863 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0); 1864 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1865 4, 1); 1866 1867 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0); 1868 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1869 5, 1); 1870 1871 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, 1872 show_pwm_enable, set_pwm_enable, 0); 1873 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0); 1874 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, 1875 set_pwm_freq, 0); 1876 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO, 1877 show_pwm_temp_map, set_pwm_temp_map, 0); 1878 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR, 1879 show_auto_pwm, set_auto_pwm, 0, 0); 1880 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR, 1881 show_auto_pwm, set_auto_pwm, 0, 1); 1882 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR, 1883 show_auto_pwm, set_auto_pwm, 0, 2); 1884 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO, 1885 show_auto_pwm, NULL, 0, 3); 1886 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR, 1887 show_auto_temp, set_auto_temp, 0, 1); 1888 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1889 show_auto_temp, set_auto_temp, 0, 0); 1890 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR, 1891 show_auto_temp, set_auto_temp, 0, 2); 1892 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR, 1893 show_auto_temp, set_auto_temp, 0, 3); 1894 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR, 1895 show_auto_temp, set_auto_temp, 0, 4); 1896 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR, 1897 show_auto_pwm, set_auto_pwm, 0, 0); 1898 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR, 1899 show_auto_pwm_slope, set_auto_pwm_slope, 0); 1900 1901 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR, 1902 show_pwm_enable, set_pwm_enable, 1); 1903 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1); 1904 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1); 1905 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO, 1906 show_pwm_temp_map, set_pwm_temp_map, 1); 1907 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR, 1908 show_auto_pwm, set_auto_pwm, 1, 0); 1909 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR, 1910 show_auto_pwm, set_auto_pwm, 1, 1); 1911 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR, 1912 show_auto_pwm, set_auto_pwm, 1, 2); 1913 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO, 1914 show_auto_pwm, NULL, 1, 3); 1915 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR, 1916 show_auto_temp, set_auto_temp, 1, 1); 1917 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1918 show_auto_temp, set_auto_temp, 1, 0); 1919 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR, 1920 show_auto_temp, set_auto_temp, 1, 2); 1921 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR, 1922 show_auto_temp, set_auto_temp, 1, 3); 1923 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR, 1924 show_auto_temp, set_auto_temp, 1, 4); 1925 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR, 1926 show_auto_pwm, set_auto_pwm, 1, 0); 1927 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR, 1928 show_auto_pwm_slope, set_auto_pwm_slope, 1); 1929 1930 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR, 1931 show_pwm_enable, set_pwm_enable, 2); 1932 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2); 1933 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2); 1934 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO, 1935 show_pwm_temp_map, set_pwm_temp_map, 2); 1936 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR, 1937 show_auto_pwm, set_auto_pwm, 2, 0); 1938 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR, 1939 show_auto_pwm, set_auto_pwm, 2, 1); 1940 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR, 1941 show_auto_pwm, set_auto_pwm, 2, 2); 1942 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO, 1943 show_auto_pwm, NULL, 2, 3); 1944 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR, 1945 show_auto_temp, set_auto_temp, 2, 1); 1946 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1947 show_auto_temp, set_auto_temp, 2, 0); 1948 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR, 1949 show_auto_temp, set_auto_temp, 2, 2); 1950 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR, 1951 show_auto_temp, set_auto_temp, 2, 3); 1952 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR, 1953 show_auto_temp, set_auto_temp, 2, 4); 1954 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR, 1955 show_auto_pwm, set_auto_pwm, 2, 0); 1956 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR, 1957 show_auto_pwm_slope, set_auto_pwm_slope, 2); 1958 1959 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR, 1960 show_pwm_enable, set_pwm_enable, 3); 1961 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3); 1962 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3); 1963 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO, 1964 show_pwm_temp_map, set_pwm_temp_map, 3); 1965 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR, 1966 show_auto_temp, set_auto_temp, 2, 1); 1967 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1968 show_auto_temp, set_auto_temp, 2, 0); 1969 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR, 1970 show_auto_temp, set_auto_temp, 2, 2); 1971 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR, 1972 show_auto_temp, set_auto_temp, 2, 3); 1973 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR, 1974 show_auto_pwm, set_auto_pwm, 3, 0); 1975 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR, 1976 show_auto_pwm_slope, set_auto_pwm_slope, 3); 1977 1978 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR, 1979 show_pwm_enable, set_pwm_enable, 4); 1980 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4); 1981 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4); 1982 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO, 1983 show_pwm_temp_map, set_pwm_temp_map, 4); 1984 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR, 1985 show_auto_temp, set_auto_temp, 2, 1); 1986 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1987 show_auto_temp, set_auto_temp, 2, 0); 1988 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR, 1989 show_auto_temp, set_auto_temp, 2, 2); 1990 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR, 1991 show_auto_temp, set_auto_temp, 2, 3); 1992 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR, 1993 show_auto_pwm, set_auto_pwm, 4, 0); 1994 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR, 1995 show_auto_pwm_slope, set_auto_pwm_slope, 4); 1996 1997 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR, 1998 show_pwm_enable, set_pwm_enable, 5); 1999 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5); 2000 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5); 2001 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO, 2002 show_pwm_temp_map, set_pwm_temp_map, 5); 2003 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR, 2004 show_auto_temp, set_auto_temp, 2, 1); 2005 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 2006 show_auto_temp, set_auto_temp, 2, 0); 2007 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR, 2008 show_auto_temp, set_auto_temp, 2, 2); 2009 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR, 2010 show_auto_temp, set_auto_temp, 2, 3); 2011 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR, 2012 show_auto_pwm, set_auto_pwm, 5, 0); 2013 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR, 2014 show_auto_pwm_slope, set_auto_pwm_slope, 5); 2015 2016 /* Alarms */ 2017 static ssize_t alarms_show(struct device *dev, struct device_attribute *attr, 2018 char *buf) 2019 { 2020 struct it87_data *data = it87_update_device(dev); 2021 2022 if (IS_ERR(data)) 2023 return PTR_ERR(data); 2024 2025 return sprintf(buf, "%u\n", data->alarms); 2026 } 2027 static DEVICE_ATTR_RO(alarms); 2028 2029 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, 2030 char *buf) 2031 { 2032 struct it87_data *data = it87_update_device(dev); 2033 int bitnr = to_sensor_dev_attr(attr)->index; 2034 2035 if (IS_ERR(data)) 2036 return PTR_ERR(data); 2037 2038 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1); 2039 } 2040 2041 static ssize_t clear_intrusion(struct device *dev, 2042 struct device_attribute *attr, const char *buf, 2043 size_t count) 2044 { 2045 struct it87_data *data = dev_get_drvdata(dev); 2046 int err, config; 2047 long val; 2048 2049 if (kstrtol(buf, 10, &val) < 0 || val != 0) 2050 return -EINVAL; 2051 2052 err = it87_lock(data); 2053 if (err) 2054 return err; 2055 2056 config = it87_read_value(data, IT87_REG_CONFIG); 2057 if (config < 0) { 2058 count = config; 2059 } else { 2060 config |= BIT(5); 2061 it87_write_value(data, IT87_REG_CONFIG, config); 2062 /* Invalidate cache to force re-read */ 2063 data->valid = false; 2064 } 2065 it87_unlock(data); 2066 return count; 2067 } 2068 2069 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8); 2070 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9); 2071 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10); 2072 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11); 2073 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12); 2074 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13); 2075 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14); 2076 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15); 2077 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0); 2078 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1); 2079 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2); 2080 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3); 2081 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6); 2082 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7); 2083 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16); 2084 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17); 2085 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18); 2086 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR, 2087 show_alarm, clear_intrusion, 4); 2088 2089 static ssize_t show_beep(struct device *dev, struct device_attribute *attr, 2090 char *buf) 2091 { 2092 struct it87_data *data = it87_update_device(dev); 2093 int bitnr = to_sensor_dev_attr(attr)->index; 2094 2095 if (IS_ERR(data)) 2096 return PTR_ERR(data); 2097 2098 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1); 2099 } 2100 2101 static ssize_t set_beep(struct device *dev, struct device_attribute *attr, 2102 const char *buf, size_t count) 2103 { 2104 int bitnr = to_sensor_dev_attr(attr)->index; 2105 struct it87_data *data = dev_get_drvdata(dev); 2106 long val; 2107 int err; 2108 2109 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1)) 2110 return -EINVAL; 2111 2112 err = it87_lock(data); 2113 if (err) 2114 return err; 2115 2116 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); 2117 if (val) 2118 data->beeps |= BIT(bitnr); 2119 else 2120 data->beeps &= ~BIT(bitnr); 2121 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps); 2122 it87_unlock(data); 2123 return count; 2124 } 2125 2126 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR, 2127 show_beep, set_beep, 1); 2128 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1); 2129 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1); 2130 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1); 2131 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1); 2132 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1); 2133 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1); 2134 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1); 2135 /* fanX_beep writability is set later */ 2136 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0); 2137 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0); 2138 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0); 2139 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0); 2140 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0); 2141 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0); 2142 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR, 2143 show_beep, set_beep, 2); 2144 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2); 2145 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2); 2146 2147 static ssize_t vrm_show(struct device *dev, struct device_attribute *attr, 2148 char *buf) 2149 { 2150 struct it87_data *data = dev_get_drvdata(dev); 2151 2152 return sprintf(buf, "%u\n", data->vrm); 2153 } 2154 2155 static ssize_t vrm_store(struct device *dev, struct device_attribute *attr, 2156 const char *buf, size_t count) 2157 { 2158 struct it87_data *data = dev_get_drvdata(dev); 2159 unsigned long val; 2160 2161 if (kstrtoul(buf, 10, &val) < 0) 2162 return -EINVAL; 2163 2164 data->vrm = val; 2165 2166 return count; 2167 } 2168 static DEVICE_ATTR_RW(vrm); 2169 2170 static ssize_t cpu0_vid_show(struct device *dev, 2171 struct device_attribute *attr, char *buf) 2172 { 2173 struct it87_data *data = it87_update_device(dev); 2174 2175 if (IS_ERR(data)) 2176 return PTR_ERR(data); 2177 2178 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm)); 2179 } 2180 static DEVICE_ATTR_RO(cpu0_vid); 2181 2182 static ssize_t show_label(struct device *dev, struct device_attribute *attr, 2183 char *buf) 2184 { 2185 static const char * const labels[] = { 2186 "+5V", 2187 "5VSB", 2188 "Vbat", 2189 "AVCC", 2190 }; 2191 static const char * const labels_it8721[] = { 2192 "+3.3V", 2193 "3VSB", 2194 "Vbat", 2195 "+3.3V", 2196 }; 2197 struct it87_data *data = dev_get_drvdata(dev); 2198 int nr = to_sensor_dev_attr(attr)->index; 2199 const char *label; 2200 2201 if (has_vin3_5v(data) && nr == 0) 2202 label = labels[0]; 2203 else if (has_scaling(data)) 2204 label = labels_it8721[nr]; 2205 else 2206 label = labels[nr]; 2207 2208 return sprintf(buf, "%s\n", label); 2209 } 2210 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0); 2211 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1); 2212 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2); 2213 /* AVCC3 */ 2214 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3); 2215 2216 static umode_t it87_in_is_visible(struct kobject *kobj, 2217 struct attribute *attr, int index) 2218 { 2219 struct device *dev = kobj_to_dev(kobj); 2220 struct it87_data *data = dev_get_drvdata(dev); 2221 int i = index / 5; /* voltage index */ 2222 int a = index % 5; /* attribute index */ 2223 2224 if (index >= 40) { /* in8 and higher only have input attributes */ 2225 i = index - 40 + 8; 2226 a = 0; 2227 } 2228 2229 if (!(data->has_in & BIT(i))) 2230 return 0; 2231 2232 if (a == 4 && !data->has_beep) 2233 return 0; 2234 2235 return attr->mode; 2236 } 2237 2238 static struct attribute *it87_attributes_in[] = { 2239 &sensor_dev_attr_in0_input.dev_attr.attr, 2240 &sensor_dev_attr_in0_min.dev_attr.attr, 2241 &sensor_dev_attr_in0_max.dev_attr.attr, 2242 &sensor_dev_attr_in0_alarm.dev_attr.attr, 2243 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */ 2244 2245 &sensor_dev_attr_in1_input.dev_attr.attr, 2246 &sensor_dev_attr_in1_min.dev_attr.attr, 2247 &sensor_dev_attr_in1_max.dev_attr.attr, 2248 &sensor_dev_attr_in1_alarm.dev_attr.attr, 2249 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */ 2250 2251 &sensor_dev_attr_in2_input.dev_attr.attr, 2252 &sensor_dev_attr_in2_min.dev_attr.attr, 2253 &sensor_dev_attr_in2_max.dev_attr.attr, 2254 &sensor_dev_attr_in2_alarm.dev_attr.attr, 2255 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */ 2256 2257 &sensor_dev_attr_in3_input.dev_attr.attr, 2258 &sensor_dev_attr_in3_min.dev_attr.attr, 2259 &sensor_dev_attr_in3_max.dev_attr.attr, 2260 &sensor_dev_attr_in3_alarm.dev_attr.attr, 2261 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */ 2262 2263 &sensor_dev_attr_in4_input.dev_attr.attr, 2264 &sensor_dev_attr_in4_min.dev_attr.attr, 2265 &sensor_dev_attr_in4_max.dev_attr.attr, 2266 &sensor_dev_attr_in4_alarm.dev_attr.attr, 2267 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */ 2268 2269 &sensor_dev_attr_in5_input.dev_attr.attr, 2270 &sensor_dev_attr_in5_min.dev_attr.attr, 2271 &sensor_dev_attr_in5_max.dev_attr.attr, 2272 &sensor_dev_attr_in5_alarm.dev_attr.attr, 2273 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */ 2274 2275 &sensor_dev_attr_in6_input.dev_attr.attr, 2276 &sensor_dev_attr_in6_min.dev_attr.attr, 2277 &sensor_dev_attr_in6_max.dev_attr.attr, 2278 &sensor_dev_attr_in6_alarm.dev_attr.attr, 2279 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */ 2280 2281 &sensor_dev_attr_in7_input.dev_attr.attr, 2282 &sensor_dev_attr_in7_min.dev_attr.attr, 2283 &sensor_dev_attr_in7_max.dev_attr.attr, 2284 &sensor_dev_attr_in7_alarm.dev_attr.attr, 2285 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */ 2286 2287 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */ 2288 &sensor_dev_attr_in9_input.dev_attr.attr, 2289 &sensor_dev_attr_in10_input.dev_attr.attr, 2290 &sensor_dev_attr_in11_input.dev_attr.attr, 2291 &sensor_dev_attr_in12_input.dev_attr.attr, 2292 NULL 2293 }; 2294 2295 static const struct attribute_group it87_group_in = { 2296 .attrs = it87_attributes_in, 2297 .is_visible = it87_in_is_visible, 2298 }; 2299 2300 static umode_t it87_temp_is_visible(struct kobject *kobj, 2301 struct attribute *attr, int index) 2302 { 2303 struct device *dev = kobj_to_dev(kobj); 2304 struct it87_data *data = dev_get_drvdata(dev); 2305 int i = index / 7; /* temperature index */ 2306 int a = index % 7; /* attribute index */ 2307 2308 if (index >= 21) { 2309 i = index - 21 + 3; 2310 a = 0; 2311 } 2312 2313 if (!(data->has_temp & BIT(i))) 2314 return 0; 2315 2316 if (a == 5 && !has_temp_offset(data)) 2317 return 0; 2318 2319 if (a == 6 && !data->has_beep) 2320 return 0; 2321 2322 return attr->mode; 2323 } 2324 2325 static struct attribute *it87_attributes_temp[] = { 2326 &sensor_dev_attr_temp1_input.dev_attr.attr, 2327 &sensor_dev_attr_temp1_max.dev_attr.attr, 2328 &sensor_dev_attr_temp1_min.dev_attr.attr, 2329 &sensor_dev_attr_temp1_type.dev_attr.attr, 2330 &sensor_dev_attr_temp1_alarm.dev_attr.attr, 2331 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */ 2332 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */ 2333 2334 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */ 2335 &sensor_dev_attr_temp2_max.dev_attr.attr, 2336 &sensor_dev_attr_temp2_min.dev_attr.attr, 2337 &sensor_dev_attr_temp2_type.dev_attr.attr, 2338 &sensor_dev_attr_temp2_alarm.dev_attr.attr, 2339 &sensor_dev_attr_temp2_offset.dev_attr.attr, 2340 &sensor_dev_attr_temp2_beep.dev_attr.attr, 2341 2342 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */ 2343 &sensor_dev_attr_temp3_max.dev_attr.attr, 2344 &sensor_dev_attr_temp3_min.dev_attr.attr, 2345 &sensor_dev_attr_temp3_type.dev_attr.attr, 2346 &sensor_dev_attr_temp3_alarm.dev_attr.attr, 2347 &sensor_dev_attr_temp3_offset.dev_attr.attr, 2348 &sensor_dev_attr_temp3_beep.dev_attr.attr, 2349 2350 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */ 2351 &sensor_dev_attr_temp5_input.dev_attr.attr, 2352 &sensor_dev_attr_temp6_input.dev_attr.attr, 2353 NULL 2354 }; 2355 2356 static const struct attribute_group it87_group_temp = { 2357 .attrs = it87_attributes_temp, 2358 .is_visible = it87_temp_is_visible, 2359 }; 2360 2361 static umode_t it87_is_visible(struct kobject *kobj, 2362 struct attribute *attr, int index) 2363 { 2364 struct device *dev = kobj_to_dev(kobj); 2365 struct it87_data *data = dev_get_drvdata(dev); 2366 2367 if ((index == 2 || index == 3) && !data->has_vid) 2368 return 0; 2369 2370 if (index > 3 && !(data->in_internal & BIT(index - 4))) 2371 return 0; 2372 2373 return attr->mode; 2374 } 2375 2376 static struct attribute *it87_attributes[] = { 2377 &dev_attr_alarms.attr, 2378 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, 2379 &dev_attr_vrm.attr, /* 2 */ 2380 &dev_attr_cpu0_vid.attr, /* 3 */ 2381 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */ 2382 &sensor_dev_attr_in7_label.dev_attr.attr, 2383 &sensor_dev_attr_in8_label.dev_attr.attr, 2384 &sensor_dev_attr_in9_label.dev_attr.attr, 2385 NULL 2386 }; 2387 2388 static const struct attribute_group it87_group = { 2389 .attrs = it87_attributes, 2390 .is_visible = it87_is_visible, 2391 }; 2392 2393 static umode_t it87_fan_is_visible(struct kobject *kobj, 2394 struct attribute *attr, int index) 2395 { 2396 struct device *dev = kobj_to_dev(kobj); 2397 struct it87_data *data = dev_get_drvdata(dev); 2398 int i = index / 5; /* fan index */ 2399 int a = index % 5; /* attribute index */ 2400 2401 if (index >= 15) { /* fan 4..6 don't have divisor attributes */ 2402 i = (index - 15) / 4 + 3; 2403 a = (index - 15) % 4; 2404 } 2405 2406 if (!(data->has_fan & BIT(i))) 2407 return 0; 2408 2409 if (a == 3) { /* beep */ 2410 if (!data->has_beep) 2411 return 0; 2412 /* first fan beep attribute is writable */ 2413 if (i == __ffs(data->has_fan)) 2414 return attr->mode | S_IWUSR; 2415 } 2416 2417 if (a == 4 && has_16bit_fans(data)) /* divisor */ 2418 return 0; 2419 2420 return attr->mode; 2421 } 2422 2423 static struct attribute *it87_attributes_fan[] = { 2424 &sensor_dev_attr_fan1_input.dev_attr.attr, 2425 &sensor_dev_attr_fan1_min.dev_attr.attr, 2426 &sensor_dev_attr_fan1_alarm.dev_attr.attr, 2427 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */ 2428 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */ 2429 2430 &sensor_dev_attr_fan2_input.dev_attr.attr, 2431 &sensor_dev_attr_fan2_min.dev_attr.attr, 2432 &sensor_dev_attr_fan2_alarm.dev_attr.attr, 2433 &sensor_dev_attr_fan2_beep.dev_attr.attr, 2434 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */ 2435 2436 &sensor_dev_attr_fan3_input.dev_attr.attr, 2437 &sensor_dev_attr_fan3_min.dev_attr.attr, 2438 &sensor_dev_attr_fan3_alarm.dev_attr.attr, 2439 &sensor_dev_attr_fan3_beep.dev_attr.attr, 2440 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */ 2441 2442 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */ 2443 &sensor_dev_attr_fan4_min.dev_attr.attr, 2444 &sensor_dev_attr_fan4_alarm.dev_attr.attr, 2445 &sensor_dev_attr_fan4_beep.dev_attr.attr, 2446 2447 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */ 2448 &sensor_dev_attr_fan5_min.dev_attr.attr, 2449 &sensor_dev_attr_fan5_alarm.dev_attr.attr, 2450 &sensor_dev_attr_fan5_beep.dev_attr.attr, 2451 2452 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */ 2453 &sensor_dev_attr_fan6_min.dev_attr.attr, 2454 &sensor_dev_attr_fan6_alarm.dev_attr.attr, 2455 &sensor_dev_attr_fan6_beep.dev_attr.attr, 2456 NULL 2457 }; 2458 2459 static const struct attribute_group it87_group_fan = { 2460 .attrs = it87_attributes_fan, 2461 .is_visible = it87_fan_is_visible, 2462 }; 2463 2464 static umode_t it87_pwm_is_visible(struct kobject *kobj, 2465 struct attribute *attr, int index) 2466 { 2467 struct device *dev = kobj_to_dev(kobj); 2468 struct it87_data *data = dev_get_drvdata(dev); 2469 int i = index / 4; /* pwm index */ 2470 int a = index % 4; /* attribute index */ 2471 2472 if (!(data->has_pwm & BIT(i))) 2473 return 0; 2474 2475 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */ 2476 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data))) 2477 return attr->mode | S_IWUSR; 2478 2479 /* pwm2_freq is writable if there are two pwm frequency selects */ 2480 if (has_pwm_freq2(data) && i == 1 && a == 2) 2481 return attr->mode | S_IWUSR; 2482 2483 return attr->mode; 2484 } 2485 2486 static struct attribute *it87_attributes_pwm[] = { 2487 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 2488 &sensor_dev_attr_pwm1.dev_attr.attr, 2489 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 2490 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr, 2491 2492 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 2493 &sensor_dev_attr_pwm2.dev_attr.attr, 2494 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 2495 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr, 2496 2497 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 2498 &sensor_dev_attr_pwm3.dev_attr.attr, 2499 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 2500 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr, 2501 2502 &sensor_dev_attr_pwm4_enable.dev_attr.attr, 2503 &sensor_dev_attr_pwm4.dev_attr.attr, 2504 &sensor_dev_attr_pwm4_freq.dev_attr.attr, 2505 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr, 2506 2507 &sensor_dev_attr_pwm5_enable.dev_attr.attr, 2508 &sensor_dev_attr_pwm5.dev_attr.attr, 2509 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 2510 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr, 2511 2512 &sensor_dev_attr_pwm6_enable.dev_attr.attr, 2513 &sensor_dev_attr_pwm6.dev_attr.attr, 2514 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 2515 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr, 2516 2517 NULL 2518 }; 2519 2520 static const struct attribute_group it87_group_pwm = { 2521 .attrs = it87_attributes_pwm, 2522 .is_visible = it87_pwm_is_visible, 2523 }; 2524 2525 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj, 2526 struct attribute *attr, int index) 2527 { 2528 struct device *dev = kobj_to_dev(kobj); 2529 struct it87_data *data = dev_get_drvdata(dev); 2530 int i = index / 11; /* pwm index */ 2531 int a = index % 11; /* attribute index */ 2532 2533 if (index >= 33) { /* pwm 4..6 */ 2534 i = (index - 33) / 6 + 3; 2535 a = (index - 33) % 6 + 4; 2536 } 2537 2538 if (!(data->has_pwm & BIT(i))) 2539 return 0; 2540 2541 if (has_newer_autopwm(data)) { 2542 if (a < 4) /* no auto point pwm */ 2543 return 0; 2544 if (a == 8) /* no auto_point4 */ 2545 return 0; 2546 } 2547 if (has_old_autopwm(data)) { 2548 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */ 2549 return 0; 2550 } 2551 2552 return attr->mode; 2553 } 2554 2555 static struct attribute *it87_attributes_auto_pwm[] = { 2556 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 2557 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, 2558 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr, 2559 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr, 2560 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr, 2561 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr, 2562 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr, 2563 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr, 2564 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr, 2565 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr, 2566 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr, 2567 2568 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */ 2569 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, 2570 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr, 2571 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr, 2572 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr, 2573 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr, 2574 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr, 2575 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr, 2576 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr, 2577 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr, 2578 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr, 2579 2580 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */ 2581 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, 2582 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr, 2583 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr, 2584 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr, 2585 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr, 2586 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr, 2587 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr, 2588 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr, 2589 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr, 2590 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr, 2591 2592 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */ 2593 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr, 2594 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr, 2595 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr, 2596 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr, 2597 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr, 2598 2599 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr, 2600 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr, 2601 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr, 2602 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr, 2603 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr, 2604 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr, 2605 2606 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr, 2607 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr, 2608 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr, 2609 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr, 2610 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr, 2611 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr, 2612 2613 NULL, 2614 }; 2615 2616 static const struct attribute_group it87_group_auto_pwm = { 2617 .attrs = it87_attributes_auto_pwm, 2618 .is_visible = it87_auto_pwm_is_visible, 2619 }; 2620 2621 /* SuperIO detection - will change isa_address if a chip is found */ 2622 static int __init it87_find(int sioaddr, unsigned short *address, 2623 struct it87_sio_data *sio_data, int chip_cnt) 2624 { 2625 int err; 2626 u16 chip_type; 2627 const struct it87_devices *config = NULL; 2628 2629 err = superio_enter(sioaddr); 2630 if (err) 2631 return err; 2632 2633 err = -ENODEV; 2634 chip_type = superio_inw(sioaddr, DEVID); 2635 /* check first for a valid chip before forcing chip id */ 2636 if (chip_type == 0xffff) 2637 goto exit; 2638 2639 if (force_id_cnt == 1) { 2640 /* If only one value given use for all chips */ 2641 if (force_id[0]) 2642 chip_type = force_id[0]; 2643 } else if (force_id[chip_cnt]) 2644 chip_type = force_id[chip_cnt]; 2645 2646 switch (chip_type) { 2647 case IT8705F_DEVID: 2648 sio_data->type = it87; 2649 break; 2650 case IT8712F_DEVID: 2651 sio_data->type = it8712; 2652 break; 2653 case IT8716F_DEVID: 2654 case IT8726F_DEVID: 2655 sio_data->type = it8716; 2656 break; 2657 case IT8718F_DEVID: 2658 sio_data->type = it8718; 2659 break; 2660 case IT8720F_DEVID: 2661 sio_data->type = it8720; 2662 break; 2663 case IT8721F_DEVID: 2664 sio_data->type = it8721; 2665 break; 2666 case IT8728F_DEVID: 2667 sio_data->type = it8728; 2668 break; 2669 case IT8732F_DEVID: 2670 sio_data->type = it8732; 2671 break; 2672 case IT8792E_DEVID: 2673 sio_data->type = it8792; 2674 break; 2675 case IT8771E_DEVID: 2676 sio_data->type = it8771; 2677 break; 2678 case IT8772E_DEVID: 2679 sio_data->type = it8772; 2680 break; 2681 case IT8781F_DEVID: 2682 sio_data->type = it8781; 2683 break; 2684 case IT8782F_DEVID: 2685 sio_data->type = it8782; 2686 break; 2687 case IT8783E_DEVID: 2688 sio_data->type = it8783; 2689 break; 2690 case IT8786E_DEVID: 2691 sio_data->type = it8786; 2692 break; 2693 case IT8790E_DEVID: 2694 sio_data->type = it8790; 2695 break; 2696 case IT8603E_DEVID: 2697 case IT8623E_DEVID: 2698 sio_data->type = it8603; 2699 break; 2700 case IT8620E_DEVID: 2701 sio_data->type = it8620; 2702 break; 2703 case IT8622E_DEVID: 2704 sio_data->type = it8622; 2705 break; 2706 case IT8628E_DEVID: 2707 sio_data->type = it8628; 2708 break; 2709 case IT87952E_DEVID: 2710 sio_data->type = it87952; 2711 break; 2712 case 0xffff: /* No device at all */ 2713 goto exit; 2714 default: 2715 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type); 2716 goto exit; 2717 } 2718 2719 config = &it87_devices[sio_data->type]; 2720 2721 superio_select(sioaddr, PME); 2722 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) { 2723 pr_info("Device (chip %s ioreg 0x%x) not activated, skipping\n", 2724 config->model, sioaddr); 2725 goto exit; 2726 } 2727 2728 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1); 2729 if (*address == 0) { 2730 pr_info("Base address not set (chip %s ioreg 0x%x), skipping\n", 2731 config->model, sioaddr); 2732 goto exit; 2733 } 2734 2735 err = 0; 2736 sio_data->sioaddr = sioaddr; 2737 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f; 2738 pr_info("Found %s chip at 0x%x, revision %d\n", 2739 it87_devices[sio_data->type].model, 2740 *address, sio_data->revision); 2741 2742 /* in7 (VSB or VCCH5V) is always internal on some chips */ 2743 if (has_in7_internal(config)) 2744 sio_data->internal |= BIT(1); 2745 2746 /* in8 (Vbat) is always internal */ 2747 sio_data->internal |= BIT(2); 2748 2749 /* in9 (AVCC3), always internal if supported */ 2750 if (has_avcc3(config)) 2751 sio_data->internal |= BIT(3); /* in9 is AVCC */ 2752 else 2753 sio_data->skip_in |= BIT(9); 2754 2755 if (!has_four_pwm(config)) 2756 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5); 2757 else if (!has_five_pwm(config)) 2758 sio_data->skip_pwm |= BIT(4) | BIT(5); 2759 else if (!has_six_pwm(config)) 2760 sio_data->skip_pwm |= BIT(5); 2761 2762 if (!has_vid(config)) 2763 sio_data->skip_vid = 1; 2764 2765 /* Read GPIO config and VID value from LDN 7 (GPIO) */ 2766 if (sio_data->type == it87) { 2767 /* The IT8705F has a different LD number for GPIO */ 2768 superio_select(sioaddr, 5); 2769 sio_data->beep_pin = superio_inb(sioaddr, 2770 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2771 } else if (sio_data->type == it8783) { 2772 int reg25, reg27, reg2a, reg2c, regef; 2773 2774 superio_select(sioaddr, GPIO); 2775 2776 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 2777 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2778 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG); 2779 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 2780 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG); 2781 2782 /* Check if fan3 is there or not */ 2783 if ((reg27 & BIT(0)) || !(reg2c & BIT(2))) 2784 sio_data->skip_fan |= BIT(2); 2785 if ((reg25 & BIT(4)) || 2786 (!(reg2a & BIT(1)) && (regef & BIT(0)))) 2787 sio_data->skip_pwm |= BIT(2); 2788 2789 /* Check if fan2 is there or not */ 2790 if (reg27 & BIT(7)) 2791 sio_data->skip_fan |= BIT(1); 2792 if (reg27 & BIT(3)) 2793 sio_data->skip_pwm |= BIT(1); 2794 2795 /* VIN5 */ 2796 if ((reg27 & BIT(0)) || (reg2c & BIT(2))) 2797 sio_data->skip_in |= BIT(5); /* No VIN5 */ 2798 2799 /* VIN6 */ 2800 if (reg27 & BIT(1)) 2801 sio_data->skip_in |= BIT(6); /* No VIN6 */ 2802 2803 /* 2804 * VIN7 2805 * Does not depend on bit 2 of Reg2C, contrary to datasheet. 2806 */ 2807 if (reg27 & BIT(2)) { 2808 /* 2809 * The data sheet is a bit unclear regarding the 2810 * internal voltage divider for VCCH5V. It says 2811 * "This bit enables and switches VIN7 (pin 91) to the 2812 * internal voltage divider for VCCH5V". 2813 * This is different to other chips, where the internal 2814 * voltage divider would connect VIN7 to an internal 2815 * voltage source. Maybe that is the case here as well. 2816 * 2817 * Since we don't know for sure, re-route it if that is 2818 * not the case, and ask the user to report if the 2819 * resulting voltage is sane. 2820 */ 2821 if (!(reg2c & BIT(1))) { 2822 reg2c |= BIT(1); 2823 superio_outb(sioaddr, IT87_SIO_PINX2_REG, 2824 reg2c); 2825 sio_data->need_in7_reroute = true; 2826 pr_notice("Routing internal VCCH5V to in7.\n"); 2827 } 2828 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n"); 2829 pr_notice("Please report if it displays a reasonable voltage.\n"); 2830 } 2831 2832 if (reg2c & BIT(0)) 2833 sio_data->internal |= BIT(0); 2834 if (reg2c & BIT(1)) 2835 sio_data->internal |= BIT(1); 2836 2837 sio_data->beep_pin = superio_inb(sioaddr, 2838 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2839 } else if (sio_data->type == it8603) { 2840 int reg27, reg29; 2841 2842 superio_select(sioaddr, GPIO); 2843 2844 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2845 2846 /* Check if fan3 is there or not */ 2847 if (reg27 & BIT(6)) 2848 sio_data->skip_pwm |= BIT(2); 2849 if (reg27 & BIT(7)) 2850 sio_data->skip_fan |= BIT(2); 2851 2852 /* Check if fan2 is there or not */ 2853 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2854 if (reg29 & BIT(1)) 2855 sio_data->skip_pwm |= BIT(1); 2856 if (reg29 & BIT(2)) 2857 sio_data->skip_fan |= BIT(1); 2858 2859 sio_data->skip_in |= BIT(5); /* No VIN5 */ 2860 sio_data->skip_in |= BIT(6); /* No VIN6 */ 2861 2862 sio_data->beep_pin = superio_inb(sioaddr, 2863 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2864 } else if (sio_data->type == it8620 || sio_data->type == it8628) { 2865 int reg; 2866 2867 superio_select(sioaddr, GPIO); 2868 2869 /* Check for pwm5 */ 2870 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 2871 if (reg & BIT(6)) 2872 sio_data->skip_pwm |= BIT(4); 2873 2874 /* Check for fan4, fan5 */ 2875 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); 2876 if (!(reg & BIT(5))) 2877 sio_data->skip_fan |= BIT(3); 2878 if (!(reg & BIT(4))) 2879 sio_data->skip_fan |= BIT(4); 2880 2881 /* Check for pwm3, fan3 */ 2882 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2883 if (reg & BIT(6)) 2884 sio_data->skip_pwm |= BIT(2); 2885 if (reg & BIT(7)) 2886 sio_data->skip_fan |= BIT(2); 2887 2888 /* Check for pwm4 */ 2889 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG); 2890 if (reg & BIT(2)) 2891 sio_data->skip_pwm |= BIT(3); 2892 2893 /* Check for pwm2, fan2 */ 2894 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2895 if (reg & BIT(1)) 2896 sio_data->skip_pwm |= BIT(1); 2897 if (reg & BIT(2)) 2898 sio_data->skip_fan |= BIT(1); 2899 /* Check for pwm6, fan6 */ 2900 if (!(reg & BIT(7))) { 2901 sio_data->skip_pwm |= BIT(5); 2902 sio_data->skip_fan |= BIT(5); 2903 } 2904 2905 /* Check if AVCC is on VIN3 */ 2906 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 2907 if (reg & BIT(0)) 2908 sio_data->internal |= BIT(0); 2909 else 2910 sio_data->skip_in |= BIT(9); 2911 2912 sio_data->beep_pin = superio_inb(sioaddr, 2913 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2914 } else if (sio_data->type == it8622) { 2915 int reg; 2916 2917 superio_select(sioaddr, GPIO); 2918 2919 /* Check for pwm4, fan4 */ 2920 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 2921 if (reg & BIT(6)) 2922 sio_data->skip_fan |= BIT(3); 2923 if (reg & BIT(5)) 2924 sio_data->skip_pwm |= BIT(3); 2925 2926 /* Check for pwm3, fan3, pwm5, fan5 */ 2927 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2928 if (reg & BIT(6)) 2929 sio_data->skip_pwm |= BIT(2); 2930 if (reg & BIT(7)) 2931 sio_data->skip_fan |= BIT(2); 2932 if (reg & BIT(3)) 2933 sio_data->skip_pwm |= BIT(4); 2934 if (reg & BIT(1)) 2935 sio_data->skip_fan |= BIT(4); 2936 2937 /* Check for pwm2, fan2 */ 2938 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2939 if (reg & BIT(1)) 2940 sio_data->skip_pwm |= BIT(1); 2941 if (reg & BIT(2)) 2942 sio_data->skip_fan |= BIT(1); 2943 2944 /* Check for AVCC */ 2945 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 2946 if (!(reg & BIT(0))) 2947 sio_data->skip_in |= BIT(9); 2948 2949 sio_data->beep_pin = superio_inb(sioaddr, 2950 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2951 } else if (sio_data->type == it8732) { 2952 int reg; 2953 2954 superio_select(sioaddr, GPIO); 2955 2956 /* Check for pwm2, fan2 */ 2957 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2958 if (reg & BIT(1)) 2959 sio_data->skip_pwm |= BIT(1); 2960 if (reg & BIT(2)) 2961 sio_data->skip_fan |= BIT(1); 2962 2963 /* Check for pwm3, fan3, fan4 */ 2964 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2965 if (reg & BIT(6)) 2966 sio_data->skip_pwm |= BIT(2); 2967 if (reg & BIT(7)) 2968 sio_data->skip_fan |= BIT(2); 2969 if (reg & BIT(5)) 2970 sio_data->skip_fan |= BIT(3); 2971 2972 /* Check if AVCC is on VIN3 */ 2973 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 2974 if (reg & BIT(0)) 2975 sio_data->internal |= BIT(0); 2976 2977 sio_data->beep_pin = superio_inb(sioaddr, 2978 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2979 } else { 2980 int reg; 2981 bool uart6; 2982 2983 superio_select(sioaddr, GPIO); 2984 2985 /* Check for fan4, fan5 */ 2986 if (has_five_fans(config)) { 2987 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); 2988 switch (sio_data->type) { 2989 case it8718: 2990 if (reg & BIT(5)) 2991 sio_data->skip_fan |= BIT(3); 2992 if (reg & BIT(4)) 2993 sio_data->skip_fan |= BIT(4); 2994 break; 2995 case it8720: 2996 case it8721: 2997 case it8728: 2998 if (!(reg & BIT(5))) 2999 sio_data->skip_fan |= BIT(3); 3000 if (!(reg & BIT(4))) 3001 sio_data->skip_fan |= BIT(4); 3002 break; 3003 default: 3004 break; 3005 } 3006 } 3007 3008 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 3009 if (!sio_data->skip_vid) { 3010 /* We need at least 4 VID pins */ 3011 if (reg & 0x0f) { 3012 pr_info("VID is disabled (pins used for GPIO)\n"); 3013 sio_data->skip_vid = 1; 3014 } 3015 } 3016 3017 /* Check if fan3 is there or not */ 3018 if (reg & BIT(6)) 3019 sio_data->skip_pwm |= BIT(2); 3020 if (reg & BIT(7)) 3021 sio_data->skip_fan |= BIT(2); 3022 3023 /* Check if fan2 is there or not */ 3024 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 3025 if (reg & BIT(1)) 3026 sio_data->skip_pwm |= BIT(1); 3027 if (reg & BIT(2)) 3028 sio_data->skip_fan |= BIT(1); 3029 3030 if ((sio_data->type == it8718 || sio_data->type == it8720) && 3031 !(sio_data->skip_vid)) 3032 sio_data->vid_value = superio_inb(sioaddr, 3033 IT87_SIO_VID_REG); 3034 3035 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 3036 3037 uart6 = sio_data->type == it8782 && (reg & BIT(2)); 3038 3039 /* 3040 * The IT8720F has no VIN7 pin, so VCCH5V should always be 3041 * routed internally to VIN7 with an internal divider. 3042 * Curiously, there still is a configuration bit to control 3043 * this, which means it can be set incorrectly. And even 3044 * more curiously, many boards out there are improperly 3045 * configured, even though the IT8720F datasheet claims 3046 * that the internal routing of VCCH5V to VIN7 is the default 3047 * setting. So we force the internal routing in this case. 3048 * 3049 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins. 3050 * If UART6 is enabled, re-route VIN7 to the internal divider 3051 * if that is not already the case. 3052 */ 3053 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) { 3054 reg |= BIT(1); 3055 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg); 3056 sio_data->need_in7_reroute = true; 3057 pr_notice("Routing internal VCCH5V to in7\n"); 3058 } 3059 if (reg & BIT(0)) 3060 sio_data->internal |= BIT(0); 3061 if (reg & BIT(1)) 3062 sio_data->internal |= BIT(1); 3063 3064 /* 3065 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7. 3066 * While VIN7 can be routed to the internal voltage divider, 3067 * VIN5 and VIN6 are not available if UART6 is enabled. 3068 * 3069 * Also, temp3 is not available if UART6 is enabled and TEMPIN3 3070 * is the temperature source. Since we can not read the 3071 * temperature source here, skip_temp is preliminary. 3072 */ 3073 if (uart6) { 3074 sio_data->skip_in |= BIT(5) | BIT(6); 3075 sio_data->skip_temp |= BIT(2); 3076 } 3077 3078 sio_data->beep_pin = superio_inb(sioaddr, 3079 IT87_SIO_BEEP_PIN_REG) & 0x3f; 3080 } 3081 if (sio_data->beep_pin) 3082 pr_info("Beeping is supported\n"); 3083 3084 /* Set values based on DMI matches */ 3085 if (dmi_data) 3086 sio_data->skip_pwm |= dmi_data->skip_pwm; 3087 3088 if (config->smbus_bitmap) { 3089 u8 reg; 3090 3091 superio_select(sioaddr, PME); 3092 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG); 3093 sio_data->ec_special_config = reg; 3094 sio_data->smbus_bitmap = reg & config->smbus_bitmap; 3095 } 3096 3097 exit: 3098 superio_exit(sioaddr, config ? has_conf_noexit(config) : false); 3099 return err; 3100 } 3101 3102 /* 3103 * Some chips seem to have default value 0xff for all limit 3104 * registers. For low voltage limits it makes no sense and triggers 3105 * alarms, so change to 0 instead. For high temperature limits, it 3106 * means -1 degree C, which surprisingly doesn't trigger an alarm, 3107 * but is still confusing, so change to 127 degrees C. 3108 */ 3109 static void it87_check_limit_regs(struct it87_data *data) 3110 { 3111 int i, reg; 3112 3113 for (i = 0; i < NUM_VIN_LIMIT; i++) { 3114 reg = it87_read_value(data, IT87_REG_VIN_MIN(i)); 3115 if (reg == 0xff) 3116 it87_write_value(data, IT87_REG_VIN_MIN(i), 0); 3117 } 3118 for (i = 0; i < NUM_TEMP_LIMIT; i++) { 3119 reg = it87_read_value(data, IT87_REG_TEMP_HIGH(i)); 3120 if (reg == 0xff) 3121 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127); 3122 } 3123 } 3124 3125 /* Check if voltage monitors are reset manually or by some reason */ 3126 static void it87_check_voltage_monitors_reset(struct it87_data *data) 3127 { 3128 int reg; 3129 3130 reg = it87_read_value(data, IT87_REG_VIN_ENABLE); 3131 if ((reg & 0xff) == 0) { 3132 /* Enable all voltage monitors */ 3133 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff); 3134 } 3135 } 3136 3137 /* Check if tachometers are reset manually or by some reason */ 3138 static void it87_check_tachometers_reset(struct platform_device *pdev) 3139 { 3140 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); 3141 struct it87_data *data = platform_get_drvdata(pdev); 3142 u8 mask, fan_main_ctrl; 3143 3144 mask = 0x70 & ~(sio_data->skip_fan << 4); 3145 fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); 3146 if ((fan_main_ctrl & mask) == 0) { 3147 /* Enable all fan tachometers */ 3148 fan_main_ctrl |= mask; 3149 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 3150 fan_main_ctrl); 3151 } 3152 } 3153 3154 /* Set tachometers to 16-bit mode if needed */ 3155 static void it87_check_tachometers_16bit_mode(struct platform_device *pdev) 3156 { 3157 struct it87_data *data = platform_get_drvdata(pdev); 3158 int reg; 3159 3160 if (!has_fan16_config(data)) 3161 return; 3162 3163 reg = it87_read_value(data, IT87_REG_FAN_16BIT); 3164 if (~reg & 0x07 & data->has_fan) { 3165 dev_dbg(&pdev->dev, 3166 "Setting fan1-3 to 16-bit mode\n"); 3167 it87_write_value(data, IT87_REG_FAN_16BIT, 3168 reg | 0x07); 3169 } 3170 } 3171 3172 static void it87_start_monitoring(struct it87_data *data) 3173 { 3174 it87_write_value(data, IT87_REG_CONFIG, 3175 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e) 3176 | (update_vbat ? 0x41 : 0x01)); 3177 } 3178 3179 /* Called when we have found a new IT87. */ 3180 static void it87_init_device(struct platform_device *pdev) 3181 { 3182 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); 3183 struct it87_data *data = platform_get_drvdata(pdev); 3184 int tmp, i; 3185 3186 /* 3187 * For each PWM channel: 3188 * - If it is in automatic mode, setting to manual mode should set 3189 * the fan to full speed by default. 3190 * - If it is in manual mode, we need a mapping to temperature 3191 * channels to use when later setting to automatic mode later. 3192 * Use a 1:1 mapping by default (we are clueless.) 3193 * In both cases, the value can (and should) be changed by the user 3194 * prior to switching to a different mode. 3195 * Note that this is no longer needed for the IT8721F and later, as 3196 * these have separate registers for the temperature mapping and the 3197 * manual duty cycle. 3198 */ 3199 for (i = 0; i < NUM_AUTO_PWM; i++) { 3200 data->pwm_temp_map[i] = i; 3201 data->pwm_duty[i] = 0x7f; /* Full speed */ 3202 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */ 3203 } 3204 3205 it87_check_limit_regs(data); 3206 3207 /* 3208 * Temperature channels are not forcibly enabled, as they can be 3209 * set to two different sensor types and we can't guess which one 3210 * is correct for a given system. These channels can be enabled at 3211 * run-time through the temp{1-3}_type sysfs accessors if needed. 3212 */ 3213 3214 it87_check_voltage_monitors_reset(data); 3215 3216 it87_check_tachometers_reset(pdev); 3217 3218 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); 3219 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07; 3220 3221 it87_check_tachometers_16bit_mode(pdev); 3222 3223 /* Check for additional fans */ 3224 tmp = it87_read_value(data, IT87_REG_FAN_16BIT); 3225 3226 if (has_four_fans(data) && (tmp & BIT(4))) 3227 data->has_fan |= BIT(3); /* fan4 enabled */ 3228 if (has_five_fans(data) && (tmp & BIT(5))) 3229 data->has_fan |= BIT(4); /* fan5 enabled */ 3230 if (has_six_fans(data) && (tmp & BIT(2))) 3231 data->has_fan |= BIT(5); /* fan6 enabled */ 3232 3233 /* Fan input pins may be used for alternative functions */ 3234 data->has_fan &= ~sio_data->skip_fan; 3235 3236 /* Check if pwm5, pwm6 are enabled */ 3237 if (has_six_pwm(data)) { 3238 /* The following code may be IT8620E specific */ 3239 tmp = it87_read_value(data, IT87_REG_FAN_DIV); 3240 if ((tmp & 0xc0) == 0xc0) 3241 sio_data->skip_pwm |= BIT(4); 3242 if (!(tmp & BIT(3))) 3243 sio_data->skip_pwm |= BIT(5); 3244 } 3245 3246 it87_start_monitoring(data); 3247 } 3248 3249 /* Return 1 if and only if the PWM interface is safe to use */ 3250 static int it87_check_pwm(struct device *dev) 3251 { 3252 struct it87_data *data = dev_get_drvdata(dev); 3253 /* 3254 * Some BIOSes fail to correctly configure the IT87 fans. All fans off 3255 * and polarity set to active low is sign that this is the case so we 3256 * disable pwm control to protect the user. 3257 */ 3258 int tmp = it87_read_value(data, IT87_REG_FAN_CTL); 3259 3260 if ((tmp & 0x87) == 0) { 3261 if (fix_pwm_polarity) { 3262 /* 3263 * The user asks us to attempt a chip reconfiguration. 3264 * This means switching to active high polarity and 3265 * inverting all fan speed values. 3266 */ 3267 int i; 3268 u8 pwm[3]; 3269 3270 for (i = 0; i < ARRAY_SIZE(pwm); i++) 3271 pwm[i] = it87_read_value(data, 3272 IT87_REG_PWM[i]); 3273 3274 /* 3275 * If any fan is in automatic pwm mode, the polarity 3276 * might be correct, as suspicious as it seems, so we 3277 * better don't change anything (but still disable the 3278 * PWM interface). 3279 */ 3280 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) { 3281 dev_info(dev, 3282 "Reconfiguring PWM to active high polarity\n"); 3283 it87_write_value(data, IT87_REG_FAN_CTL, 3284 tmp | 0x87); 3285 for (i = 0; i < 3; i++) 3286 it87_write_value(data, 3287 IT87_REG_PWM[i], 3288 0x7f & ~pwm[i]); 3289 return 1; 3290 } 3291 3292 dev_info(dev, 3293 "PWM configuration is too broken to be fixed\n"); 3294 } 3295 3296 return 0; 3297 } else if (fix_pwm_polarity) { 3298 dev_info(dev, 3299 "PWM configuration looks sane, won't touch\n"); 3300 } 3301 3302 return 1; 3303 } 3304 3305 static int it87_probe(struct platform_device *pdev) 3306 { 3307 struct it87_data *data; 3308 struct resource *res; 3309 struct device *dev = &pdev->dev; 3310 struct it87_sio_data *sio_data = dev_get_platdata(dev); 3311 int enable_pwm_interface; 3312 struct device *hwmon_dev; 3313 int err; 3314 3315 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 3316 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT, 3317 DRVNAME)) { 3318 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n", 3319 (unsigned long)res->start, 3320 (unsigned long)(res->start + IT87_EC_EXTENT - 1)); 3321 return -EBUSY; 3322 } 3323 3324 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL); 3325 if (!data) 3326 return -ENOMEM; 3327 3328 data->addr = res->start; 3329 data->sioaddr = sio_data->sioaddr; 3330 data->type = sio_data->type; 3331 data->smbus_bitmap = sio_data->smbus_bitmap; 3332 data->ec_special_config = sio_data->ec_special_config; 3333 data->features = it87_devices[sio_data->type].features; 3334 data->peci_mask = it87_devices[sio_data->type].peci_mask; 3335 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask; 3336 /* 3337 * IT8705F Datasheet 0.4.1, 3h == Version G. 3338 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J. 3339 * These are the first revisions with 16-bit tachometer support. 3340 */ 3341 switch (data->type) { 3342 case it87: 3343 if (sio_data->revision >= 0x03) { 3344 data->features &= ~FEAT_OLD_AUTOPWM; 3345 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS; 3346 } 3347 break; 3348 case it8712: 3349 if (sio_data->revision >= 0x08) { 3350 data->features &= ~FEAT_OLD_AUTOPWM; 3351 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS | 3352 FEAT_FIVE_FANS; 3353 } 3354 break; 3355 default: 3356 break; 3357 } 3358 3359 platform_set_drvdata(pdev, data); 3360 3361 mutex_init(&data->update_lock); 3362 3363 err = smbus_disable(data); 3364 if (err) 3365 return err; 3366 3367 /* Now, we do the remaining detection. */ 3368 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) || 3369 it87_read_value(data, IT87_REG_CHIPID) != 0x90) { 3370 smbus_enable(data); 3371 return -ENODEV; 3372 } 3373 3374 /* Check PWM configuration */ 3375 enable_pwm_interface = it87_check_pwm(dev); 3376 if (!enable_pwm_interface) 3377 dev_info(dev, 3378 "Detected broken BIOS defaults, disabling PWM interface\n"); 3379 3380 /* Starting with IT8721F, we handle scaling of internal voltages */ 3381 if (has_scaling(data)) { 3382 if (sio_data->internal & BIT(0)) 3383 data->in_scaled |= BIT(3); /* in3 is AVCC */ 3384 if (sio_data->internal & BIT(1)) 3385 data->in_scaled |= BIT(7); /* in7 is VSB */ 3386 if (sio_data->internal & BIT(2)) 3387 data->in_scaled |= BIT(8); /* in8 is Vbat */ 3388 if (sio_data->internal & BIT(3)) 3389 data->in_scaled |= BIT(9); /* in9 is AVCC */ 3390 } else if (sio_data->type == it8781 || sio_data->type == it8782 || 3391 sio_data->type == it8783) { 3392 if (sio_data->internal & BIT(0)) 3393 data->in_scaled |= BIT(3); /* in3 is VCC5V */ 3394 if (sio_data->internal & BIT(1)) 3395 data->in_scaled |= BIT(7); /* in7 is VCCH5V */ 3396 } 3397 3398 data->has_temp = 0x07; 3399 if (sio_data->skip_temp & BIT(2)) { 3400 if (sio_data->type == it8782 && 3401 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80)) 3402 data->has_temp &= ~BIT(2); 3403 } 3404 3405 data->in_internal = sio_data->internal; 3406 data->need_in7_reroute = sio_data->need_in7_reroute; 3407 data->has_in = 0x3ff & ~sio_data->skip_in; 3408 3409 if (has_four_temp(data)) { 3410 data->has_temp |= BIT(3); 3411 } else if (has_six_temp(data)) { 3412 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE); 3413 3414 /* Check for additional temperature sensors */ 3415 if ((reg & 0x03) >= 0x02) 3416 data->has_temp |= BIT(3); 3417 if (((reg >> 2) & 0x03) >= 0x02) 3418 data->has_temp |= BIT(4); 3419 if (((reg >> 4) & 0x03) >= 0x02) 3420 data->has_temp |= BIT(5); 3421 3422 /* Check for additional voltage sensors */ 3423 if ((reg & 0x03) == 0x01) 3424 data->has_in |= BIT(10); 3425 if (((reg >> 2) & 0x03) == 0x01) 3426 data->has_in |= BIT(11); 3427 if (((reg >> 4) & 0x03) == 0x01) 3428 data->has_in |= BIT(12); 3429 } 3430 3431 data->has_beep = !!sio_data->beep_pin; 3432 3433 /* Initialize the IT87 chip */ 3434 it87_init_device(pdev); 3435 3436 smbus_enable(data); 3437 3438 if (!sio_data->skip_vid) { 3439 data->has_vid = true; 3440 data->vrm = vid_which_vrm(); 3441 /* VID reading from Super-I/O config space if available */ 3442 data->vid = sio_data->vid_value; 3443 } 3444 3445 /* Prepare for sysfs hooks */ 3446 data->groups[0] = &it87_group; 3447 data->groups[1] = &it87_group_in; 3448 data->groups[2] = &it87_group_temp; 3449 data->groups[3] = &it87_group_fan; 3450 3451 if (enable_pwm_interface) { 3452 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1; 3453 data->has_pwm &= ~sio_data->skip_pwm; 3454 3455 data->groups[4] = &it87_group_pwm; 3456 if (has_old_autopwm(data) || has_newer_autopwm(data)) 3457 data->groups[5] = &it87_group_auto_pwm; 3458 } 3459 3460 hwmon_dev = devm_hwmon_device_register_with_groups(dev, 3461 it87_devices[sio_data->type].name, 3462 data, data->groups); 3463 return PTR_ERR_OR_ZERO(hwmon_dev); 3464 } 3465 3466 static void it87_resume_sio(struct platform_device *pdev) 3467 { 3468 struct it87_data *data = dev_get_drvdata(&pdev->dev); 3469 int err; 3470 int reg2c; 3471 3472 if (!data->need_in7_reroute) 3473 return; 3474 3475 err = superio_enter(data->sioaddr); 3476 if (err) { 3477 dev_warn(&pdev->dev, 3478 "Unable to enter Super I/O to reroute in7 (%d)", 3479 err); 3480 return; 3481 } 3482 3483 superio_select(data->sioaddr, GPIO); 3484 3485 reg2c = superio_inb(data->sioaddr, IT87_SIO_PINX2_REG); 3486 if (!(reg2c & BIT(1))) { 3487 dev_dbg(&pdev->dev, 3488 "Routing internal VCCH5V to in7 again"); 3489 3490 reg2c |= BIT(1); 3491 superio_outb(data->sioaddr, IT87_SIO_PINX2_REG, 3492 reg2c); 3493 } 3494 3495 superio_exit(data->sioaddr, has_conf_noexit(data)); 3496 } 3497 3498 static int it87_resume(struct device *dev) 3499 { 3500 struct platform_device *pdev = to_platform_device(dev); 3501 struct it87_data *data = dev_get_drvdata(dev); 3502 3503 it87_resume_sio(pdev); 3504 3505 it87_lock(data); 3506 3507 it87_check_pwm(dev); 3508 it87_check_limit_regs(data); 3509 it87_check_voltage_monitors_reset(data); 3510 it87_check_tachometers_reset(pdev); 3511 it87_check_tachometers_16bit_mode(pdev); 3512 3513 it87_start_monitoring(data); 3514 3515 /* force update */ 3516 data->valid = false; 3517 3518 it87_unlock(data); 3519 3520 it87_update_device(dev); 3521 3522 return 0; 3523 } 3524 3525 static DEFINE_SIMPLE_DEV_PM_OPS(it87_dev_pm_ops, NULL, it87_resume); 3526 3527 static struct platform_driver it87_driver = { 3528 .driver = { 3529 .name = DRVNAME, 3530 .pm = pm_sleep_ptr(&it87_dev_pm_ops), 3531 }, 3532 .probe = it87_probe, 3533 }; 3534 3535 static int __init it87_device_add(int index, unsigned short address, 3536 const struct it87_sio_data *sio_data) 3537 { 3538 struct platform_device *pdev; 3539 struct resource res = { 3540 .start = address + IT87_EC_OFFSET, 3541 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1, 3542 .name = DRVNAME, 3543 .flags = IORESOURCE_IO, 3544 }; 3545 int err; 3546 3547 err = acpi_check_resource_conflict(&res); 3548 if (err) { 3549 if (!ignore_resource_conflict) 3550 return err; 3551 } 3552 3553 pdev = platform_device_alloc(DRVNAME, address); 3554 if (!pdev) 3555 return -ENOMEM; 3556 3557 err = platform_device_add_resources(pdev, &res, 1); 3558 if (err) { 3559 pr_err("Device resource addition failed (%d)\n", err); 3560 goto exit_device_put; 3561 } 3562 3563 err = platform_device_add_data(pdev, sio_data, 3564 sizeof(struct it87_sio_data)); 3565 if (err) { 3566 pr_err("Platform data allocation failed\n"); 3567 goto exit_device_put; 3568 } 3569 3570 err = platform_device_add(pdev); 3571 if (err) { 3572 pr_err("Device addition failed (%d)\n", err); 3573 goto exit_device_put; 3574 } 3575 3576 it87_pdev[index] = pdev; 3577 return 0; 3578 3579 exit_device_put: 3580 platform_device_put(pdev); 3581 return err; 3582 } 3583 3584 /* callback function for DMI */ 3585 static int it87_dmi_cb(const struct dmi_system_id *dmi_entry) 3586 { 3587 dmi_data = dmi_entry->driver_data; 3588 3589 if (dmi_data && dmi_data->skip_pwm) 3590 pr_info("Disabling pwm2 due to hardware constraints\n"); 3591 3592 return 1; 3593 } 3594 3595 /* 3596 * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip 3597 * (IT8792E) needs to be in configuration mode before accessing the first 3598 * due to a bug in IT8792E which otherwise results in LPC bus access errors. 3599 * This needs to be done before accessing the first Super-IO chip since 3600 * the second chip may have been accessed prior to loading this driver. 3601 * 3602 * The problem is also reported to affect IT8795E, which is used on X299 boards 3603 * and has the same chip ID as IT8792E (0x8733). It also appears to affect 3604 * systems with IT8790E, which is used on some Z97X-Gaming boards as well as 3605 * Z87X-OC. 3606 * DMI entries for those systems will be added as they become available and 3607 * as the problem is confirmed to affect those boards. 3608 */ 3609 static int it87_sio_force(const struct dmi_system_id *dmi_entry) 3610 { 3611 __superio_enter(REG_4E); 3612 3613 return it87_dmi_cb(dmi_entry); 3614 }; 3615 3616 /* 3617 * On the Shuttle SN68PT, FAN_CTL2 is apparently not 3618 * connected to a fan, but to something else. One user 3619 * has reported instant system power-off when changing 3620 * the PWM2 duty cycle, so we disable it. 3621 * I use the board name string as the trigger in case 3622 * the same board is ever used in other systems. 3623 */ 3624 static struct it87_dmi_data nvidia_fn68pt = { 3625 .skip_pwm = BIT(1), 3626 }; 3627 3628 #define IT87_DMI_MATCH_VND(vendor, name, cb, data) \ 3629 { \ 3630 .callback = cb, \ 3631 .matches = { \ 3632 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, vendor), \ 3633 DMI_EXACT_MATCH(DMI_BOARD_NAME, name), \ 3634 }, \ 3635 .driver_data = data, \ 3636 } 3637 3638 #define IT87_DMI_MATCH_GBT(name, cb, data) \ 3639 IT87_DMI_MATCH_VND("Gigabyte Technology Co., Ltd.", name, cb, data) 3640 3641 static const struct dmi_system_id it87_dmi_table[] __initconst = { 3642 IT87_DMI_MATCH_GBT("AB350", it87_sio_force, NULL), 3643 /* ? + IT8792E/IT8795E */ 3644 IT87_DMI_MATCH_GBT("AX370", it87_sio_force, NULL), 3645 /* ? + IT8792E/IT8795E */ 3646 IT87_DMI_MATCH_GBT("Z97X-Gaming G1", it87_sio_force, NULL), 3647 /* ? + IT8790E */ 3648 IT87_DMI_MATCH_GBT("TRX40 AORUS XTREME", it87_sio_force, NULL), 3649 /* IT8688E + IT8792E/IT8795E */ 3650 IT87_DMI_MATCH_GBT("Z390 AORUS ULTRA-CF", it87_sio_force, NULL), 3651 /* IT8688E + IT8792E/IT8795E */ 3652 IT87_DMI_MATCH_GBT("B550 AORUS PRO AC", it87_sio_force, NULL), 3653 /* IT8688E + IT8792E/IT8795E */ 3654 IT87_DMI_MATCH_GBT("X570 AORUS MASTER", it87_sio_force, NULL), 3655 /* IT8688E + IT8792E/IT8795E */ 3656 IT87_DMI_MATCH_GBT("X570 AORUS PRO", it87_sio_force, NULL), 3657 /* IT8688E + IT8792E/IT8795E */ 3658 IT87_DMI_MATCH_GBT("X570 AORUS PRO WIFI", it87_sio_force, NULL), 3659 /* IT8688E + IT8792E/IT8795E */ 3660 IT87_DMI_MATCH_GBT("X570S AERO G", it87_sio_force, NULL), 3661 /* IT8689E + IT87952E */ 3662 IT87_DMI_MATCH_GBT("Z690 AORUS PRO DDR4", it87_sio_force, NULL), 3663 /* IT8689E + IT87952E */ 3664 IT87_DMI_MATCH_GBT("Z690 AORUS PRO", it87_sio_force, NULL), 3665 /* IT8689E + IT87952E */ 3666 IT87_DMI_MATCH_VND("nVIDIA", "FN68PT", it87_dmi_cb, &nvidia_fn68pt), 3667 { } 3668 3669 }; 3670 MODULE_DEVICE_TABLE(dmi, it87_dmi_table); 3671 3672 static int __init sm_it87_init(void) 3673 { 3674 int sioaddr[2] = { REG_2E, REG_4E }; 3675 struct it87_sio_data sio_data; 3676 unsigned short isa_address[2]; 3677 bool found = false; 3678 int i, err; 3679 3680 err = platform_driver_register(&it87_driver); 3681 if (err) 3682 return err; 3683 3684 dmi_check_system(it87_dmi_table); 3685 3686 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) { 3687 memset(&sio_data, 0, sizeof(struct it87_sio_data)); 3688 isa_address[i] = 0; 3689 err = it87_find(sioaddr[i], &isa_address[i], &sio_data, i); 3690 if (err || isa_address[i] == 0) 3691 continue; 3692 /* 3693 * Don't register second chip if its ISA address matches 3694 * the first chip's ISA address. 3695 */ 3696 if (i && isa_address[i] == isa_address[0]) 3697 break; 3698 3699 err = it87_device_add(i, isa_address[i], &sio_data); 3700 if (err) 3701 goto exit_dev_unregister; 3702 3703 found = true; 3704 3705 /* 3706 * IT8705F may respond on both SIO addresses. 3707 * Stop probing after finding one. 3708 */ 3709 if (sio_data.type == it87) 3710 break; 3711 } 3712 3713 if (!found) { 3714 err = -ENODEV; 3715 goto exit_unregister; 3716 } 3717 return 0; 3718 3719 exit_dev_unregister: 3720 /* NULL check handled by platform_device_unregister */ 3721 platform_device_unregister(it87_pdev[0]); 3722 exit_unregister: 3723 platform_driver_unregister(&it87_driver); 3724 return err; 3725 } 3726 3727 static void __exit sm_it87_exit(void) 3728 { 3729 /* NULL check handled by platform_device_unregister */ 3730 platform_device_unregister(it87_pdev[1]); 3731 platform_device_unregister(it87_pdev[0]); 3732 platform_driver_unregister(&it87_driver); 3733 } 3734 3735 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>"); 3736 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver"); 3737 3738 module_param_array(force_id, ushort, &force_id_cnt, 0); 3739 MODULE_PARM_DESC(force_id, "Override one or more detected device ID(s)"); 3740 3741 module_param(ignore_resource_conflict, bool, 0); 3742 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict"); 3743 3744 module_param(update_vbat, bool, 0); 3745 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value"); 3746 3747 module_param(fix_pwm_polarity, bool, 0); 3748 MODULE_PARM_DESC(fix_pwm_polarity, 3749 "Force PWM polarity to active high (DANGEROUS)"); 3750 3751 MODULE_LICENSE("GPL"); 3752 3753 module_init(sm_it87_init); 3754 module_exit(sm_it87_exit); 3755