1 /* 2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware 3 * monitoring. 4 * 5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a 6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in 7 * addition to an Environment Controller (Enhanced Hardware Monitor and 8 * Fan Controller) 9 * 10 * This driver supports only the Environment Controller in the IT8705F and 11 * similar parts. The other devices are supported by different drivers. 12 * 13 * Supports: IT8603E Super I/O chip w/LPC interface 14 * IT8620E Super I/O chip w/LPC interface 15 * IT8623E Super I/O chip w/LPC interface 16 * IT8628E Super I/O chip w/LPC interface 17 * IT8705F Super I/O chip w/LPC interface 18 * IT8712F Super I/O chip w/LPC interface 19 * IT8716F Super I/O chip w/LPC interface 20 * IT8718F Super I/O chip w/LPC interface 21 * IT8720F Super I/O chip w/LPC interface 22 * IT8721F Super I/O chip w/LPC interface 23 * IT8726F Super I/O chip w/LPC interface 24 * IT8728F Super I/O chip w/LPC interface 25 * IT8732F Super I/O chip w/LPC interface 26 * IT8758E Super I/O chip w/LPC interface 27 * IT8771E Super I/O chip w/LPC interface 28 * IT8772E Super I/O chip w/LPC interface 29 * IT8781F Super I/O chip w/LPC interface 30 * IT8782F Super I/O chip w/LPC interface 31 * IT8783E/F Super I/O chip w/LPC interface 32 * IT8786E Super I/O chip w/LPC interface 33 * IT8790E Super I/O chip w/LPC interface 34 * Sis950 A clone of the IT8705F 35 * 36 * Copyright (C) 2001 Chris Gauthron 37 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de> 38 * 39 * This program is free software; you can redistribute it and/or modify 40 * it under the terms of the GNU General Public License as published by 41 * the Free Software Foundation; either version 2 of the License, or 42 * (at your option) any later version. 43 * 44 * This program is distributed in the hope that it will be useful, 45 * but WITHOUT ANY WARRANTY; without even the implied warranty of 46 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 47 * GNU General Public License for more details. 48 */ 49 50 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 51 52 #include <linux/bitops.h> 53 #include <linux/module.h> 54 #include <linux/init.h> 55 #include <linux/slab.h> 56 #include <linux/jiffies.h> 57 #include <linux/platform_device.h> 58 #include <linux/hwmon.h> 59 #include <linux/hwmon-sysfs.h> 60 #include <linux/hwmon-vid.h> 61 #include <linux/err.h> 62 #include <linux/mutex.h> 63 #include <linux/sysfs.h> 64 #include <linux/string.h> 65 #include <linux/dmi.h> 66 #include <linux/acpi.h> 67 #include <linux/io.h> 68 69 #define DRVNAME "it87" 70 71 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732, 72 it8771, it8772, it8781, it8782, it8783, it8786, it8790, it8603, 73 it8620, it8628 }; 74 75 static unsigned short force_id; 76 module_param(force_id, ushort, 0); 77 MODULE_PARM_DESC(force_id, "Override the detected device ID"); 78 79 static struct platform_device *it87_pdev[2]; 80 81 #define REG_2E 0x2e /* The register to read/write */ 82 #define REG_4E 0x4e /* Secondary register to read/write */ 83 84 #define DEV 0x07 /* Register: Logical device select */ 85 #define PME 0x04 /* The device with the fan registers in it */ 86 87 /* The device with the IT8718F/IT8720F VID value in it */ 88 #define GPIO 0x07 89 90 #define DEVID 0x20 /* Register: Device ID */ 91 #define DEVREV 0x22 /* Register: Device Revision */ 92 93 static inline int superio_inb(int ioreg, int reg) 94 { 95 outb(reg, ioreg); 96 return inb(ioreg + 1); 97 } 98 99 static inline void superio_outb(int ioreg, int reg, int val) 100 { 101 outb(reg, ioreg); 102 outb(val, ioreg + 1); 103 } 104 105 static int superio_inw(int ioreg, int reg) 106 { 107 int val; 108 109 outb(reg++, ioreg); 110 val = inb(ioreg + 1) << 8; 111 outb(reg, ioreg); 112 val |= inb(ioreg + 1); 113 return val; 114 } 115 116 static inline void superio_select(int ioreg, int ldn) 117 { 118 outb(DEV, ioreg); 119 outb(ldn, ioreg + 1); 120 } 121 122 static inline int superio_enter(int ioreg) 123 { 124 /* 125 * Try to reserve ioreg and ioreg + 1 for exclusive access. 126 */ 127 if (!request_muxed_region(ioreg, 2, DRVNAME)) 128 return -EBUSY; 129 130 outb(0x87, ioreg); 131 outb(0x01, ioreg); 132 outb(0x55, ioreg); 133 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg); 134 return 0; 135 } 136 137 static inline void superio_exit(int ioreg) 138 { 139 outb(0x02, ioreg); 140 outb(0x02, ioreg + 1); 141 release_region(ioreg, 2); 142 } 143 144 /* Logical device 4 registers */ 145 #define IT8712F_DEVID 0x8712 146 #define IT8705F_DEVID 0x8705 147 #define IT8716F_DEVID 0x8716 148 #define IT8718F_DEVID 0x8718 149 #define IT8720F_DEVID 0x8720 150 #define IT8721F_DEVID 0x8721 151 #define IT8726F_DEVID 0x8726 152 #define IT8728F_DEVID 0x8728 153 #define IT8732F_DEVID 0x8732 154 #define IT8771E_DEVID 0x8771 155 #define IT8772E_DEVID 0x8772 156 #define IT8781F_DEVID 0x8781 157 #define IT8782F_DEVID 0x8782 158 #define IT8783E_DEVID 0x8783 159 #define IT8786E_DEVID 0x8786 160 #define IT8790E_DEVID 0x8790 161 #define IT8603E_DEVID 0x8603 162 #define IT8620E_DEVID 0x8620 163 #define IT8623E_DEVID 0x8623 164 #define IT8628E_DEVID 0x8628 165 #define IT87_ACT_REG 0x30 166 #define IT87_BASE_REG 0x60 167 168 /* Logical device 7 registers (IT8712F and later) */ 169 #define IT87_SIO_GPIO1_REG 0x25 170 #define IT87_SIO_GPIO2_REG 0x26 171 #define IT87_SIO_GPIO3_REG 0x27 172 #define IT87_SIO_GPIO4_REG 0x28 173 #define IT87_SIO_GPIO5_REG 0x29 174 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */ 175 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */ 176 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */ 177 #define IT87_SIO_VID_REG 0xfc /* VID value */ 178 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */ 179 180 /* Update battery voltage after every reading if true */ 181 static bool update_vbat; 182 183 /* Not all BIOSes properly configure the PWM registers */ 184 static bool fix_pwm_polarity; 185 186 /* Many IT87 constants specified below */ 187 188 /* Length of ISA address segment */ 189 #define IT87_EXTENT 8 190 191 /* Length of ISA address segment for Environmental Controller */ 192 #define IT87_EC_EXTENT 2 193 194 /* Offset of EC registers from ISA base address */ 195 #define IT87_EC_OFFSET 5 196 197 /* Where are the ISA address/data registers relative to the EC base address */ 198 #define IT87_ADDR_REG_OFFSET 0 199 #define IT87_DATA_REG_OFFSET 1 200 201 /*----- The IT87 registers -----*/ 202 203 #define IT87_REG_CONFIG 0x00 204 205 #define IT87_REG_ALARM1 0x01 206 #define IT87_REG_ALARM2 0x02 207 #define IT87_REG_ALARM3 0x03 208 209 /* 210 * The IT8718F and IT8720F have the VID value in a different register, in 211 * Super-I/O configuration space. 212 */ 213 #define IT87_REG_VID 0x0a 214 /* 215 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b 216 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer 217 * mode. 218 */ 219 #define IT87_REG_FAN_DIV 0x0b 220 #define IT87_REG_FAN_16BIT 0x0c 221 222 /* 223 * Monitors: 224 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12) 225 * - up to 6 temp (1 to 6) 226 * - up to 6 fan (1 to 6) 227 */ 228 229 static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c }; 230 static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e }; 231 static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d }; 232 static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f }; 233 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 }; 234 235 #define IT87_REG_FAN_MAIN_CTRL 0x13 236 #define IT87_REG_FAN_CTL 0x14 237 static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf }; 238 static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab }; 239 240 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 241 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e }; 242 243 #define IT87_REG_TEMP(nr) (0x29 + (nr)) 244 245 #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2) 246 #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2) 247 #define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2) 248 #define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2) 249 250 #define IT87_REG_VIN_ENABLE 0x50 251 #define IT87_REG_TEMP_ENABLE 0x51 252 #define IT87_REG_TEMP_EXTRA 0x55 253 #define IT87_REG_BEEP_ENABLE 0x5c 254 255 #define IT87_REG_CHIPID 0x58 256 257 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 }; 258 259 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i)) 260 #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i)) 261 262 #define IT87_REG_TEMP456_ENABLE 0x77 263 264 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN) 265 #define NUM_VIN_LIMIT 8 266 #define NUM_TEMP 6 267 #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET) 268 #define NUM_TEMP_LIMIT 3 269 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN) 270 #define NUM_FAN_DIV 3 271 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM) 272 #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM) 273 274 struct it87_devices { 275 const char *name; 276 const char * const suffix; 277 u32 features; 278 u8 peci_mask; 279 u8 old_peci_mask; 280 }; 281 282 #define FEAT_12MV_ADC BIT(0) 283 #define FEAT_NEWER_AUTOPWM BIT(1) 284 #define FEAT_OLD_AUTOPWM BIT(2) 285 #define FEAT_16BIT_FANS BIT(3) 286 #define FEAT_TEMP_OFFSET BIT(4) 287 #define FEAT_TEMP_PECI BIT(5) 288 #define FEAT_TEMP_OLD_PECI BIT(6) 289 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */ 290 #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */ 291 #define FEAT_VID BIT(9) /* Set if chip supports VID */ 292 #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */ 293 #define FEAT_SIX_FANS BIT(11) /* Supports six fans */ 294 #define FEAT_10_9MV_ADC BIT(12) 295 #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */ 296 #define FEAT_SIX_PWM BIT(14) /* Chip supports 6 pwm chn */ 297 #define FEAT_PWM_FREQ2 BIT(15) /* Separate pwm freq 2 */ 298 #define FEAT_SIX_TEMP BIT(16) /* Up to 6 temp sensors */ 299 300 static const struct it87_devices it87_devices[] = { 301 [it87] = { 302 .name = "it87", 303 .suffix = "F", 304 .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */ 305 }, 306 [it8712] = { 307 .name = "it8712", 308 .suffix = "F", 309 .features = FEAT_OLD_AUTOPWM | FEAT_VID, 310 /* may need to overwrite */ 311 }, 312 [it8716] = { 313 .name = "it8716", 314 .suffix = "F", 315 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 316 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2, 317 }, 318 [it8718] = { 319 .name = "it8718", 320 .suffix = "F", 321 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 322 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS 323 | FEAT_PWM_FREQ2, 324 .old_peci_mask = 0x4, 325 }, 326 [it8720] = { 327 .name = "it8720", 328 .suffix = "F", 329 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 330 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS 331 | FEAT_PWM_FREQ2, 332 .old_peci_mask = 0x4, 333 }, 334 [it8721] = { 335 .name = "it8721", 336 .suffix = "F", 337 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 338 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 339 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL 340 | FEAT_PWM_FREQ2, 341 .peci_mask = 0x05, 342 .old_peci_mask = 0x02, /* Actually reports PCH */ 343 }, 344 [it8728] = { 345 .name = "it8728", 346 .suffix = "F", 347 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 348 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS 349 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2, 350 .peci_mask = 0x07, 351 }, 352 [it8732] = { 353 .name = "it8732", 354 .suffix = "F", 355 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 356 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 357 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL, 358 .peci_mask = 0x07, 359 .old_peci_mask = 0x02, /* Actually reports PCH */ 360 }, 361 [it8771] = { 362 .name = "it8771", 363 .suffix = "E", 364 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 365 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 366 | FEAT_PWM_FREQ2, 367 /* PECI: guesswork */ 368 /* 12mV ADC (OHM) */ 369 /* 16 bit fans (OHM) */ 370 /* three fans, always 16 bit (guesswork) */ 371 .peci_mask = 0x07, 372 }, 373 [it8772] = { 374 .name = "it8772", 375 .suffix = "E", 376 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 377 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 378 | FEAT_PWM_FREQ2, 379 /* PECI (coreboot) */ 380 /* 12mV ADC (HWSensors4, OHM) */ 381 /* 16 bit fans (HWSensors4, OHM) */ 382 /* three fans, always 16 bit (datasheet) */ 383 .peci_mask = 0x07, 384 }, 385 [it8781] = { 386 .name = "it8781", 387 .suffix = "F", 388 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 389 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, 390 .old_peci_mask = 0x4, 391 }, 392 [it8782] = { 393 .name = "it8782", 394 .suffix = "F", 395 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 396 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, 397 .old_peci_mask = 0x4, 398 }, 399 [it8783] = { 400 .name = "it8783", 401 .suffix = "E/F", 402 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 403 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2, 404 .old_peci_mask = 0x4, 405 }, 406 [it8786] = { 407 .name = "it8786", 408 .suffix = "E", 409 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 410 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 411 | FEAT_PWM_FREQ2, 412 .peci_mask = 0x07, 413 }, 414 [it8790] = { 415 .name = "it8790", 416 .suffix = "E", 417 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 418 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 419 | FEAT_PWM_FREQ2, 420 .peci_mask = 0x07, 421 }, 422 [it8603] = { 423 .name = "it8603", 424 .suffix = "E", 425 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 426 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 427 | FEAT_AVCC3 | FEAT_PWM_FREQ2, 428 .peci_mask = 0x07, 429 }, 430 [it8620] = { 431 .name = "it8620", 432 .suffix = "E", 433 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 434 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS 435 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 436 | FEAT_SIX_TEMP, 437 .peci_mask = 0x07, 438 }, 439 [it8628] = { 440 .name = "it8628", 441 .suffix = "E", 442 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 443 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS 444 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 445 | FEAT_SIX_TEMP, 446 .peci_mask = 0x07, 447 }, 448 }; 449 450 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS) 451 #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC) 452 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC) 453 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM) 454 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM) 455 #define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET) 456 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \ 457 ((data)->peci_mask & BIT(nr))) 458 #define has_temp_old_peci(data, nr) \ 459 (((data)->features & FEAT_TEMP_OLD_PECI) && \ 460 ((data)->old_peci_mask & BIT(nr))) 461 #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG) 462 #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \ 463 FEAT_SIX_FANS)) 464 #define has_vid(data) ((data)->features & FEAT_VID) 465 #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL) 466 #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS) 467 #define has_avcc3(data) ((data)->features & FEAT_AVCC3) 468 #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM) 469 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2) 470 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP) 471 472 struct it87_sio_data { 473 enum chips type; 474 /* Values read from Super-I/O config space */ 475 u8 revision; 476 u8 vid_value; 477 u8 beep_pin; 478 u8 internal; /* Internal sensors can be labeled */ 479 /* Features skipped based on config or DMI */ 480 u16 skip_in; 481 u8 skip_vid; 482 u8 skip_fan; 483 u8 skip_pwm; 484 u8 skip_temp; 485 }; 486 487 /* 488 * For each registered chip, we need to keep some data in memory. 489 * The structure is dynamically allocated. 490 */ 491 struct it87_data { 492 const struct attribute_group *groups[7]; 493 enum chips type; 494 u16 features; 495 u8 peci_mask; 496 u8 old_peci_mask; 497 498 unsigned short addr; 499 const char *name; 500 struct mutex update_lock; 501 char valid; /* !=0 if following fields are valid */ 502 unsigned long last_updated; /* In jiffies */ 503 504 u16 in_scaled; /* Internal voltage sensors are scaled */ 505 u16 in_internal; /* Bitfield, internal sensors (for labels) */ 506 u16 has_in; /* Bitfield, voltage sensors enabled */ 507 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */ 508 u8 has_fan; /* Bitfield, fans enabled */ 509 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */ 510 u8 has_temp; /* Bitfield, temp sensors enabled */ 511 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */ 512 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */ 513 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */ 514 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */ 515 bool has_vid; /* True if VID supported */ 516 u8 vid; /* Register encoding, combined */ 517 u8 vrm; 518 u32 alarms; /* Register encoding, combined */ 519 bool has_beep; /* true if beep supported */ 520 u8 beeps; /* Register encoding */ 521 u8 fan_main_ctrl; /* Register value */ 522 u8 fan_ctl; /* Register value */ 523 524 /* 525 * The following 3 arrays correspond to the same registers up to 526 * the IT8720F. The meaning of bits 6-0 depends on the value of bit 527 * 7, and we want to preserve settings on mode changes, so we have 528 * to track all values separately. 529 * Starting with the IT8721F, the manual PWM duty cycles are stored 530 * in separate registers (8-bit values), so the separate tracking 531 * is no longer needed, but it is still done to keep the driver 532 * simple. 533 */ 534 u8 has_pwm; /* Bitfield, pwm control enabled */ 535 u8 pwm_ctrl[NUM_PWM]; /* Register value */ 536 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */ 537 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */ 538 539 /* Automatic fan speed control registers */ 540 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */ 541 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */ 542 }; 543 544 static int adc_lsb(const struct it87_data *data, int nr) 545 { 546 int lsb; 547 548 if (has_12mv_adc(data)) 549 lsb = 120; 550 else if (has_10_9mv_adc(data)) 551 lsb = 109; 552 else 553 lsb = 160; 554 if (data->in_scaled & BIT(nr)) 555 lsb <<= 1; 556 return lsb; 557 } 558 559 static u8 in_to_reg(const struct it87_data *data, int nr, long val) 560 { 561 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr)); 562 return clamp_val(val, 0, 255); 563 } 564 565 static int in_from_reg(const struct it87_data *data, int nr, int val) 566 { 567 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10); 568 } 569 570 static inline u8 FAN_TO_REG(long rpm, int div) 571 { 572 if (rpm == 0) 573 return 255; 574 rpm = clamp_val(rpm, 1, 1000000); 575 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254); 576 } 577 578 static inline u16 FAN16_TO_REG(long rpm) 579 { 580 if (rpm == 0) 581 return 0xffff; 582 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe); 583 } 584 585 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \ 586 1350000 / ((val) * (div))) 587 /* The divider is fixed to 2 in 16-bit mode */ 588 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \ 589 1350000 / ((val) * 2)) 590 591 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \ 592 ((val) + 500) / 1000), -128, 127)) 593 #define TEMP_FROM_REG(val) ((val) * 1000) 594 595 static u8 pwm_to_reg(const struct it87_data *data, long val) 596 { 597 if (has_newer_autopwm(data)) 598 return val; 599 else 600 return val >> 1; 601 } 602 603 static int pwm_from_reg(const struct it87_data *data, u8 reg) 604 { 605 if (has_newer_autopwm(data)) 606 return reg; 607 else 608 return (reg & 0x7f) << 1; 609 } 610 611 static int DIV_TO_REG(int val) 612 { 613 int answer = 0; 614 615 while (answer < 7 && (val >>= 1)) 616 answer++; 617 return answer; 618 } 619 620 #define DIV_FROM_REG(val) BIT(val) 621 622 /* 623 * PWM base frequencies. The frequency has to be divided by either 128 or 256, 624 * depending on the chip type, to calculate the actual PWM frequency. 625 * 626 * Some of the chip datasheets suggest a base frequency of 51 kHz instead 627 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency 628 * of 200 Hz. Sometimes both PWM frequency select registers are affected, 629 * sometimes just one. It is unknown if this is a datasheet error or real, 630 * so this is ignored for now. 631 */ 632 static const unsigned int pwm_freq[8] = { 633 48000000, 634 24000000, 635 12000000, 636 8000000, 637 6000000, 638 3000000, 639 1500000, 640 750000, 641 }; 642 643 /* 644 * Must be called with data->update_lock held, except during initialization. 645 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, 646 * would slow down the IT87 access and should not be necessary. 647 */ 648 static int it87_read_value(struct it87_data *data, u8 reg) 649 { 650 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); 651 return inb_p(data->addr + IT87_DATA_REG_OFFSET); 652 } 653 654 /* 655 * Must be called with data->update_lock held, except during initialization. 656 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, 657 * would slow down the IT87 access and should not be necessary. 658 */ 659 static void it87_write_value(struct it87_data *data, u8 reg, u8 value) 660 { 661 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); 662 outb_p(value, data->addr + IT87_DATA_REG_OFFSET); 663 } 664 665 static void it87_update_pwm_ctrl(struct it87_data *data, int nr) 666 { 667 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]); 668 if (has_newer_autopwm(data)) { 669 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; 670 data->pwm_duty[nr] = it87_read_value(data, 671 IT87_REG_PWM_DUTY[nr]); 672 } else { 673 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */ 674 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; 675 else /* Manual mode */ 676 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f; 677 } 678 679 if (has_old_autopwm(data)) { 680 int i; 681 682 for (i = 0; i < 5 ; i++) 683 data->auto_temp[nr][i] = it87_read_value(data, 684 IT87_REG_AUTO_TEMP(nr, i)); 685 for (i = 0; i < 3 ; i++) 686 data->auto_pwm[nr][i] = it87_read_value(data, 687 IT87_REG_AUTO_PWM(nr, i)); 688 } else if (has_newer_autopwm(data)) { 689 int i; 690 691 /* 692 * 0: temperature hysteresis (base + 5) 693 * 1: fan off temperature (base + 0) 694 * 2: fan start temperature (base + 1) 695 * 3: fan max temperature (base + 2) 696 */ 697 data->auto_temp[nr][0] = 698 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5)); 699 700 for (i = 0; i < 3 ; i++) 701 data->auto_temp[nr][i + 1] = 702 it87_read_value(data, 703 IT87_REG_AUTO_TEMP(nr, i)); 704 /* 705 * 0: start pwm value (base + 3) 706 * 1: pwm slope (base + 4, 1/8th pwm) 707 */ 708 data->auto_pwm[nr][0] = 709 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3)); 710 data->auto_pwm[nr][1] = 711 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4)); 712 } 713 } 714 715 static struct it87_data *it87_update_device(struct device *dev) 716 { 717 struct it87_data *data = dev_get_drvdata(dev); 718 int i; 719 720 mutex_lock(&data->update_lock); 721 722 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) || 723 !data->valid) { 724 if (update_vbat) { 725 /* 726 * Cleared after each update, so reenable. Value 727 * returned by this read will be previous value 728 */ 729 it87_write_value(data, IT87_REG_CONFIG, 730 it87_read_value(data, IT87_REG_CONFIG) | 0x40); 731 } 732 for (i = 0; i < NUM_VIN; i++) { 733 if (!(data->has_in & BIT(i))) 734 continue; 735 736 data->in[i][0] = 737 it87_read_value(data, IT87_REG_VIN[i]); 738 739 /* VBAT and AVCC don't have limit registers */ 740 if (i >= NUM_VIN_LIMIT) 741 continue; 742 743 data->in[i][1] = 744 it87_read_value(data, IT87_REG_VIN_MIN(i)); 745 data->in[i][2] = 746 it87_read_value(data, IT87_REG_VIN_MAX(i)); 747 } 748 749 for (i = 0; i < NUM_FAN; i++) { 750 /* Skip disabled fans */ 751 if (!(data->has_fan & BIT(i))) 752 continue; 753 754 data->fan[i][1] = 755 it87_read_value(data, IT87_REG_FAN_MIN[i]); 756 data->fan[i][0] = it87_read_value(data, 757 IT87_REG_FAN[i]); 758 /* Add high byte if in 16-bit mode */ 759 if (has_16bit_fans(data)) { 760 data->fan[i][0] |= it87_read_value(data, 761 IT87_REG_FANX[i]) << 8; 762 data->fan[i][1] |= it87_read_value(data, 763 IT87_REG_FANX_MIN[i]) << 8; 764 } 765 } 766 for (i = 0; i < NUM_TEMP; i++) { 767 if (!(data->has_temp & BIT(i))) 768 continue; 769 data->temp[i][0] = 770 it87_read_value(data, IT87_REG_TEMP(i)); 771 772 if (has_temp_offset(data) && i < NUM_TEMP_OFFSET) 773 data->temp[i][3] = 774 it87_read_value(data, 775 IT87_REG_TEMP_OFFSET[i]); 776 777 if (i >= NUM_TEMP_LIMIT) 778 continue; 779 780 data->temp[i][1] = 781 it87_read_value(data, IT87_REG_TEMP_LOW(i)); 782 data->temp[i][2] = 783 it87_read_value(data, IT87_REG_TEMP_HIGH(i)); 784 } 785 786 /* Newer chips don't have clock dividers */ 787 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) { 788 i = it87_read_value(data, IT87_REG_FAN_DIV); 789 data->fan_div[0] = i & 0x07; 790 data->fan_div[1] = (i >> 3) & 0x07; 791 data->fan_div[2] = (i & 0x40) ? 3 : 1; 792 } 793 794 data->alarms = 795 it87_read_value(data, IT87_REG_ALARM1) | 796 (it87_read_value(data, IT87_REG_ALARM2) << 8) | 797 (it87_read_value(data, IT87_REG_ALARM3) << 16); 798 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); 799 800 data->fan_main_ctrl = it87_read_value(data, 801 IT87_REG_FAN_MAIN_CTRL); 802 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL); 803 for (i = 0; i < NUM_PWM; i++) { 804 if (!(data->has_pwm & BIT(i))) 805 continue; 806 it87_update_pwm_ctrl(data, i); 807 } 808 809 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); 810 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); 811 /* 812 * The IT8705F does not have VID capability. 813 * The IT8718F and later don't use IT87_REG_VID for the 814 * same purpose. 815 */ 816 if (data->type == it8712 || data->type == it8716) { 817 data->vid = it87_read_value(data, IT87_REG_VID); 818 /* 819 * The older IT8712F revisions had only 5 VID pins, 820 * but we assume it is always safe to read 6 bits. 821 */ 822 data->vid &= 0x3f; 823 } 824 data->last_updated = jiffies; 825 data->valid = 1; 826 } 827 828 mutex_unlock(&data->update_lock); 829 830 return data; 831 } 832 833 static ssize_t show_in(struct device *dev, struct device_attribute *attr, 834 char *buf) 835 { 836 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 837 struct it87_data *data = it87_update_device(dev); 838 int index = sattr->index; 839 int nr = sattr->nr; 840 841 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index])); 842 } 843 844 static ssize_t set_in(struct device *dev, struct device_attribute *attr, 845 const char *buf, size_t count) 846 { 847 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 848 struct it87_data *data = dev_get_drvdata(dev); 849 int index = sattr->index; 850 int nr = sattr->nr; 851 unsigned long val; 852 853 if (kstrtoul(buf, 10, &val) < 0) 854 return -EINVAL; 855 856 mutex_lock(&data->update_lock); 857 data->in[nr][index] = in_to_reg(data, nr, val); 858 it87_write_value(data, 859 index == 1 ? IT87_REG_VIN_MIN(nr) 860 : IT87_REG_VIN_MAX(nr), 861 data->in[nr][index]); 862 mutex_unlock(&data->update_lock); 863 return count; 864 } 865 866 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0); 867 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in, 868 0, 1); 869 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in, 870 0, 2); 871 872 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0); 873 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in, 874 1, 1); 875 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in, 876 1, 2); 877 878 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0); 879 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in, 880 2, 1); 881 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in, 882 2, 2); 883 884 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0); 885 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in, 886 3, 1); 887 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in, 888 3, 2); 889 890 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0); 891 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in, 892 4, 1); 893 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in, 894 4, 2); 895 896 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0); 897 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in, 898 5, 1); 899 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in, 900 5, 2); 901 902 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0); 903 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in, 904 6, 1); 905 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in, 906 6, 2); 907 908 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0); 909 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in, 910 7, 1); 911 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in, 912 7, 2); 913 914 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0); 915 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0); 916 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0); 917 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0); 918 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0); 919 920 /* Up to 6 temperatures */ 921 static ssize_t show_temp(struct device *dev, struct device_attribute *attr, 922 char *buf) 923 { 924 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 925 int nr = sattr->nr; 926 int index = sattr->index; 927 struct it87_data *data = it87_update_device(dev); 928 929 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index])); 930 } 931 932 static ssize_t set_temp(struct device *dev, struct device_attribute *attr, 933 const char *buf, size_t count) 934 { 935 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 936 int nr = sattr->nr; 937 int index = sattr->index; 938 struct it87_data *data = dev_get_drvdata(dev); 939 long val; 940 u8 reg, regval; 941 942 if (kstrtol(buf, 10, &val) < 0) 943 return -EINVAL; 944 945 mutex_lock(&data->update_lock); 946 947 switch (index) { 948 default: 949 case 1: 950 reg = IT87_REG_TEMP_LOW(nr); 951 break; 952 case 2: 953 reg = IT87_REG_TEMP_HIGH(nr); 954 break; 955 case 3: 956 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE); 957 if (!(regval & 0x80)) { 958 regval |= 0x80; 959 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval); 960 } 961 data->valid = 0; 962 reg = IT87_REG_TEMP_OFFSET[nr]; 963 break; 964 } 965 966 data->temp[nr][index] = TEMP_TO_REG(val); 967 it87_write_value(data, reg, data->temp[nr][index]); 968 mutex_unlock(&data->update_lock); 969 return count; 970 } 971 972 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0); 973 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 974 0, 1); 975 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 976 0, 2); 977 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp, 978 set_temp, 0, 3); 979 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0); 980 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 981 1, 1); 982 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 983 1, 2); 984 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp, 985 set_temp, 1, 3); 986 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0); 987 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 988 2, 1); 989 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 990 2, 2); 991 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp, 992 set_temp, 2, 3); 993 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0); 994 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0); 995 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0); 996 997 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr, 998 char *buf) 999 { 1000 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1001 int nr = sensor_attr->index; 1002 struct it87_data *data = it87_update_device(dev); 1003 u8 reg = data->sensor; /* In case value is updated while used */ 1004 u8 extra = data->extra; 1005 1006 if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) || 1007 (has_temp_old_peci(data, nr) && (extra & 0x80))) 1008 return sprintf(buf, "6\n"); /* Intel PECI */ 1009 if (reg & (1 << nr)) 1010 return sprintf(buf, "3\n"); /* thermal diode */ 1011 if (reg & (8 << nr)) 1012 return sprintf(buf, "4\n"); /* thermistor */ 1013 return sprintf(buf, "0\n"); /* disabled */ 1014 } 1015 1016 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr, 1017 const char *buf, size_t count) 1018 { 1019 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1020 int nr = sensor_attr->index; 1021 1022 struct it87_data *data = dev_get_drvdata(dev); 1023 long val; 1024 u8 reg, extra; 1025 1026 if (kstrtol(buf, 10, &val) < 0) 1027 return -EINVAL; 1028 1029 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); 1030 reg &= ~(1 << nr); 1031 reg &= ~(8 << nr); 1032 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6)) 1033 reg &= 0x3f; 1034 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); 1035 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6)) 1036 extra &= 0x7f; 1037 if (val == 2) { /* backwards compatibility */ 1038 dev_warn(dev, 1039 "Sensor type 2 is deprecated, please use 4 instead\n"); 1040 val = 4; 1041 } 1042 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */ 1043 if (val == 3) 1044 reg |= 1 << nr; 1045 else if (val == 4) 1046 reg |= 8 << nr; 1047 else if (has_temp_peci(data, nr) && val == 6) 1048 reg |= (nr + 1) << 6; 1049 else if (has_temp_old_peci(data, nr) && val == 6) 1050 extra |= 0x80; 1051 else if (val != 0) 1052 return -EINVAL; 1053 1054 mutex_lock(&data->update_lock); 1055 data->sensor = reg; 1056 data->extra = extra; 1057 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor); 1058 if (has_temp_old_peci(data, nr)) 1059 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); 1060 data->valid = 0; /* Force cache refresh */ 1061 mutex_unlock(&data->update_lock); 1062 return count; 1063 } 1064 1065 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type, 1066 set_temp_type, 0); 1067 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type, 1068 set_temp_type, 1); 1069 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type, 1070 set_temp_type, 2); 1071 1072 /* 6 Fans */ 1073 1074 static int pwm_mode(const struct it87_data *data, int nr) 1075 { 1076 if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr))) 1077 return 0; /* Full speed */ 1078 if (data->pwm_ctrl[nr] & 0x80) 1079 return 2; /* Automatic mode */ 1080 if ((data->type == it8603 || nr >= 3) && 1081 data->pwm_duty[nr] == pwm_to_reg(data, 0xff)) 1082 return 0; /* Full speed */ 1083 1084 return 1; /* Manual mode */ 1085 } 1086 1087 static ssize_t show_fan(struct device *dev, struct device_attribute *attr, 1088 char *buf) 1089 { 1090 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1091 int nr = sattr->nr; 1092 int index = sattr->index; 1093 int speed; 1094 struct it87_data *data = it87_update_device(dev); 1095 1096 speed = has_16bit_fans(data) ? 1097 FAN16_FROM_REG(data->fan[nr][index]) : 1098 FAN_FROM_REG(data->fan[nr][index], 1099 DIV_FROM_REG(data->fan_div[nr])); 1100 return sprintf(buf, "%d\n", speed); 1101 } 1102 1103 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr, 1104 char *buf) 1105 { 1106 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1107 struct it87_data *data = it87_update_device(dev); 1108 int nr = sensor_attr->index; 1109 1110 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr])); 1111 } 1112 1113 static ssize_t show_pwm_enable(struct device *dev, 1114 struct device_attribute *attr, char *buf) 1115 { 1116 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1117 struct it87_data *data = it87_update_device(dev); 1118 int nr = sensor_attr->index; 1119 1120 return sprintf(buf, "%d\n", pwm_mode(data, nr)); 1121 } 1122 1123 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, 1124 char *buf) 1125 { 1126 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1127 struct it87_data *data = it87_update_device(dev); 1128 int nr = sensor_attr->index; 1129 1130 return sprintf(buf, "%d\n", 1131 pwm_from_reg(data, data->pwm_duty[nr])); 1132 } 1133 1134 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr, 1135 char *buf) 1136 { 1137 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1138 struct it87_data *data = it87_update_device(dev); 1139 int nr = sensor_attr->index; 1140 unsigned int freq; 1141 int index; 1142 1143 if (has_pwm_freq2(data) && nr == 1) 1144 index = (data->extra >> 4) & 0x07; 1145 else 1146 index = (data->fan_ctl >> 4) & 0x07; 1147 1148 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128); 1149 1150 return sprintf(buf, "%u\n", freq); 1151 } 1152 1153 static ssize_t set_fan(struct device *dev, struct device_attribute *attr, 1154 const char *buf, size_t count) 1155 { 1156 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1157 int nr = sattr->nr; 1158 int index = sattr->index; 1159 1160 struct it87_data *data = dev_get_drvdata(dev); 1161 long val; 1162 u8 reg; 1163 1164 if (kstrtol(buf, 10, &val) < 0) 1165 return -EINVAL; 1166 1167 mutex_lock(&data->update_lock); 1168 1169 if (has_16bit_fans(data)) { 1170 data->fan[nr][index] = FAN16_TO_REG(val); 1171 it87_write_value(data, IT87_REG_FAN_MIN[nr], 1172 data->fan[nr][index] & 0xff); 1173 it87_write_value(data, IT87_REG_FANX_MIN[nr], 1174 data->fan[nr][index] >> 8); 1175 } else { 1176 reg = it87_read_value(data, IT87_REG_FAN_DIV); 1177 switch (nr) { 1178 case 0: 1179 data->fan_div[nr] = reg & 0x07; 1180 break; 1181 case 1: 1182 data->fan_div[nr] = (reg >> 3) & 0x07; 1183 break; 1184 case 2: 1185 data->fan_div[nr] = (reg & 0x40) ? 3 : 1; 1186 break; 1187 } 1188 data->fan[nr][index] = 1189 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); 1190 it87_write_value(data, IT87_REG_FAN_MIN[nr], 1191 data->fan[nr][index]); 1192 } 1193 1194 mutex_unlock(&data->update_lock); 1195 return count; 1196 } 1197 1198 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr, 1199 const char *buf, size_t count) 1200 { 1201 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1202 struct it87_data *data = dev_get_drvdata(dev); 1203 int nr = sensor_attr->index; 1204 unsigned long val; 1205 int min; 1206 u8 old; 1207 1208 if (kstrtoul(buf, 10, &val) < 0) 1209 return -EINVAL; 1210 1211 mutex_lock(&data->update_lock); 1212 old = it87_read_value(data, IT87_REG_FAN_DIV); 1213 1214 /* Save fan min limit */ 1215 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr])); 1216 1217 switch (nr) { 1218 case 0: 1219 case 1: 1220 data->fan_div[nr] = DIV_TO_REG(val); 1221 break; 1222 case 2: 1223 if (val < 8) 1224 data->fan_div[nr] = 1; 1225 else 1226 data->fan_div[nr] = 3; 1227 } 1228 val = old & 0x80; 1229 val |= (data->fan_div[0] & 0x07); 1230 val |= (data->fan_div[1] & 0x07) << 3; 1231 if (data->fan_div[2] == 3) 1232 val |= 0x1 << 6; 1233 it87_write_value(data, IT87_REG_FAN_DIV, val); 1234 1235 /* Restore fan min limit */ 1236 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr])); 1237 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]); 1238 1239 mutex_unlock(&data->update_lock); 1240 return count; 1241 } 1242 1243 /* Returns 0 if OK, -EINVAL otherwise */ 1244 static int check_trip_points(struct device *dev, int nr) 1245 { 1246 const struct it87_data *data = dev_get_drvdata(dev); 1247 int i, err = 0; 1248 1249 if (has_old_autopwm(data)) { 1250 for (i = 0; i < 3; i++) { 1251 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) 1252 err = -EINVAL; 1253 } 1254 for (i = 0; i < 2; i++) { 1255 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1]) 1256 err = -EINVAL; 1257 } 1258 } else if (has_newer_autopwm(data)) { 1259 for (i = 1; i < 3; i++) { 1260 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) 1261 err = -EINVAL; 1262 } 1263 } 1264 1265 if (err) { 1266 dev_err(dev, 1267 "Inconsistent trip points, not switching to automatic mode\n"); 1268 dev_err(dev, "Adjust the trip points and try again\n"); 1269 } 1270 return err; 1271 } 1272 1273 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr, 1274 const char *buf, size_t count) 1275 { 1276 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1277 struct it87_data *data = dev_get_drvdata(dev); 1278 int nr = sensor_attr->index; 1279 long val; 1280 1281 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2) 1282 return -EINVAL; 1283 1284 /* Check trip points before switching to automatic mode */ 1285 if (val == 2) { 1286 if (check_trip_points(dev, nr) < 0) 1287 return -EINVAL; 1288 } 1289 1290 mutex_lock(&data->update_lock); 1291 1292 if (val == 0) { 1293 if (nr < 3 && data->type != it8603) { 1294 int tmp; 1295 /* make sure the fan is on when in on/off mode */ 1296 tmp = it87_read_value(data, IT87_REG_FAN_CTL); 1297 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr)); 1298 /* set on/off mode */ 1299 data->fan_main_ctrl &= ~BIT(nr); 1300 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 1301 data->fan_main_ctrl); 1302 } else { 1303 /* No on/off mode, set maximum pwm value */ 1304 data->pwm_duty[nr] = pwm_to_reg(data, 0xff); 1305 it87_write_value(data, IT87_REG_PWM_DUTY[nr], 1306 data->pwm_duty[nr]); 1307 /* and set manual mode */ 1308 data->pwm_ctrl[nr] = has_newer_autopwm(data) ? 1309 data->pwm_temp_map[nr] : 1310 data->pwm_duty[nr]; 1311 it87_write_value(data, IT87_REG_PWM[nr], 1312 data->pwm_ctrl[nr]); 1313 } 1314 } else { 1315 if (val == 1) /* Manual mode */ 1316 data->pwm_ctrl[nr] = has_newer_autopwm(data) ? 1317 data->pwm_temp_map[nr] : 1318 data->pwm_duty[nr]; 1319 else /* Automatic mode */ 1320 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr]; 1321 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]); 1322 1323 if (data->type != it8603 && nr < 3) { 1324 /* set SmartGuardian mode */ 1325 data->fan_main_ctrl |= BIT(nr); 1326 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 1327 data->fan_main_ctrl); 1328 } 1329 } 1330 1331 mutex_unlock(&data->update_lock); 1332 return count; 1333 } 1334 1335 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, 1336 const char *buf, size_t count) 1337 { 1338 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1339 struct it87_data *data = dev_get_drvdata(dev); 1340 int nr = sensor_attr->index; 1341 long val; 1342 1343 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) 1344 return -EINVAL; 1345 1346 mutex_lock(&data->update_lock); 1347 if (has_newer_autopwm(data)) { 1348 /* 1349 * If we are in automatic mode, the PWM duty cycle register 1350 * is read-only so we can't write the value. 1351 */ 1352 if (data->pwm_ctrl[nr] & 0x80) { 1353 mutex_unlock(&data->update_lock); 1354 return -EBUSY; 1355 } 1356 data->pwm_duty[nr] = pwm_to_reg(data, val); 1357 it87_write_value(data, IT87_REG_PWM_DUTY[nr], 1358 data->pwm_duty[nr]); 1359 } else { 1360 data->pwm_duty[nr] = pwm_to_reg(data, val); 1361 /* 1362 * If we are in manual mode, write the duty cycle immediately; 1363 * otherwise, just store it for later use. 1364 */ 1365 if (!(data->pwm_ctrl[nr] & 0x80)) { 1366 data->pwm_ctrl[nr] = data->pwm_duty[nr]; 1367 it87_write_value(data, IT87_REG_PWM[nr], 1368 data->pwm_ctrl[nr]); 1369 } 1370 } 1371 mutex_unlock(&data->update_lock); 1372 return count; 1373 } 1374 1375 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr, 1376 const char *buf, size_t count) 1377 { 1378 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1379 struct it87_data *data = dev_get_drvdata(dev); 1380 int nr = sensor_attr->index; 1381 unsigned long val; 1382 int i; 1383 1384 if (kstrtoul(buf, 10, &val) < 0) 1385 return -EINVAL; 1386 1387 val = clamp_val(val, 0, 1000000); 1388 val *= has_newer_autopwm(data) ? 256 : 128; 1389 1390 /* Search for the nearest available frequency */ 1391 for (i = 0; i < 7; i++) { 1392 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2) 1393 break; 1394 } 1395 1396 mutex_lock(&data->update_lock); 1397 if (nr == 0) { 1398 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f; 1399 data->fan_ctl |= i << 4; 1400 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl); 1401 } else { 1402 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f; 1403 data->extra |= i << 4; 1404 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); 1405 } 1406 mutex_unlock(&data->update_lock); 1407 1408 return count; 1409 } 1410 1411 static ssize_t show_pwm_temp_map(struct device *dev, 1412 struct device_attribute *attr, char *buf) 1413 { 1414 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1415 struct it87_data *data = it87_update_device(dev); 1416 int nr = sensor_attr->index; 1417 int map; 1418 1419 map = data->pwm_temp_map[nr]; 1420 if (map >= 3) 1421 map = 0; /* Should never happen */ 1422 if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */ 1423 map += 3; 1424 1425 return sprintf(buf, "%d\n", (int)BIT(map)); 1426 } 1427 1428 static ssize_t set_pwm_temp_map(struct device *dev, 1429 struct device_attribute *attr, const char *buf, 1430 size_t count) 1431 { 1432 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1433 struct it87_data *data = dev_get_drvdata(dev); 1434 int nr = sensor_attr->index; 1435 long val; 1436 u8 reg; 1437 1438 if (kstrtol(buf, 10, &val) < 0) 1439 return -EINVAL; 1440 1441 if (nr >= 3) 1442 val -= 3; 1443 1444 switch (val) { 1445 case BIT(0): 1446 reg = 0x00; 1447 break; 1448 case BIT(1): 1449 reg = 0x01; 1450 break; 1451 case BIT(2): 1452 reg = 0x02; 1453 break; 1454 default: 1455 return -EINVAL; 1456 } 1457 1458 mutex_lock(&data->update_lock); 1459 data->pwm_temp_map[nr] = reg; 1460 /* 1461 * If we are in automatic mode, write the temp mapping immediately; 1462 * otherwise, just store it for later use. 1463 */ 1464 if (data->pwm_ctrl[nr] & 0x80) { 1465 data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr]; 1466 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]); 1467 } 1468 mutex_unlock(&data->update_lock); 1469 return count; 1470 } 1471 1472 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr, 1473 char *buf) 1474 { 1475 struct it87_data *data = it87_update_device(dev); 1476 struct sensor_device_attribute_2 *sensor_attr = 1477 to_sensor_dev_attr_2(attr); 1478 int nr = sensor_attr->nr; 1479 int point = sensor_attr->index; 1480 1481 return sprintf(buf, "%d\n", 1482 pwm_from_reg(data, data->auto_pwm[nr][point])); 1483 } 1484 1485 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr, 1486 const char *buf, size_t count) 1487 { 1488 struct it87_data *data = dev_get_drvdata(dev); 1489 struct sensor_device_attribute_2 *sensor_attr = 1490 to_sensor_dev_attr_2(attr); 1491 int nr = sensor_attr->nr; 1492 int point = sensor_attr->index; 1493 int regaddr; 1494 long val; 1495 1496 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) 1497 return -EINVAL; 1498 1499 mutex_lock(&data->update_lock); 1500 data->auto_pwm[nr][point] = pwm_to_reg(data, val); 1501 if (has_newer_autopwm(data)) 1502 regaddr = IT87_REG_AUTO_TEMP(nr, 3); 1503 else 1504 regaddr = IT87_REG_AUTO_PWM(nr, point); 1505 it87_write_value(data, regaddr, data->auto_pwm[nr][point]); 1506 mutex_unlock(&data->update_lock); 1507 return count; 1508 } 1509 1510 static ssize_t show_auto_pwm_slope(struct device *dev, 1511 struct device_attribute *attr, char *buf) 1512 { 1513 struct it87_data *data = it87_update_device(dev); 1514 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1515 int nr = sensor_attr->index; 1516 1517 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f); 1518 } 1519 1520 static ssize_t set_auto_pwm_slope(struct device *dev, 1521 struct device_attribute *attr, 1522 const char *buf, size_t count) 1523 { 1524 struct it87_data *data = dev_get_drvdata(dev); 1525 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1526 int nr = sensor_attr->index; 1527 unsigned long val; 1528 1529 if (kstrtoul(buf, 10, &val) < 0 || val > 127) 1530 return -EINVAL; 1531 1532 mutex_lock(&data->update_lock); 1533 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val; 1534 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4), 1535 data->auto_pwm[nr][1]); 1536 mutex_unlock(&data->update_lock); 1537 return count; 1538 } 1539 1540 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr, 1541 char *buf) 1542 { 1543 struct it87_data *data = it87_update_device(dev); 1544 struct sensor_device_attribute_2 *sensor_attr = 1545 to_sensor_dev_attr_2(attr); 1546 int nr = sensor_attr->nr; 1547 int point = sensor_attr->index; 1548 int reg; 1549 1550 if (has_old_autopwm(data) || point) 1551 reg = data->auto_temp[nr][point]; 1552 else 1553 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f); 1554 1555 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg)); 1556 } 1557 1558 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr, 1559 const char *buf, size_t count) 1560 { 1561 struct it87_data *data = dev_get_drvdata(dev); 1562 struct sensor_device_attribute_2 *sensor_attr = 1563 to_sensor_dev_attr_2(attr); 1564 int nr = sensor_attr->nr; 1565 int point = sensor_attr->index; 1566 long val; 1567 int reg; 1568 1569 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000) 1570 return -EINVAL; 1571 1572 mutex_lock(&data->update_lock); 1573 if (has_newer_autopwm(data) && !point) { 1574 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val); 1575 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0); 1576 data->auto_temp[nr][0] = reg; 1577 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg); 1578 } else { 1579 reg = TEMP_TO_REG(val); 1580 data->auto_temp[nr][point] = reg; 1581 if (has_newer_autopwm(data)) 1582 point--; 1583 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg); 1584 } 1585 mutex_unlock(&data->update_lock); 1586 return count; 1587 } 1588 1589 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0); 1590 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1591 0, 1); 1592 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div, 1593 set_fan_div, 0); 1594 1595 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0); 1596 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1597 1, 1); 1598 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div, 1599 set_fan_div, 1); 1600 1601 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0); 1602 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1603 2, 1); 1604 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div, 1605 set_fan_div, 2); 1606 1607 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0); 1608 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1609 3, 1); 1610 1611 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0); 1612 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1613 4, 1); 1614 1615 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0); 1616 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1617 5, 1); 1618 1619 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, 1620 show_pwm_enable, set_pwm_enable, 0); 1621 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0); 1622 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, 1623 set_pwm_freq, 0); 1624 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO, 1625 show_pwm_temp_map, set_pwm_temp_map, 0); 1626 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR, 1627 show_auto_pwm, set_auto_pwm, 0, 0); 1628 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR, 1629 show_auto_pwm, set_auto_pwm, 0, 1); 1630 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR, 1631 show_auto_pwm, set_auto_pwm, 0, 2); 1632 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO, 1633 show_auto_pwm, NULL, 0, 3); 1634 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR, 1635 show_auto_temp, set_auto_temp, 0, 1); 1636 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1637 show_auto_temp, set_auto_temp, 0, 0); 1638 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR, 1639 show_auto_temp, set_auto_temp, 0, 2); 1640 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR, 1641 show_auto_temp, set_auto_temp, 0, 3); 1642 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR, 1643 show_auto_temp, set_auto_temp, 0, 4); 1644 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR, 1645 show_auto_pwm, set_auto_pwm, 0, 0); 1646 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR, 1647 show_auto_pwm_slope, set_auto_pwm_slope, 0); 1648 1649 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR, 1650 show_pwm_enable, set_pwm_enable, 1); 1651 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1); 1652 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1); 1653 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO, 1654 show_pwm_temp_map, set_pwm_temp_map, 1); 1655 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR, 1656 show_auto_pwm, set_auto_pwm, 1, 0); 1657 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR, 1658 show_auto_pwm, set_auto_pwm, 1, 1); 1659 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR, 1660 show_auto_pwm, set_auto_pwm, 1, 2); 1661 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO, 1662 show_auto_pwm, NULL, 1, 3); 1663 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR, 1664 show_auto_temp, set_auto_temp, 1, 1); 1665 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1666 show_auto_temp, set_auto_temp, 1, 0); 1667 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR, 1668 show_auto_temp, set_auto_temp, 1, 2); 1669 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR, 1670 show_auto_temp, set_auto_temp, 1, 3); 1671 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR, 1672 show_auto_temp, set_auto_temp, 1, 4); 1673 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR, 1674 show_auto_pwm, set_auto_pwm, 1, 0); 1675 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR, 1676 show_auto_pwm_slope, set_auto_pwm_slope, 1); 1677 1678 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR, 1679 show_pwm_enable, set_pwm_enable, 2); 1680 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2); 1681 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2); 1682 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO, 1683 show_pwm_temp_map, set_pwm_temp_map, 2); 1684 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR, 1685 show_auto_pwm, set_auto_pwm, 2, 0); 1686 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR, 1687 show_auto_pwm, set_auto_pwm, 2, 1); 1688 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR, 1689 show_auto_pwm, set_auto_pwm, 2, 2); 1690 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO, 1691 show_auto_pwm, NULL, 2, 3); 1692 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR, 1693 show_auto_temp, set_auto_temp, 2, 1); 1694 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1695 show_auto_temp, set_auto_temp, 2, 0); 1696 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR, 1697 show_auto_temp, set_auto_temp, 2, 2); 1698 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR, 1699 show_auto_temp, set_auto_temp, 2, 3); 1700 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR, 1701 show_auto_temp, set_auto_temp, 2, 4); 1702 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR, 1703 show_auto_pwm, set_auto_pwm, 2, 0); 1704 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR, 1705 show_auto_pwm_slope, set_auto_pwm_slope, 2); 1706 1707 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR, 1708 show_pwm_enable, set_pwm_enable, 3); 1709 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3); 1710 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3); 1711 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO, 1712 show_pwm_temp_map, set_pwm_temp_map, 3); 1713 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR, 1714 show_auto_temp, set_auto_temp, 2, 1); 1715 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1716 show_auto_temp, set_auto_temp, 2, 0); 1717 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR, 1718 show_auto_temp, set_auto_temp, 2, 2); 1719 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR, 1720 show_auto_temp, set_auto_temp, 2, 3); 1721 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR, 1722 show_auto_pwm, set_auto_pwm, 3, 0); 1723 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR, 1724 show_auto_pwm_slope, set_auto_pwm_slope, 3); 1725 1726 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR, 1727 show_pwm_enable, set_pwm_enable, 4); 1728 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4); 1729 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4); 1730 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO, 1731 show_pwm_temp_map, set_pwm_temp_map, 4); 1732 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR, 1733 show_auto_temp, set_auto_temp, 2, 1); 1734 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1735 show_auto_temp, set_auto_temp, 2, 0); 1736 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR, 1737 show_auto_temp, set_auto_temp, 2, 2); 1738 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR, 1739 show_auto_temp, set_auto_temp, 2, 3); 1740 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR, 1741 show_auto_pwm, set_auto_pwm, 4, 0); 1742 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR, 1743 show_auto_pwm_slope, set_auto_pwm_slope, 4); 1744 1745 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR, 1746 show_pwm_enable, set_pwm_enable, 5); 1747 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5); 1748 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5); 1749 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO, 1750 show_pwm_temp_map, set_pwm_temp_map, 5); 1751 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR, 1752 show_auto_temp, set_auto_temp, 2, 1); 1753 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1754 show_auto_temp, set_auto_temp, 2, 0); 1755 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR, 1756 show_auto_temp, set_auto_temp, 2, 2); 1757 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR, 1758 show_auto_temp, set_auto_temp, 2, 3); 1759 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR, 1760 show_auto_pwm, set_auto_pwm, 5, 0); 1761 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR, 1762 show_auto_pwm_slope, set_auto_pwm_slope, 5); 1763 1764 /* Alarms */ 1765 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr, 1766 char *buf) 1767 { 1768 struct it87_data *data = it87_update_device(dev); 1769 1770 return sprintf(buf, "%u\n", data->alarms); 1771 } 1772 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL); 1773 1774 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, 1775 char *buf) 1776 { 1777 struct it87_data *data = it87_update_device(dev); 1778 int bitnr = to_sensor_dev_attr(attr)->index; 1779 1780 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1); 1781 } 1782 1783 static ssize_t clear_intrusion(struct device *dev, 1784 struct device_attribute *attr, const char *buf, 1785 size_t count) 1786 { 1787 struct it87_data *data = dev_get_drvdata(dev); 1788 int config; 1789 long val; 1790 1791 if (kstrtol(buf, 10, &val) < 0 || val != 0) 1792 return -EINVAL; 1793 1794 mutex_lock(&data->update_lock); 1795 config = it87_read_value(data, IT87_REG_CONFIG); 1796 if (config < 0) { 1797 count = config; 1798 } else { 1799 config |= BIT(5); 1800 it87_write_value(data, IT87_REG_CONFIG, config); 1801 /* Invalidate cache to force re-read */ 1802 data->valid = 0; 1803 } 1804 mutex_unlock(&data->update_lock); 1805 1806 return count; 1807 } 1808 1809 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8); 1810 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9); 1811 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10); 1812 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11); 1813 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12); 1814 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13); 1815 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14); 1816 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15); 1817 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0); 1818 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1); 1819 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2); 1820 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3); 1821 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6); 1822 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7); 1823 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16); 1824 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17); 1825 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18); 1826 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR, 1827 show_alarm, clear_intrusion, 4); 1828 1829 static ssize_t show_beep(struct device *dev, struct device_attribute *attr, 1830 char *buf) 1831 { 1832 struct it87_data *data = it87_update_device(dev); 1833 int bitnr = to_sensor_dev_attr(attr)->index; 1834 1835 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1); 1836 } 1837 1838 static ssize_t set_beep(struct device *dev, struct device_attribute *attr, 1839 const char *buf, size_t count) 1840 { 1841 int bitnr = to_sensor_dev_attr(attr)->index; 1842 struct it87_data *data = dev_get_drvdata(dev); 1843 long val; 1844 1845 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1)) 1846 return -EINVAL; 1847 1848 mutex_lock(&data->update_lock); 1849 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); 1850 if (val) 1851 data->beeps |= BIT(bitnr); 1852 else 1853 data->beeps &= ~BIT(bitnr); 1854 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps); 1855 mutex_unlock(&data->update_lock); 1856 return count; 1857 } 1858 1859 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR, 1860 show_beep, set_beep, 1); 1861 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1); 1862 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1); 1863 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1); 1864 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1); 1865 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1); 1866 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1); 1867 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1); 1868 /* fanX_beep writability is set later */ 1869 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0); 1870 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0); 1871 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0); 1872 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0); 1873 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0); 1874 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0); 1875 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR, 1876 show_beep, set_beep, 2); 1877 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2); 1878 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2); 1879 1880 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr, 1881 char *buf) 1882 { 1883 struct it87_data *data = dev_get_drvdata(dev); 1884 1885 return sprintf(buf, "%u\n", data->vrm); 1886 } 1887 1888 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr, 1889 const char *buf, size_t count) 1890 { 1891 struct it87_data *data = dev_get_drvdata(dev); 1892 unsigned long val; 1893 1894 if (kstrtoul(buf, 10, &val) < 0) 1895 return -EINVAL; 1896 1897 data->vrm = val; 1898 1899 return count; 1900 } 1901 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg); 1902 1903 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr, 1904 char *buf) 1905 { 1906 struct it87_data *data = it87_update_device(dev); 1907 1908 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm)); 1909 } 1910 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL); 1911 1912 static ssize_t show_label(struct device *dev, struct device_attribute *attr, 1913 char *buf) 1914 { 1915 static const char * const labels[] = { 1916 "+5V", 1917 "5VSB", 1918 "Vbat", 1919 }; 1920 static const char * const labels_it8721[] = { 1921 "+3.3V", 1922 "3VSB", 1923 "Vbat", 1924 }; 1925 struct it87_data *data = dev_get_drvdata(dev); 1926 int nr = to_sensor_dev_attr(attr)->index; 1927 const char *label; 1928 1929 if (has_12mv_adc(data) || has_10_9mv_adc(data)) 1930 label = labels_it8721[nr]; 1931 else 1932 label = labels[nr]; 1933 1934 return sprintf(buf, "%s\n", label); 1935 } 1936 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0); 1937 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1); 1938 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2); 1939 /* AVCC3 */ 1940 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 0); 1941 1942 static umode_t it87_in_is_visible(struct kobject *kobj, 1943 struct attribute *attr, int index) 1944 { 1945 struct device *dev = container_of(kobj, struct device, kobj); 1946 struct it87_data *data = dev_get_drvdata(dev); 1947 int i = index / 5; /* voltage index */ 1948 int a = index % 5; /* attribute index */ 1949 1950 if (index >= 40) { /* in8 and higher only have input attributes */ 1951 i = index - 40 + 8; 1952 a = 0; 1953 } 1954 1955 if (!(data->has_in & BIT(i))) 1956 return 0; 1957 1958 if (a == 4 && !data->has_beep) 1959 return 0; 1960 1961 return attr->mode; 1962 } 1963 1964 static struct attribute *it87_attributes_in[] = { 1965 &sensor_dev_attr_in0_input.dev_attr.attr, 1966 &sensor_dev_attr_in0_min.dev_attr.attr, 1967 &sensor_dev_attr_in0_max.dev_attr.attr, 1968 &sensor_dev_attr_in0_alarm.dev_attr.attr, 1969 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */ 1970 1971 &sensor_dev_attr_in1_input.dev_attr.attr, 1972 &sensor_dev_attr_in1_min.dev_attr.attr, 1973 &sensor_dev_attr_in1_max.dev_attr.attr, 1974 &sensor_dev_attr_in1_alarm.dev_attr.attr, 1975 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */ 1976 1977 &sensor_dev_attr_in2_input.dev_attr.attr, 1978 &sensor_dev_attr_in2_min.dev_attr.attr, 1979 &sensor_dev_attr_in2_max.dev_attr.attr, 1980 &sensor_dev_attr_in2_alarm.dev_attr.attr, 1981 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */ 1982 1983 &sensor_dev_attr_in3_input.dev_attr.attr, 1984 &sensor_dev_attr_in3_min.dev_attr.attr, 1985 &sensor_dev_attr_in3_max.dev_attr.attr, 1986 &sensor_dev_attr_in3_alarm.dev_attr.attr, 1987 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */ 1988 1989 &sensor_dev_attr_in4_input.dev_attr.attr, 1990 &sensor_dev_attr_in4_min.dev_attr.attr, 1991 &sensor_dev_attr_in4_max.dev_attr.attr, 1992 &sensor_dev_attr_in4_alarm.dev_attr.attr, 1993 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */ 1994 1995 &sensor_dev_attr_in5_input.dev_attr.attr, 1996 &sensor_dev_attr_in5_min.dev_attr.attr, 1997 &sensor_dev_attr_in5_max.dev_attr.attr, 1998 &sensor_dev_attr_in5_alarm.dev_attr.attr, 1999 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */ 2000 2001 &sensor_dev_attr_in6_input.dev_attr.attr, 2002 &sensor_dev_attr_in6_min.dev_attr.attr, 2003 &sensor_dev_attr_in6_max.dev_attr.attr, 2004 &sensor_dev_attr_in6_alarm.dev_attr.attr, 2005 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */ 2006 2007 &sensor_dev_attr_in7_input.dev_attr.attr, 2008 &sensor_dev_attr_in7_min.dev_attr.attr, 2009 &sensor_dev_attr_in7_max.dev_attr.attr, 2010 &sensor_dev_attr_in7_alarm.dev_attr.attr, 2011 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */ 2012 2013 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */ 2014 &sensor_dev_attr_in9_input.dev_attr.attr, /* 41 */ 2015 &sensor_dev_attr_in10_input.dev_attr.attr, /* 41 */ 2016 &sensor_dev_attr_in11_input.dev_attr.attr, /* 41 */ 2017 &sensor_dev_attr_in12_input.dev_attr.attr, /* 41 */ 2018 }; 2019 2020 static const struct attribute_group it87_group_in = { 2021 .attrs = it87_attributes_in, 2022 .is_visible = it87_in_is_visible, 2023 }; 2024 2025 static umode_t it87_temp_is_visible(struct kobject *kobj, 2026 struct attribute *attr, int index) 2027 { 2028 struct device *dev = container_of(kobj, struct device, kobj); 2029 struct it87_data *data = dev_get_drvdata(dev); 2030 int i = index / 7; /* temperature index */ 2031 int a = index % 7; /* attribute index */ 2032 2033 if (index >= 21) { 2034 i = index - 21 + 3; 2035 a = 0; 2036 } 2037 2038 if (!(data->has_temp & BIT(i))) 2039 return 0; 2040 2041 if (a == 5 && !has_temp_offset(data)) 2042 return 0; 2043 2044 if (a == 6 && !data->has_beep) 2045 return 0; 2046 2047 return attr->mode; 2048 } 2049 2050 static struct attribute *it87_attributes_temp[] = { 2051 &sensor_dev_attr_temp1_input.dev_attr.attr, 2052 &sensor_dev_attr_temp1_max.dev_attr.attr, 2053 &sensor_dev_attr_temp1_min.dev_attr.attr, 2054 &sensor_dev_attr_temp1_type.dev_attr.attr, 2055 &sensor_dev_attr_temp1_alarm.dev_attr.attr, 2056 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */ 2057 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */ 2058 2059 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */ 2060 &sensor_dev_attr_temp2_max.dev_attr.attr, 2061 &sensor_dev_attr_temp2_min.dev_attr.attr, 2062 &sensor_dev_attr_temp2_type.dev_attr.attr, 2063 &sensor_dev_attr_temp2_alarm.dev_attr.attr, 2064 &sensor_dev_attr_temp2_offset.dev_attr.attr, 2065 &sensor_dev_attr_temp2_beep.dev_attr.attr, 2066 2067 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */ 2068 &sensor_dev_attr_temp3_max.dev_attr.attr, 2069 &sensor_dev_attr_temp3_min.dev_attr.attr, 2070 &sensor_dev_attr_temp3_type.dev_attr.attr, 2071 &sensor_dev_attr_temp3_alarm.dev_attr.attr, 2072 &sensor_dev_attr_temp3_offset.dev_attr.attr, 2073 &sensor_dev_attr_temp3_beep.dev_attr.attr, 2074 2075 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */ 2076 &sensor_dev_attr_temp5_input.dev_attr.attr, 2077 &sensor_dev_attr_temp6_input.dev_attr.attr, 2078 NULL 2079 }; 2080 2081 static const struct attribute_group it87_group_temp = { 2082 .attrs = it87_attributes_temp, 2083 .is_visible = it87_temp_is_visible, 2084 }; 2085 2086 static umode_t it87_is_visible(struct kobject *kobj, 2087 struct attribute *attr, int index) 2088 { 2089 struct device *dev = container_of(kobj, struct device, kobj); 2090 struct it87_data *data = dev_get_drvdata(dev); 2091 2092 if ((index == 2 || index == 3) && !data->has_vid) 2093 return 0; 2094 2095 if (index > 3 && !(data->in_internal & BIT(index - 4))) 2096 return 0; 2097 2098 return attr->mode; 2099 } 2100 2101 static struct attribute *it87_attributes[] = { 2102 &dev_attr_alarms.attr, 2103 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, 2104 &dev_attr_vrm.attr, /* 2 */ 2105 &dev_attr_cpu0_vid.attr, /* 3 */ 2106 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */ 2107 &sensor_dev_attr_in7_label.dev_attr.attr, 2108 &sensor_dev_attr_in8_label.dev_attr.attr, 2109 &sensor_dev_attr_in9_label.dev_attr.attr, 2110 NULL 2111 }; 2112 2113 static const struct attribute_group it87_group = { 2114 .attrs = it87_attributes, 2115 .is_visible = it87_is_visible, 2116 }; 2117 2118 static umode_t it87_fan_is_visible(struct kobject *kobj, 2119 struct attribute *attr, int index) 2120 { 2121 struct device *dev = container_of(kobj, struct device, kobj); 2122 struct it87_data *data = dev_get_drvdata(dev); 2123 int i = index / 5; /* fan index */ 2124 int a = index % 5; /* attribute index */ 2125 2126 if (index >= 15) { /* fan 4..6 don't have divisor attributes */ 2127 i = (index - 15) / 4 + 3; 2128 a = (index - 15) % 4; 2129 } 2130 2131 if (!(data->has_fan & BIT(i))) 2132 return 0; 2133 2134 if (a == 3) { /* beep */ 2135 if (!data->has_beep) 2136 return 0; 2137 /* first fan beep attribute is writable */ 2138 if (i == __ffs(data->has_fan)) 2139 return attr->mode | S_IWUSR; 2140 } 2141 2142 if (a == 4 && has_16bit_fans(data)) /* divisor */ 2143 return 0; 2144 2145 return attr->mode; 2146 } 2147 2148 static struct attribute *it87_attributes_fan[] = { 2149 &sensor_dev_attr_fan1_input.dev_attr.attr, 2150 &sensor_dev_attr_fan1_min.dev_attr.attr, 2151 &sensor_dev_attr_fan1_alarm.dev_attr.attr, 2152 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */ 2153 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */ 2154 2155 &sensor_dev_attr_fan2_input.dev_attr.attr, 2156 &sensor_dev_attr_fan2_min.dev_attr.attr, 2157 &sensor_dev_attr_fan2_alarm.dev_attr.attr, 2158 &sensor_dev_attr_fan2_beep.dev_attr.attr, 2159 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */ 2160 2161 &sensor_dev_attr_fan3_input.dev_attr.attr, 2162 &sensor_dev_attr_fan3_min.dev_attr.attr, 2163 &sensor_dev_attr_fan3_alarm.dev_attr.attr, 2164 &sensor_dev_attr_fan3_beep.dev_attr.attr, 2165 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */ 2166 2167 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */ 2168 &sensor_dev_attr_fan4_min.dev_attr.attr, 2169 &sensor_dev_attr_fan4_alarm.dev_attr.attr, 2170 &sensor_dev_attr_fan4_beep.dev_attr.attr, 2171 2172 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */ 2173 &sensor_dev_attr_fan5_min.dev_attr.attr, 2174 &sensor_dev_attr_fan5_alarm.dev_attr.attr, 2175 &sensor_dev_attr_fan5_beep.dev_attr.attr, 2176 2177 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */ 2178 &sensor_dev_attr_fan6_min.dev_attr.attr, 2179 &sensor_dev_attr_fan6_alarm.dev_attr.attr, 2180 &sensor_dev_attr_fan6_beep.dev_attr.attr, 2181 NULL 2182 }; 2183 2184 static const struct attribute_group it87_group_fan = { 2185 .attrs = it87_attributes_fan, 2186 .is_visible = it87_fan_is_visible, 2187 }; 2188 2189 static umode_t it87_pwm_is_visible(struct kobject *kobj, 2190 struct attribute *attr, int index) 2191 { 2192 struct device *dev = container_of(kobj, struct device, kobj); 2193 struct it87_data *data = dev_get_drvdata(dev); 2194 int i = index / 4; /* pwm index */ 2195 int a = index % 4; /* attribute index */ 2196 2197 if (!(data->has_pwm & BIT(i))) 2198 return 0; 2199 2200 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */ 2201 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data))) 2202 return attr->mode | S_IWUSR; 2203 2204 /* pwm2_freq is writable if there are two pwm frequency selects */ 2205 if (has_pwm_freq2(data) && i == 1 && a == 2) 2206 return attr->mode | S_IWUSR; 2207 2208 return attr->mode; 2209 } 2210 2211 static struct attribute *it87_attributes_pwm[] = { 2212 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 2213 &sensor_dev_attr_pwm1.dev_attr.attr, 2214 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 2215 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr, 2216 2217 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 2218 &sensor_dev_attr_pwm2.dev_attr.attr, 2219 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 2220 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr, 2221 2222 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 2223 &sensor_dev_attr_pwm3.dev_attr.attr, 2224 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 2225 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr, 2226 2227 &sensor_dev_attr_pwm4_enable.dev_attr.attr, 2228 &sensor_dev_attr_pwm4.dev_attr.attr, 2229 &sensor_dev_attr_pwm4_freq.dev_attr.attr, 2230 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr, 2231 2232 &sensor_dev_attr_pwm5_enable.dev_attr.attr, 2233 &sensor_dev_attr_pwm5.dev_attr.attr, 2234 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 2235 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr, 2236 2237 &sensor_dev_attr_pwm6_enable.dev_attr.attr, 2238 &sensor_dev_attr_pwm6.dev_attr.attr, 2239 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 2240 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr, 2241 2242 NULL 2243 }; 2244 2245 static const struct attribute_group it87_group_pwm = { 2246 .attrs = it87_attributes_pwm, 2247 .is_visible = it87_pwm_is_visible, 2248 }; 2249 2250 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj, 2251 struct attribute *attr, int index) 2252 { 2253 struct device *dev = container_of(kobj, struct device, kobj); 2254 struct it87_data *data = dev_get_drvdata(dev); 2255 int i = index / 11; /* pwm index */ 2256 int a = index % 11; /* attribute index */ 2257 2258 if (index >= 33) { /* pwm 4..6 */ 2259 i = (index - 33) / 6 + 3; 2260 a = (index - 33) % 6 + 4; 2261 } 2262 2263 if (!(data->has_pwm & BIT(i))) 2264 return 0; 2265 2266 if (has_newer_autopwm(data)) { 2267 if (a < 4) /* no auto point pwm */ 2268 return 0; 2269 if (a == 8) /* no auto_point4 */ 2270 return 0; 2271 } 2272 if (has_old_autopwm(data)) { 2273 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */ 2274 return 0; 2275 } 2276 2277 return attr->mode; 2278 } 2279 2280 static struct attribute *it87_attributes_auto_pwm[] = { 2281 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 2282 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, 2283 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr, 2284 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr, 2285 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr, 2286 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr, 2287 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr, 2288 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr, 2289 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr, 2290 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr, 2291 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr, 2292 2293 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */ 2294 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, 2295 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr, 2296 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr, 2297 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr, 2298 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr, 2299 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr, 2300 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr, 2301 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr, 2302 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr, 2303 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr, 2304 2305 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */ 2306 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, 2307 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr, 2308 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr, 2309 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr, 2310 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr, 2311 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr, 2312 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr, 2313 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr, 2314 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr, 2315 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr, 2316 2317 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */ 2318 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr, 2319 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr, 2320 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr, 2321 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr, 2322 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr, 2323 2324 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr, 2325 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr, 2326 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr, 2327 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr, 2328 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr, 2329 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr, 2330 2331 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr, 2332 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr, 2333 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr, 2334 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr, 2335 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr, 2336 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr, 2337 2338 NULL, 2339 }; 2340 2341 static const struct attribute_group it87_group_auto_pwm = { 2342 .attrs = it87_attributes_auto_pwm, 2343 .is_visible = it87_auto_pwm_is_visible, 2344 }; 2345 2346 /* SuperIO detection - will change isa_address if a chip is found */ 2347 static int __init it87_find(int sioaddr, unsigned short *address, 2348 struct it87_sio_data *sio_data) 2349 { 2350 int err; 2351 u16 chip_type; 2352 const char *board_vendor, *board_name; 2353 const struct it87_devices *config; 2354 2355 err = superio_enter(sioaddr); 2356 if (err) 2357 return err; 2358 2359 err = -ENODEV; 2360 chip_type = force_id ? force_id : superio_inw(sioaddr, DEVID); 2361 2362 switch (chip_type) { 2363 case IT8705F_DEVID: 2364 sio_data->type = it87; 2365 break; 2366 case IT8712F_DEVID: 2367 sio_data->type = it8712; 2368 break; 2369 case IT8716F_DEVID: 2370 case IT8726F_DEVID: 2371 sio_data->type = it8716; 2372 break; 2373 case IT8718F_DEVID: 2374 sio_data->type = it8718; 2375 break; 2376 case IT8720F_DEVID: 2377 sio_data->type = it8720; 2378 break; 2379 case IT8721F_DEVID: 2380 sio_data->type = it8721; 2381 break; 2382 case IT8728F_DEVID: 2383 sio_data->type = it8728; 2384 break; 2385 case IT8732F_DEVID: 2386 sio_data->type = it8732; 2387 break; 2388 case IT8771E_DEVID: 2389 sio_data->type = it8771; 2390 break; 2391 case IT8772E_DEVID: 2392 sio_data->type = it8772; 2393 break; 2394 case IT8781F_DEVID: 2395 sio_data->type = it8781; 2396 break; 2397 case IT8782F_DEVID: 2398 sio_data->type = it8782; 2399 break; 2400 case IT8783E_DEVID: 2401 sio_data->type = it8783; 2402 break; 2403 case IT8786E_DEVID: 2404 sio_data->type = it8786; 2405 break; 2406 case IT8790E_DEVID: 2407 sio_data->type = it8790; 2408 break; 2409 case IT8603E_DEVID: 2410 case IT8623E_DEVID: 2411 sio_data->type = it8603; 2412 break; 2413 case IT8620E_DEVID: 2414 sio_data->type = it8620; 2415 break; 2416 case IT8628E_DEVID: 2417 sio_data->type = it8628; 2418 break; 2419 case 0xffff: /* No device at all */ 2420 goto exit; 2421 default: 2422 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type); 2423 goto exit; 2424 } 2425 2426 superio_select(sioaddr, PME); 2427 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) { 2428 pr_info("Device not activated, skipping\n"); 2429 goto exit; 2430 } 2431 2432 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1); 2433 if (*address == 0) { 2434 pr_info("Base address not set, skipping\n"); 2435 goto exit; 2436 } 2437 2438 err = 0; 2439 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f; 2440 pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type, 2441 it87_devices[sio_data->type].suffix, 2442 *address, sio_data->revision); 2443 2444 config = &it87_devices[sio_data->type]; 2445 2446 /* in7 (VSB or VCCH5V) is always internal on some chips */ 2447 if (has_in7_internal(config)) 2448 sio_data->internal |= BIT(1); 2449 2450 /* in8 (Vbat) is always internal */ 2451 sio_data->internal |= BIT(2); 2452 2453 /* in9 (AVCC3), always internal if supported */ 2454 if (has_avcc3(config)) 2455 sio_data->internal |= BIT(3); /* in9 is AVCC */ 2456 else 2457 sio_data->skip_in |= BIT(9); 2458 2459 if (!has_six_pwm(config)) 2460 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5); 2461 2462 if (!has_vid(config)) 2463 sio_data->skip_vid = 1; 2464 2465 /* Read GPIO config and VID value from LDN 7 (GPIO) */ 2466 if (sio_data->type == it87) { 2467 /* The IT8705F has a different LD number for GPIO */ 2468 superio_select(sioaddr, 5); 2469 sio_data->beep_pin = superio_inb(sioaddr, 2470 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2471 } else if (sio_data->type == it8783) { 2472 int reg25, reg27, reg2a, reg2c, regef; 2473 2474 superio_select(sioaddr, GPIO); 2475 2476 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 2477 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2478 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG); 2479 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 2480 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG); 2481 2482 /* Check if fan3 is there or not */ 2483 if ((reg27 & BIT(0)) || !(reg2c & BIT(2))) 2484 sio_data->skip_fan |= BIT(2); 2485 if ((reg25 & BIT(4)) || 2486 (!(reg2a & BIT(1)) && (regef & BIT(0)))) 2487 sio_data->skip_pwm |= BIT(2); 2488 2489 /* Check if fan2 is there or not */ 2490 if (reg27 & BIT(7)) 2491 sio_data->skip_fan |= BIT(1); 2492 if (reg27 & BIT(3)) 2493 sio_data->skip_pwm |= BIT(1); 2494 2495 /* VIN5 */ 2496 if ((reg27 & BIT(0)) || (reg2c & BIT(2))) 2497 sio_data->skip_in |= BIT(5); /* No VIN5 */ 2498 2499 /* VIN6 */ 2500 if (reg27 & BIT(1)) 2501 sio_data->skip_in |= BIT(6); /* No VIN6 */ 2502 2503 /* 2504 * VIN7 2505 * Does not depend on bit 2 of Reg2C, contrary to datasheet. 2506 */ 2507 if (reg27 & BIT(2)) { 2508 /* 2509 * The data sheet is a bit unclear regarding the 2510 * internal voltage divider for VCCH5V. It says 2511 * "This bit enables and switches VIN7 (pin 91) to the 2512 * internal voltage divider for VCCH5V". 2513 * This is different to other chips, where the internal 2514 * voltage divider would connect VIN7 to an internal 2515 * voltage source. Maybe that is the case here as well. 2516 * 2517 * Since we don't know for sure, re-route it if that is 2518 * not the case, and ask the user to report if the 2519 * resulting voltage is sane. 2520 */ 2521 if (!(reg2c & BIT(1))) { 2522 reg2c |= BIT(1); 2523 superio_outb(sioaddr, IT87_SIO_PINX2_REG, 2524 reg2c); 2525 pr_notice("Routing internal VCCH5V to in7.\n"); 2526 } 2527 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n"); 2528 pr_notice("Please report if it displays a reasonable voltage.\n"); 2529 } 2530 2531 if (reg2c & BIT(0)) 2532 sio_data->internal |= BIT(0); 2533 if (reg2c & BIT(1)) 2534 sio_data->internal |= BIT(1); 2535 2536 sio_data->beep_pin = superio_inb(sioaddr, 2537 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2538 } else if (sio_data->type == it8603) { 2539 int reg27, reg29; 2540 2541 superio_select(sioaddr, GPIO); 2542 2543 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2544 2545 /* Check if fan3 is there or not */ 2546 if (reg27 & BIT(6)) 2547 sio_data->skip_pwm |= BIT(2); 2548 if (reg27 & BIT(7)) 2549 sio_data->skip_fan |= BIT(2); 2550 2551 /* Check if fan2 is there or not */ 2552 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2553 if (reg29 & BIT(1)) 2554 sio_data->skip_pwm |= BIT(1); 2555 if (reg29 & BIT(2)) 2556 sio_data->skip_fan |= BIT(1); 2557 2558 sio_data->skip_in |= BIT(5); /* No VIN5 */ 2559 sio_data->skip_in |= BIT(6); /* No VIN6 */ 2560 2561 sio_data->beep_pin = superio_inb(sioaddr, 2562 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2563 } else if (sio_data->type == it8620 || sio_data->type == it8628) { 2564 int reg; 2565 2566 superio_select(sioaddr, GPIO); 2567 2568 /* Check for pwm5 */ 2569 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 2570 if (reg & BIT(6)) 2571 sio_data->skip_pwm |= BIT(4); 2572 2573 /* Check for fan4, fan5 */ 2574 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); 2575 if (!(reg & BIT(5))) 2576 sio_data->skip_fan |= BIT(3); 2577 if (!(reg & BIT(4))) 2578 sio_data->skip_fan |= BIT(4); 2579 2580 /* Check for pwm3, fan3 */ 2581 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2582 if (reg & BIT(6)) 2583 sio_data->skip_pwm |= BIT(2); 2584 if (reg & BIT(7)) 2585 sio_data->skip_fan |= BIT(2); 2586 2587 /* Check for pwm4 */ 2588 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG); 2589 if (!(reg & BIT(2))) 2590 sio_data->skip_pwm |= BIT(3); 2591 2592 /* Check for pwm2, fan2 */ 2593 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2594 if (reg & BIT(1)) 2595 sio_data->skip_pwm |= BIT(1); 2596 if (reg & BIT(2)) 2597 sio_data->skip_fan |= BIT(1); 2598 /* Check for pwm6, fan6 */ 2599 if (!(reg & BIT(7))) { 2600 sio_data->skip_pwm |= BIT(5); 2601 sio_data->skip_fan |= BIT(5); 2602 } 2603 2604 sio_data->beep_pin = superio_inb(sioaddr, 2605 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2606 } else { 2607 int reg; 2608 bool uart6; 2609 2610 superio_select(sioaddr, GPIO); 2611 2612 /* Check for fan4, fan5 */ 2613 if (has_five_fans(config)) { 2614 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); 2615 switch (sio_data->type) { 2616 case it8718: 2617 if (reg & BIT(5)) 2618 sio_data->skip_fan |= BIT(3); 2619 if (reg & BIT(4)) 2620 sio_data->skip_fan |= BIT(4); 2621 break; 2622 case it8720: 2623 case it8721: 2624 case it8728: 2625 if (!(reg & BIT(5))) 2626 sio_data->skip_fan |= BIT(3); 2627 if (!(reg & BIT(4))) 2628 sio_data->skip_fan |= BIT(4); 2629 break; 2630 default: 2631 break; 2632 } 2633 } 2634 2635 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2636 if (!sio_data->skip_vid) { 2637 /* We need at least 4 VID pins */ 2638 if (reg & 0x0f) { 2639 pr_info("VID is disabled (pins used for GPIO)\n"); 2640 sio_data->skip_vid = 1; 2641 } 2642 } 2643 2644 /* Check if fan3 is there or not */ 2645 if (reg & BIT(6)) 2646 sio_data->skip_pwm |= BIT(2); 2647 if (reg & BIT(7)) 2648 sio_data->skip_fan |= BIT(2); 2649 2650 /* Check if fan2 is there or not */ 2651 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2652 if (reg & BIT(1)) 2653 sio_data->skip_pwm |= BIT(1); 2654 if (reg & BIT(2)) 2655 sio_data->skip_fan |= BIT(1); 2656 2657 if ((sio_data->type == it8718 || sio_data->type == it8720) && 2658 !(sio_data->skip_vid)) 2659 sio_data->vid_value = superio_inb(sioaddr, 2660 IT87_SIO_VID_REG); 2661 2662 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 2663 2664 uart6 = sio_data->type == it8782 && (reg & BIT(2)); 2665 2666 /* 2667 * The IT8720F has no VIN7 pin, so VCCH should always be 2668 * routed internally to VIN7 with an internal divider. 2669 * Curiously, there still is a configuration bit to control 2670 * this, which means it can be set incorrectly. And even 2671 * more curiously, many boards out there are improperly 2672 * configured, even though the IT8720F datasheet claims 2673 * that the internal routing of VCCH to VIN7 is the default 2674 * setting. So we force the internal routing in this case. 2675 * 2676 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins. 2677 * If UART6 is enabled, re-route VIN7 to the internal divider 2678 * if that is not already the case. 2679 */ 2680 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) { 2681 reg |= BIT(1); 2682 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg); 2683 pr_notice("Routing internal VCCH to in7\n"); 2684 } 2685 if (reg & BIT(0)) 2686 sio_data->internal |= BIT(0); 2687 if (reg & BIT(1)) 2688 sio_data->internal |= BIT(1); 2689 2690 /* 2691 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7. 2692 * While VIN7 can be routed to the internal voltage divider, 2693 * VIN5 and VIN6 are not available if UART6 is enabled. 2694 * 2695 * Also, temp3 is not available if UART6 is enabled and TEMPIN3 2696 * is the temperature source. Since we can not read the 2697 * temperature source here, skip_temp is preliminary. 2698 */ 2699 if (uart6) { 2700 sio_data->skip_in |= BIT(5) | BIT(6); 2701 sio_data->skip_temp |= BIT(2); 2702 } 2703 2704 sio_data->beep_pin = superio_inb(sioaddr, 2705 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2706 } 2707 if (sio_data->beep_pin) 2708 pr_info("Beeping is supported\n"); 2709 2710 /* Disable specific features based on DMI strings */ 2711 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR); 2712 board_name = dmi_get_system_info(DMI_BOARD_NAME); 2713 if (board_vendor && board_name) { 2714 if (strcmp(board_vendor, "nVIDIA") == 0 && 2715 strcmp(board_name, "FN68PT") == 0) { 2716 /* 2717 * On the Shuttle SN68PT, FAN_CTL2 is apparently not 2718 * connected to a fan, but to something else. One user 2719 * has reported instant system power-off when changing 2720 * the PWM2 duty cycle, so we disable it. 2721 * I use the board name string as the trigger in case 2722 * the same board is ever used in other systems. 2723 */ 2724 pr_info("Disabling pwm2 due to hardware constraints\n"); 2725 sio_data->skip_pwm = BIT(1); 2726 } 2727 } 2728 2729 exit: 2730 superio_exit(sioaddr); 2731 return err; 2732 } 2733 2734 /* Called when we have found a new IT87. */ 2735 static void it87_init_device(struct platform_device *pdev) 2736 { 2737 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); 2738 struct it87_data *data = platform_get_drvdata(pdev); 2739 int tmp, i; 2740 u8 mask; 2741 2742 /* 2743 * For each PWM channel: 2744 * - If it is in automatic mode, setting to manual mode should set 2745 * the fan to full speed by default. 2746 * - If it is in manual mode, we need a mapping to temperature 2747 * channels to use when later setting to automatic mode later. 2748 * Use a 1:1 mapping by default (we are clueless.) 2749 * In both cases, the value can (and should) be changed by the user 2750 * prior to switching to a different mode. 2751 * Note that this is no longer needed for the IT8721F and later, as 2752 * these have separate registers for the temperature mapping and the 2753 * manual duty cycle. 2754 */ 2755 for (i = 0; i < NUM_AUTO_PWM; i++) { 2756 data->pwm_temp_map[i] = i; 2757 data->pwm_duty[i] = 0x7f; /* Full speed */ 2758 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */ 2759 } 2760 2761 /* 2762 * Some chips seem to have default value 0xff for all limit 2763 * registers. For low voltage limits it makes no sense and triggers 2764 * alarms, so change to 0 instead. For high temperature limits, it 2765 * means -1 degree C, which surprisingly doesn't trigger an alarm, 2766 * but is still confusing, so change to 127 degrees C. 2767 */ 2768 for (i = 0; i < NUM_VIN_LIMIT; i++) { 2769 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i)); 2770 if (tmp == 0xff) 2771 it87_write_value(data, IT87_REG_VIN_MIN(i), 0); 2772 } 2773 for (i = 0; i < NUM_TEMP_LIMIT; i++) { 2774 tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i)); 2775 if (tmp == 0xff) 2776 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127); 2777 } 2778 2779 /* 2780 * Temperature channels are not forcibly enabled, as they can be 2781 * set to two different sensor types and we can't guess which one 2782 * is correct for a given system. These channels can be enabled at 2783 * run-time through the temp{1-3}_type sysfs accessors if needed. 2784 */ 2785 2786 /* Check if voltage monitors are reset manually or by some reason */ 2787 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE); 2788 if ((tmp & 0xff) == 0) { 2789 /* Enable all voltage monitors */ 2790 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff); 2791 } 2792 2793 /* Check if tachometers are reset manually or by some reason */ 2794 mask = 0x70 & ~(sio_data->skip_fan << 4); 2795 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); 2796 if ((data->fan_main_ctrl & mask) == 0) { 2797 /* Enable all fan tachometers */ 2798 data->fan_main_ctrl |= mask; 2799 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 2800 data->fan_main_ctrl); 2801 } 2802 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07; 2803 2804 tmp = it87_read_value(data, IT87_REG_FAN_16BIT); 2805 2806 /* Set tachometers to 16-bit mode if needed */ 2807 if (has_fan16_config(data)) { 2808 if (~tmp & 0x07 & data->has_fan) { 2809 dev_dbg(&pdev->dev, 2810 "Setting fan1-3 to 16-bit mode\n"); 2811 it87_write_value(data, IT87_REG_FAN_16BIT, 2812 tmp | 0x07); 2813 } 2814 } 2815 2816 /* Check for additional fans */ 2817 if (has_five_fans(data)) { 2818 if (tmp & BIT(4)) 2819 data->has_fan |= BIT(3); /* fan4 enabled */ 2820 if (tmp & BIT(5)) 2821 data->has_fan |= BIT(4); /* fan5 enabled */ 2822 if (has_six_fans(data) && (tmp & BIT(2))) 2823 data->has_fan |= BIT(5); /* fan6 enabled */ 2824 } 2825 2826 /* Fan input pins may be used for alternative functions */ 2827 data->has_fan &= ~sio_data->skip_fan; 2828 2829 /* Check if pwm5, pwm6 are enabled */ 2830 if (has_six_pwm(data)) { 2831 /* The following code may be IT8620E specific */ 2832 tmp = it87_read_value(data, IT87_REG_FAN_DIV); 2833 if ((tmp & 0xc0) == 0xc0) 2834 sio_data->skip_pwm |= BIT(4); 2835 if (!(tmp & BIT(3))) 2836 sio_data->skip_pwm |= BIT(5); 2837 } 2838 2839 /* Start monitoring */ 2840 it87_write_value(data, IT87_REG_CONFIG, 2841 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e) 2842 | (update_vbat ? 0x41 : 0x01)); 2843 } 2844 2845 /* Return 1 if and only if the PWM interface is safe to use */ 2846 static int it87_check_pwm(struct device *dev) 2847 { 2848 struct it87_data *data = dev_get_drvdata(dev); 2849 /* 2850 * Some BIOSes fail to correctly configure the IT87 fans. All fans off 2851 * and polarity set to active low is sign that this is the case so we 2852 * disable pwm control to protect the user. 2853 */ 2854 int tmp = it87_read_value(data, IT87_REG_FAN_CTL); 2855 2856 if ((tmp & 0x87) == 0) { 2857 if (fix_pwm_polarity) { 2858 /* 2859 * The user asks us to attempt a chip reconfiguration. 2860 * This means switching to active high polarity and 2861 * inverting all fan speed values. 2862 */ 2863 int i; 2864 u8 pwm[3]; 2865 2866 for (i = 0; i < ARRAY_SIZE(pwm); i++) 2867 pwm[i] = it87_read_value(data, 2868 IT87_REG_PWM[i]); 2869 2870 /* 2871 * If any fan is in automatic pwm mode, the polarity 2872 * might be correct, as suspicious as it seems, so we 2873 * better don't change anything (but still disable the 2874 * PWM interface). 2875 */ 2876 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) { 2877 dev_info(dev, 2878 "Reconfiguring PWM to active high polarity\n"); 2879 it87_write_value(data, IT87_REG_FAN_CTL, 2880 tmp | 0x87); 2881 for (i = 0; i < 3; i++) 2882 it87_write_value(data, 2883 IT87_REG_PWM[i], 2884 0x7f & ~pwm[i]); 2885 return 1; 2886 } 2887 2888 dev_info(dev, 2889 "PWM configuration is too broken to be fixed\n"); 2890 } 2891 2892 dev_info(dev, 2893 "Detected broken BIOS defaults, disabling PWM interface\n"); 2894 return 0; 2895 } else if (fix_pwm_polarity) { 2896 dev_info(dev, 2897 "PWM configuration looks sane, won't touch\n"); 2898 } 2899 2900 return 1; 2901 } 2902 2903 static int it87_probe(struct platform_device *pdev) 2904 { 2905 struct it87_data *data; 2906 struct resource *res; 2907 struct device *dev = &pdev->dev; 2908 struct it87_sio_data *sio_data = dev_get_platdata(dev); 2909 int enable_pwm_interface; 2910 struct device *hwmon_dev; 2911 2912 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 2913 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT, 2914 DRVNAME)) { 2915 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n", 2916 (unsigned long)res->start, 2917 (unsigned long)(res->start + IT87_EC_EXTENT - 1)); 2918 return -EBUSY; 2919 } 2920 2921 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL); 2922 if (!data) 2923 return -ENOMEM; 2924 2925 data->addr = res->start; 2926 data->type = sio_data->type; 2927 data->features = it87_devices[sio_data->type].features; 2928 data->peci_mask = it87_devices[sio_data->type].peci_mask; 2929 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask; 2930 /* 2931 * IT8705F Datasheet 0.4.1, 3h == Version G. 2932 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J. 2933 * These are the first revisions with 16-bit tachometer support. 2934 */ 2935 switch (data->type) { 2936 case it87: 2937 if (sio_data->revision >= 0x03) { 2938 data->features &= ~FEAT_OLD_AUTOPWM; 2939 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS; 2940 } 2941 break; 2942 case it8712: 2943 if (sio_data->revision >= 0x08) { 2944 data->features &= ~FEAT_OLD_AUTOPWM; 2945 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS | 2946 FEAT_FIVE_FANS; 2947 } 2948 break; 2949 default: 2950 break; 2951 } 2952 2953 /* Now, we do the remaining detection. */ 2954 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) || 2955 it87_read_value(data, IT87_REG_CHIPID) != 0x90) 2956 return -ENODEV; 2957 2958 platform_set_drvdata(pdev, data); 2959 2960 mutex_init(&data->update_lock); 2961 2962 /* Check PWM configuration */ 2963 enable_pwm_interface = it87_check_pwm(dev); 2964 2965 /* Starting with IT8721F, we handle scaling of internal voltages */ 2966 if (has_12mv_adc(data)) { 2967 if (sio_data->internal & BIT(0)) 2968 data->in_scaled |= BIT(3); /* in3 is AVCC */ 2969 if (sio_data->internal & BIT(1)) 2970 data->in_scaled |= BIT(7); /* in7 is VSB */ 2971 if (sio_data->internal & BIT(2)) 2972 data->in_scaled |= BIT(8); /* in8 is Vbat */ 2973 if (sio_data->internal & BIT(3)) 2974 data->in_scaled |= BIT(9); /* in9 is AVCC */ 2975 } else if (sio_data->type == it8781 || sio_data->type == it8782 || 2976 sio_data->type == it8783) { 2977 if (sio_data->internal & BIT(0)) 2978 data->in_scaled |= BIT(3); /* in3 is VCC5V */ 2979 if (sio_data->internal & BIT(1)) 2980 data->in_scaled |= BIT(7); /* in7 is VCCH5V */ 2981 } 2982 2983 data->has_temp = 0x07; 2984 if (sio_data->skip_temp & BIT(2)) { 2985 if (sio_data->type == it8782 && 2986 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80)) 2987 data->has_temp &= ~BIT(2); 2988 } 2989 2990 data->in_internal = sio_data->internal; 2991 data->has_in = 0x3ff & ~sio_data->skip_in; 2992 2993 if (has_six_temp(data)) { 2994 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE); 2995 2996 /* Check for additional temperature sensors */ 2997 if ((reg & 0x03) >= 0x02) 2998 data->has_temp |= BIT(3); 2999 if (((reg >> 2) & 0x03) >= 0x02) 3000 data->has_temp |= BIT(4); 3001 if (((reg >> 4) & 0x03) >= 0x02) 3002 data->has_temp |= BIT(5); 3003 3004 /* Check for additional voltage sensors */ 3005 if ((reg & 0x03) == 0x01) 3006 data->has_in |= BIT(10); 3007 if (((reg >> 2) & 0x03) == 0x01) 3008 data->has_in |= BIT(11); 3009 if (((reg >> 4) & 0x03) == 0x01) 3010 data->has_in |= BIT(12); 3011 } 3012 3013 data->has_beep = !!sio_data->beep_pin; 3014 3015 /* Initialize the IT87 chip */ 3016 it87_init_device(pdev); 3017 3018 if (!sio_data->skip_vid) { 3019 data->has_vid = true; 3020 data->vrm = vid_which_vrm(); 3021 /* VID reading from Super-I/O config space if available */ 3022 data->vid = sio_data->vid_value; 3023 } 3024 3025 /* Prepare for sysfs hooks */ 3026 data->groups[0] = &it87_group; 3027 data->groups[1] = &it87_group_in; 3028 data->groups[2] = &it87_group_temp; 3029 data->groups[3] = &it87_group_fan; 3030 3031 if (enable_pwm_interface) { 3032 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1; 3033 data->has_pwm &= ~sio_data->skip_pwm; 3034 3035 data->groups[4] = &it87_group_pwm; 3036 if (has_old_autopwm(data) || has_newer_autopwm(data)) 3037 data->groups[5] = &it87_group_auto_pwm; 3038 } 3039 3040 hwmon_dev = devm_hwmon_device_register_with_groups(dev, 3041 it87_devices[sio_data->type].name, 3042 data, data->groups); 3043 return PTR_ERR_OR_ZERO(hwmon_dev); 3044 } 3045 3046 static struct platform_driver it87_driver = { 3047 .driver = { 3048 .name = DRVNAME, 3049 }, 3050 .probe = it87_probe, 3051 }; 3052 3053 static int __init it87_device_add(int index, unsigned short address, 3054 const struct it87_sio_data *sio_data) 3055 { 3056 struct platform_device *pdev; 3057 struct resource res = { 3058 .start = address + IT87_EC_OFFSET, 3059 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1, 3060 .name = DRVNAME, 3061 .flags = IORESOURCE_IO, 3062 }; 3063 int err; 3064 3065 err = acpi_check_resource_conflict(&res); 3066 if (err) 3067 return err; 3068 3069 pdev = platform_device_alloc(DRVNAME, address); 3070 if (!pdev) 3071 return -ENOMEM; 3072 3073 err = platform_device_add_resources(pdev, &res, 1); 3074 if (err) { 3075 pr_err("Device resource addition failed (%d)\n", err); 3076 goto exit_device_put; 3077 } 3078 3079 err = platform_device_add_data(pdev, sio_data, 3080 sizeof(struct it87_sio_data)); 3081 if (err) { 3082 pr_err("Platform data allocation failed\n"); 3083 goto exit_device_put; 3084 } 3085 3086 err = platform_device_add(pdev); 3087 if (err) { 3088 pr_err("Device addition failed (%d)\n", err); 3089 goto exit_device_put; 3090 } 3091 3092 it87_pdev[index] = pdev; 3093 return 0; 3094 3095 exit_device_put: 3096 platform_device_put(pdev); 3097 return err; 3098 } 3099 3100 static int __init sm_it87_init(void) 3101 { 3102 int sioaddr[2] = { REG_2E, REG_4E }; 3103 struct it87_sio_data sio_data; 3104 unsigned short isa_address; 3105 bool found = false; 3106 int i, err; 3107 3108 err = platform_driver_register(&it87_driver); 3109 if (err) 3110 return err; 3111 3112 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) { 3113 memset(&sio_data, 0, sizeof(struct it87_sio_data)); 3114 isa_address = 0; 3115 err = it87_find(sioaddr[i], &isa_address, &sio_data); 3116 if (err || isa_address == 0) 3117 continue; 3118 3119 err = it87_device_add(i, isa_address, &sio_data); 3120 if (err) 3121 goto exit_dev_unregister; 3122 found = true; 3123 } 3124 3125 if (!found) { 3126 err = -ENODEV; 3127 goto exit_unregister; 3128 } 3129 return 0; 3130 3131 exit_dev_unregister: 3132 /* NULL check handled by platform_device_unregister */ 3133 platform_device_unregister(it87_pdev[0]); 3134 exit_unregister: 3135 platform_driver_unregister(&it87_driver); 3136 return err; 3137 } 3138 3139 static void __exit sm_it87_exit(void) 3140 { 3141 /* NULL check handled by platform_device_unregister */ 3142 platform_device_unregister(it87_pdev[1]); 3143 platform_device_unregister(it87_pdev[0]); 3144 platform_driver_unregister(&it87_driver); 3145 } 3146 3147 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>"); 3148 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver"); 3149 module_param(update_vbat, bool, 0); 3150 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value"); 3151 module_param(fix_pwm_polarity, bool, 0); 3152 MODULE_PARM_DESC(fix_pwm_polarity, 3153 "Force PWM polarity to active high (DANGEROUS)"); 3154 MODULE_LICENSE("GPL"); 3155 3156 module_init(sm_it87_init); 3157 module_exit(sm_it87_exit); 3158