1 /* 2 * hwmon-vid.c - VID/VRM/VRD voltage conversions 3 * 4 * Copyright (c) 2004 Rudolf Marek <r.marek@assembler.cz> 5 * 6 * Partly imported from i2c-vid.h of the lm_sensors project 7 * Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com> 8 * With assistance from Trent Piepho <xyzzy@speakeasy.org> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 26 27 #include <linux/module.h> 28 #include <linux/kernel.h> 29 #include <linux/hwmon-vid.h> 30 31 /* 32 * Common code for decoding VID pins. 33 * 34 * References: 35 * 36 * For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines", 37 * available at http://developer.intel.com/. 38 * 39 * For VRD 10.0 and up, "VRD x.y Design Guide", 40 * available at http://developer.intel.com/. 41 * 42 * AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094, 43 * http://support.amd.com/us/Processor_TechDocs/26094.PDF 44 * Table 74. VID Code Voltages 45 * This corresponds to an arbitrary VRM code of 24 in the functions below. 46 * These CPU models (K8 revision <= E) have 5 VID pins. See also: 47 * Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759, 48 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 49 * 50 * AMD NPT Family 0Fh Processors, AMD Publication 32559, 51 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf 52 * Table 71. VID Code Voltages 53 * This corresponds to an arbitrary VRM code of 25 in the functions below. 54 * These CPU models (K8 revision >= F) have 6 VID pins. See also: 55 * Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610, 56 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 57 * 58 * The 17 specification is in fact Intel Mobile Voltage Positioning - 59 * (IMVP-II). You can find more information in the datasheet of Max1718 60 * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452 61 * 62 * The 13 specification corresponds to the Intel Pentium M series. There 63 * doesn't seem to be any named specification for these. The conversion 64 * tables are detailed directly in the various Pentium M datasheets: 65 * http://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm 66 * 67 * The 14 specification corresponds to Intel Core series. There 68 * doesn't seem to be any named specification for these. The conversion 69 * tables are detailed directly in the various Pentium Core datasheets: 70 * http://www.intel.com/design/mobile/datashts/309221.htm 71 * 72 * The 110 (VRM 11) specification corresponds to Intel Conroe based series. 73 * http://www.intel.com/design/processor/applnots/313214.htm 74 */ 75 76 /* 77 * vrm is the VRM/VRD document version multiplied by 10. 78 * val is the 4-bit or more VID code. 79 * Returned value is in mV to avoid floating point in the kernel. 80 * Some VID have some bits in uV scale, this is rounded to mV. 81 */ 82 int vid_from_reg(int val, u8 vrm) 83 { 84 int vid; 85 86 switch(vrm) { 87 88 case 100: /* VRD 10.0 */ 89 /* compute in uV, round to mV */ 90 val &= 0x3f; 91 if((val & 0x1f) == 0x1f) 92 return 0; 93 if((val & 0x1f) <= 0x09 || val == 0x0a) 94 vid = 1087500 - (val & 0x1f) * 25000; 95 else 96 vid = 1862500 - (val & 0x1f) * 25000; 97 if(val & 0x20) 98 vid -= 12500; 99 return((vid + 500) / 1000); 100 101 case 110: /* Intel Conroe */ 102 /* compute in uV, round to mV */ 103 val &= 0xff; 104 if (val < 0x02 || val > 0xb2) 105 return 0; 106 return((1600000 - (val - 2) * 6250 + 500) / 1000); 107 108 case 24: /* Athlon64 & Opteron */ 109 val &= 0x1f; 110 if (val == 0x1f) 111 return 0; 112 /* fall through */ 113 case 25: /* AMD NPT 0Fh */ 114 val &= 0x3f; 115 return (val < 32) ? 1550 - 25 * val 116 : 775 - (25 * (val - 31)) / 2; 117 118 case 91: /* VRM 9.1 */ 119 case 90: /* VRM 9.0 */ 120 val &= 0x1f; 121 return(val == 0x1f ? 0 : 122 1850 - val * 25); 123 124 case 85: /* VRM 8.5 */ 125 val &= 0x1f; 126 return((val & 0x10 ? 25 : 0) + 127 ((val & 0x0f) > 0x04 ? 2050 : 1250) - 128 ((val & 0x0f) * 50)); 129 130 case 84: /* VRM 8.4 */ 131 val &= 0x0f; 132 /* fall through */ 133 case 82: /* VRM 8.2 */ 134 val &= 0x1f; 135 return(val == 0x1f ? 0 : 136 val & 0x10 ? 5100 - (val) * 100 : 137 2050 - (val) * 50); 138 case 17: /* Intel IMVP-II */ 139 val &= 0x1f; 140 return(val & 0x10 ? 975 - (val & 0xF) * 25 : 141 1750 - val * 50); 142 case 13: 143 case 131: 144 val &= 0x3f; 145 /* Exception for Eden ULV 500 MHz */ 146 if (vrm == 131 && val == 0x3f) 147 val++; 148 return(1708 - val * 16); 149 case 14: /* Intel Core */ 150 /* compute in uV, round to mV */ 151 val &= 0x7f; 152 return(val > 0x77 ? 0 : (1500000 - (val * 12500) + 500) / 1000); 153 default: /* report 0 for unknown */ 154 if (vrm) 155 pr_warn("Requested unsupported VRM version (%u)\n", 156 (unsigned int)vrm); 157 return 0; 158 } 159 } 160 161 162 /* 163 * After this point is the code to automatically determine which 164 * VRM/VRD specification should be used depending on the CPU. 165 */ 166 167 struct vrm_model { 168 u8 vendor; 169 u8 eff_family; 170 u8 eff_model; 171 u8 eff_stepping; 172 u8 vrm_type; 173 }; 174 175 #define ANY 0xFF 176 177 #ifdef CONFIG_X86 178 179 /* 180 * The stepping parameter is highest acceptable stepping for current line. 181 * The model match must be exact for 4-bit values. For model values 0x10 182 * and above (extended model), all models below the parameter will match. 183 */ 184 185 static struct vrm_model vrm_models[] = { 186 {X86_VENDOR_AMD, 0x6, ANY, ANY, 90}, /* Athlon Duron etc */ 187 {X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24}, /* Athlon 64, Opteron */ 188 /* In theory, all NPT family 0Fh processors have 6 VID pins and should 189 thus use vrm 25, however in practice not all mainboards route the 190 6th VID pin because it is never needed. So we use the 5 VID pin 191 variant (vrm 24) for the models which exist today. */ 192 {X86_VENDOR_AMD, 0xF, 0x7F, ANY, 24}, /* NPT family 0Fh */ 193 {X86_VENDOR_AMD, 0xF, ANY, ANY, 25}, /* future fam. 0Fh */ 194 {X86_VENDOR_AMD, 0x10, ANY, ANY, 25}, /* NPT family 10h */ 195 196 {X86_VENDOR_INTEL, 0x6, 0x9, ANY, 13}, /* Pentium M (130 nm) */ 197 {X86_VENDOR_INTEL, 0x6, 0xB, ANY, 85}, /* Tualatin */ 198 {X86_VENDOR_INTEL, 0x6, 0xD, ANY, 13}, /* Pentium M (90 nm) */ 199 {X86_VENDOR_INTEL, 0x6, 0xE, ANY, 14}, /* Intel Core (65 nm) */ 200 {X86_VENDOR_INTEL, 0x6, 0xF, ANY, 110}, /* Intel Conroe */ 201 {X86_VENDOR_INTEL, 0x6, ANY, ANY, 82}, /* any P6 */ 202 {X86_VENDOR_INTEL, 0xF, 0x0, ANY, 90}, /* P4 */ 203 {X86_VENDOR_INTEL, 0xF, 0x1, ANY, 90}, /* P4 Willamette */ 204 {X86_VENDOR_INTEL, 0xF, 0x2, ANY, 90}, /* P4 Northwood */ 205 {X86_VENDOR_INTEL, 0xF, ANY, ANY, 100}, /* Prescott and above assume VRD 10 */ 206 207 {X86_VENDOR_CENTAUR, 0x6, 0x7, ANY, 85}, /* Eden ESP/Ezra */ 208 {X86_VENDOR_CENTAUR, 0x6, 0x8, 0x7, 85}, /* Ezra T */ 209 {X86_VENDOR_CENTAUR, 0x6, 0x9, 0x7, 85}, /* Nehemiah */ 210 {X86_VENDOR_CENTAUR, 0x6, 0x9, ANY, 17}, /* C3-M, Eden-N */ 211 {X86_VENDOR_CENTAUR, 0x6, 0xA, 0x7, 0}, /* No information */ 212 {X86_VENDOR_CENTAUR, 0x6, 0xA, ANY, 13}, /* C7-M, C7, Eden (Esther) */ 213 {X86_VENDOR_CENTAUR, 0x6, 0xD, ANY, 134}, /* C7-D, C7-M, C7, Eden (Esther) */ 214 215 {X86_VENDOR_UNKNOWN, ANY, ANY, ANY, 0} /* stop here */ 216 }; 217 218 /* 219 * Special case for VIA model D: there are two different possible 220 * VID tables, so we have to figure out first, which one must be 221 * used. This resolves temporary drm value 134 to 14 (Intel Core 222 * 7-bit VID), 13 (Pentium M 6-bit VID) or 131 (Pentium M 6-bit VID 223 * + quirk for Eden ULV 500 MHz). 224 * Note: something similar might be needed for model A, I'm not sure. 225 */ 226 static u8 get_via_model_d_vrm(void) 227 { 228 unsigned int vid, brand, dummy; 229 static const char *brands[4] = { 230 "C7-M", "C7", "Eden", "C7-D" 231 }; 232 233 rdmsr(0x198, dummy, vid); 234 vid &= 0xff; 235 236 rdmsr(0x1154, brand, dummy); 237 brand = ((brand >> 4) ^ (brand >> 2)) & 0x03; 238 239 if (vid > 0x3f) { 240 pr_info("Using %d-bit VID table for VIA %s CPU\n", 241 7, brands[brand]); 242 return 14; 243 } else { 244 pr_info("Using %d-bit VID table for VIA %s CPU\n", 245 6, brands[brand]); 246 /* Enable quirk for Eden */ 247 return brand == 2 ? 131 : 13; 248 } 249 } 250 251 static u8 find_vrm(u8 eff_family, u8 eff_model, u8 eff_stepping, u8 vendor) 252 { 253 int i = 0; 254 255 while (vrm_models[i].vendor!=X86_VENDOR_UNKNOWN) { 256 if (vrm_models[i].vendor==vendor) 257 if ((vrm_models[i].eff_family==eff_family) 258 && ((vrm_models[i].eff_model==eff_model) || 259 (vrm_models[i].eff_model >= 0x10 && 260 eff_model <= vrm_models[i].eff_model) || 261 (vrm_models[i].eff_model==ANY)) && 262 (eff_stepping <= vrm_models[i].eff_stepping)) 263 return vrm_models[i].vrm_type; 264 i++; 265 } 266 267 return 0; 268 } 269 270 u8 vid_which_vrm(void) 271 { 272 struct cpuinfo_x86 *c = &cpu_data(0); 273 u32 eax; 274 u8 eff_family, eff_model, eff_stepping, vrm_ret; 275 276 if (c->x86 < 6) /* Any CPU with family lower than 6 */ 277 return 0; /* doesn't have VID and/or CPUID */ 278 279 eax = cpuid_eax(1); 280 eff_family = ((eax & 0x00000F00)>>8); 281 eff_model = ((eax & 0x000000F0)>>4); 282 eff_stepping = eax & 0xF; 283 if (eff_family == 0xF) { /* use extended model & family */ 284 eff_family += ((eax & 0x00F00000)>>20); 285 eff_model += ((eax & 0x000F0000)>>16)<<4; 286 } 287 vrm_ret = find_vrm(eff_family, eff_model, eff_stepping, c->x86_vendor); 288 if (vrm_ret == 134) 289 vrm_ret = get_via_model_d_vrm(); 290 if (vrm_ret == 0) 291 pr_info("Unknown VRM version of your x86 CPU\n"); 292 return vrm_ret; 293 } 294 295 /* and now for something completely different for the non-x86 world */ 296 #else 297 u8 vid_which_vrm(void) 298 { 299 pr_info("Unknown VRM version of your CPU\n"); 300 return 0; 301 } 302 #endif 303 304 EXPORT_SYMBOL(vid_from_reg); 305 EXPORT_SYMBOL(vid_which_vrm); 306 307 MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>"); 308 309 MODULE_DESCRIPTION("hwmon-vid driver"); 310 MODULE_LICENSE("GPL"); 311