1 /* 2 * fam15h_power.c - AMD Family 15h processor power monitoring 3 * 4 * Copyright (c) 2011-2016 Advanced Micro Devices, Inc. 5 * Author: Andreas Herrmann <herrmann.der.user@googlemail.com> 6 * 7 * 8 * This driver is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This driver is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 15 * See the GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this driver; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <linux/err.h> 22 #include <linux/hwmon.h> 23 #include <linux/hwmon-sysfs.h> 24 #include <linux/init.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 #include <linux/bitops.h> 28 #include <linux/cpu.h> 29 #include <linux/cpumask.h> 30 #include <linux/time.h> 31 #include <linux/sched.h> 32 #include <asm/processor.h> 33 #include <asm/msr.h> 34 35 MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor"); 36 MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>"); 37 MODULE_LICENSE("GPL"); 38 39 /* D18F3 */ 40 #define REG_NORTHBRIDGE_CAP 0xe8 41 42 /* D18F4 */ 43 #define REG_PROCESSOR_TDP 0x1b8 44 45 /* D18F5 */ 46 #define REG_TDP_RUNNING_AVERAGE 0xe0 47 #define REG_TDP_LIMIT3 0xe8 48 49 #define FAM15H_MIN_NUM_ATTRS 2 50 #define FAM15H_NUM_GROUPS 2 51 #define MAX_CUS 8 52 53 /* set maximum interval as 1 second */ 54 #define MAX_INTERVAL 1000 55 56 #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 57 #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 58 #define MSR_F15H_PTSC 0xc0010280 59 60 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4 61 62 struct fam15h_power_data { 63 struct pci_dev *pdev; 64 unsigned int tdp_to_watts; 65 unsigned int base_tdp; 66 unsigned int processor_pwr_watts; 67 unsigned int cpu_pwr_sample_ratio; 68 const struct attribute_group *groups[FAM15H_NUM_GROUPS]; 69 struct attribute_group group; 70 /* maximum accumulated power of a compute unit */ 71 u64 max_cu_acc_power; 72 /* accumulated power of the compute units */ 73 u64 cu_acc_power[MAX_CUS]; 74 /* performance timestamp counter */ 75 u64 cpu_sw_pwr_ptsc[MAX_CUS]; 76 /* online/offline status of current compute unit */ 77 int cu_on[MAX_CUS]; 78 unsigned long power_period; 79 }; 80 81 static bool is_carrizo_or_later(void) 82 { 83 return boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60; 84 } 85 86 static ssize_t power1_input_show(struct device *dev, 87 struct device_attribute *attr, char *buf) 88 { 89 u32 val, tdp_limit, running_avg_range; 90 s32 running_avg_capture; 91 u64 curr_pwr_watts; 92 struct fam15h_power_data *data = dev_get_drvdata(dev); 93 struct pci_dev *f4 = data->pdev; 94 95 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5), 96 REG_TDP_RUNNING_AVERAGE, &val); 97 98 /* 99 * On Carrizo and later platforms, TdpRunAvgAccCap bit field 100 * is extended to 4:31 from 4:25. 101 */ 102 if (is_carrizo_or_later()) { 103 running_avg_capture = val >> 4; 104 running_avg_capture = sign_extend32(running_avg_capture, 27); 105 } else { 106 running_avg_capture = (val >> 4) & 0x3fffff; 107 running_avg_capture = sign_extend32(running_avg_capture, 21); 108 } 109 110 running_avg_range = (val & 0xf) + 1; 111 112 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5), 113 REG_TDP_LIMIT3, &val); 114 115 /* 116 * On Carrizo and later platforms, ApmTdpLimit bit field 117 * is extended to 16:31 from 16:28. 118 */ 119 if (is_carrizo_or_later()) 120 tdp_limit = val >> 16; 121 else 122 tdp_limit = (val >> 16) & 0x1fff; 123 124 curr_pwr_watts = ((u64)(tdp_limit + 125 data->base_tdp)) << running_avg_range; 126 curr_pwr_watts -= running_avg_capture; 127 curr_pwr_watts *= data->tdp_to_watts; 128 129 /* 130 * Convert to microWatt 131 * 132 * power is in Watt provided as fixed point integer with 133 * scaling factor 1/(2^16). For conversion we use 134 * (10^6)/(2^16) = 15625/(2^10) 135 */ 136 curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range); 137 return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts); 138 } 139 static DEVICE_ATTR_RO(power1_input); 140 141 static ssize_t power1_crit_show(struct device *dev, 142 struct device_attribute *attr, char *buf) 143 { 144 struct fam15h_power_data *data = dev_get_drvdata(dev); 145 146 return sprintf(buf, "%u\n", data->processor_pwr_watts); 147 } 148 static DEVICE_ATTR_RO(power1_crit); 149 150 static void do_read_registers_on_cu(void *_data) 151 { 152 struct fam15h_power_data *data = _data; 153 int cpu, cu; 154 155 cpu = smp_processor_id(); 156 157 /* 158 * With the new x86 topology modelling, cpu core id actually 159 * is compute unit id. 160 */ 161 cu = cpu_data(cpu).cpu_core_id; 162 163 rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]); 164 rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]); 165 166 data->cu_on[cu] = 1; 167 } 168 169 /* 170 * This function is only able to be called when CPUID 171 * Fn8000_0007:EDX[12] is set. 172 */ 173 static int read_registers(struct fam15h_power_data *data) 174 { 175 int core, this_core; 176 cpumask_var_t mask; 177 int ret, cpu; 178 179 ret = zalloc_cpumask_var(&mask, GFP_KERNEL); 180 if (!ret) 181 return -ENOMEM; 182 183 memset(data->cu_on, 0, sizeof(int) * MAX_CUS); 184 185 get_online_cpus(); 186 187 /* 188 * Choose the first online core of each compute unit, and then 189 * read their MSR value of power and ptsc in a single IPI, 190 * because the MSR value of CPU core represent the compute 191 * unit's. 192 */ 193 core = -1; 194 195 for_each_online_cpu(cpu) { 196 this_core = topology_core_id(cpu); 197 198 if (this_core == core) 199 continue; 200 201 core = this_core; 202 203 /* get any CPU on this compute unit */ 204 cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask); 205 } 206 207 on_each_cpu_mask(mask, do_read_registers_on_cu, data, true); 208 209 put_online_cpus(); 210 free_cpumask_var(mask); 211 212 return 0; 213 } 214 215 static ssize_t power1_average_show(struct device *dev, 216 struct device_attribute *attr, char *buf) 217 { 218 struct fam15h_power_data *data = dev_get_drvdata(dev); 219 u64 prev_cu_acc_power[MAX_CUS], prev_ptsc[MAX_CUS], 220 jdelta[MAX_CUS]; 221 u64 tdelta, avg_acc; 222 int cu, cu_num, ret; 223 signed long leftover; 224 225 /* 226 * With the new x86 topology modelling, x86_max_cores is the 227 * compute unit number. 228 */ 229 cu_num = boot_cpu_data.x86_max_cores; 230 231 ret = read_registers(data); 232 if (ret) 233 return 0; 234 235 for (cu = 0; cu < cu_num; cu++) { 236 prev_cu_acc_power[cu] = data->cu_acc_power[cu]; 237 prev_ptsc[cu] = data->cpu_sw_pwr_ptsc[cu]; 238 } 239 240 leftover = schedule_timeout_interruptible(msecs_to_jiffies(data->power_period)); 241 if (leftover) 242 return 0; 243 244 ret = read_registers(data); 245 if (ret) 246 return 0; 247 248 for (cu = 0, avg_acc = 0; cu < cu_num; cu++) { 249 /* check if current compute unit is online */ 250 if (data->cu_on[cu] == 0) 251 continue; 252 253 if (data->cu_acc_power[cu] < prev_cu_acc_power[cu]) { 254 jdelta[cu] = data->max_cu_acc_power + data->cu_acc_power[cu]; 255 jdelta[cu] -= prev_cu_acc_power[cu]; 256 } else { 257 jdelta[cu] = data->cu_acc_power[cu] - prev_cu_acc_power[cu]; 258 } 259 tdelta = data->cpu_sw_pwr_ptsc[cu] - prev_ptsc[cu]; 260 jdelta[cu] *= data->cpu_pwr_sample_ratio * 1000; 261 do_div(jdelta[cu], tdelta); 262 263 /* the unit is microWatt */ 264 avg_acc += jdelta[cu]; 265 } 266 267 return sprintf(buf, "%llu\n", (unsigned long long)avg_acc); 268 } 269 static DEVICE_ATTR_RO(power1_average); 270 271 static ssize_t power1_average_interval_show(struct device *dev, 272 struct device_attribute *attr, 273 char *buf) 274 { 275 struct fam15h_power_data *data = dev_get_drvdata(dev); 276 277 return sprintf(buf, "%lu\n", data->power_period); 278 } 279 280 static ssize_t power1_average_interval_store(struct device *dev, 281 struct device_attribute *attr, 282 const char *buf, size_t count) 283 { 284 struct fam15h_power_data *data = dev_get_drvdata(dev); 285 unsigned long temp; 286 int ret; 287 288 ret = kstrtoul(buf, 10, &temp); 289 if (ret) 290 return ret; 291 292 if (temp > MAX_INTERVAL) 293 return -EINVAL; 294 295 /* the interval value should be greater than 0 */ 296 if (temp <= 0) 297 return -EINVAL; 298 299 data->power_period = temp; 300 301 return count; 302 } 303 static DEVICE_ATTR_RW(power1_average_interval); 304 305 static int fam15h_power_init_attrs(struct pci_dev *pdev, 306 struct fam15h_power_data *data) 307 { 308 int n = FAM15H_MIN_NUM_ATTRS; 309 struct attribute **fam15h_power_attrs; 310 struct cpuinfo_x86 *c = &boot_cpu_data; 311 312 if (c->x86 == 0x15 && 313 (c->x86_model <= 0xf || 314 (c->x86_model >= 0x60 && c->x86_model <= 0x7f))) 315 n += 1; 316 317 /* check if processor supports accumulated power */ 318 if (boot_cpu_has(X86_FEATURE_ACC_POWER)) 319 n += 2; 320 321 fam15h_power_attrs = devm_kcalloc(&pdev->dev, n, 322 sizeof(*fam15h_power_attrs), 323 GFP_KERNEL); 324 325 if (!fam15h_power_attrs) 326 return -ENOMEM; 327 328 n = 0; 329 fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr; 330 if (c->x86 == 0x15 && 331 (c->x86_model <= 0xf || 332 (c->x86_model >= 0x60 && c->x86_model <= 0x7f))) 333 fam15h_power_attrs[n++] = &dev_attr_power1_input.attr; 334 335 if (boot_cpu_has(X86_FEATURE_ACC_POWER)) { 336 fam15h_power_attrs[n++] = &dev_attr_power1_average.attr; 337 fam15h_power_attrs[n++] = &dev_attr_power1_average_interval.attr; 338 } 339 340 data->group.attrs = fam15h_power_attrs; 341 342 return 0; 343 } 344 345 static bool should_load_on_this_node(struct pci_dev *f4) 346 { 347 u32 val; 348 349 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3), 350 REG_NORTHBRIDGE_CAP, &val); 351 if ((val & BIT(29)) && ((val >> 30) & 3)) 352 return false; 353 354 return true; 355 } 356 357 /* 358 * Newer BKDG versions have an updated recommendation on how to properly 359 * initialize the running average range (was: 0xE, now: 0x9). This avoids 360 * counter saturations resulting in bogus power readings. 361 * We correct this value ourselves to cope with older BIOSes. 362 */ 363 static const struct pci_device_id affected_device[] = { 364 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) }, 365 { 0 } 366 }; 367 368 static void tweak_runavg_range(struct pci_dev *pdev) 369 { 370 u32 val; 371 372 /* 373 * let this quirk apply only to the current version of the 374 * northbridge, since future versions may change the behavior 375 */ 376 if (!pci_match_id(affected_device, pdev)) 377 return; 378 379 pci_bus_read_config_dword(pdev->bus, 380 PCI_DEVFN(PCI_SLOT(pdev->devfn), 5), 381 REG_TDP_RUNNING_AVERAGE, &val); 382 if ((val & 0xf) != 0xe) 383 return; 384 385 val &= ~0xf; 386 val |= 0x9; 387 pci_bus_write_config_dword(pdev->bus, 388 PCI_DEVFN(PCI_SLOT(pdev->devfn), 5), 389 REG_TDP_RUNNING_AVERAGE, val); 390 } 391 392 #ifdef CONFIG_PM 393 static int fam15h_power_resume(struct pci_dev *pdev) 394 { 395 tweak_runavg_range(pdev); 396 return 0; 397 } 398 #else 399 #define fam15h_power_resume NULL 400 #endif 401 402 static int fam15h_power_init_data(struct pci_dev *f4, 403 struct fam15h_power_data *data) 404 { 405 u32 val; 406 u64 tmp; 407 int ret; 408 409 pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val); 410 data->base_tdp = val >> 16; 411 tmp = val & 0xffff; 412 413 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5), 414 REG_TDP_LIMIT3, &val); 415 416 data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f); 417 tmp *= data->tdp_to_watts; 418 419 /* result not allowed to be >= 256W */ 420 if ((tmp >> 16) >= 256) 421 dev_warn(&f4->dev, 422 "Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n", 423 (unsigned int) (tmp >> 16)); 424 425 /* convert to microWatt */ 426 data->processor_pwr_watts = (tmp * 15625) >> 10; 427 428 ret = fam15h_power_init_attrs(f4, data); 429 if (ret) 430 return ret; 431 432 433 /* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */ 434 if (!boot_cpu_has(X86_FEATURE_ACC_POWER)) 435 return 0; 436 437 /* 438 * determine the ratio of the compute unit power accumulator 439 * sample period to the PTSC counter period by executing CPUID 440 * Fn8000_0007:ECX 441 */ 442 data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007); 443 444 if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) { 445 pr_err("Failed to read max compute unit power accumulator MSR\n"); 446 return -ENODEV; 447 } 448 449 data->max_cu_acc_power = tmp; 450 451 /* 452 * Milliseconds are a reasonable interval for the measurement. 453 * But it shouldn't set too long here, because several seconds 454 * would cause the read function to hang. So set default 455 * interval as 10 ms. 456 */ 457 data->power_period = 10; 458 459 return read_registers(data); 460 } 461 462 static int fam15h_power_probe(struct pci_dev *pdev, 463 const struct pci_device_id *id) 464 { 465 struct fam15h_power_data *data; 466 struct device *dev = &pdev->dev; 467 struct device *hwmon_dev; 468 int ret; 469 470 /* 471 * though we ignore every other northbridge, we still have to 472 * do the tweaking on _each_ node in MCM processors as the counters 473 * are working hand-in-hand 474 */ 475 tweak_runavg_range(pdev); 476 477 if (!should_load_on_this_node(pdev)) 478 return -ENODEV; 479 480 data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL); 481 if (!data) 482 return -ENOMEM; 483 484 ret = fam15h_power_init_data(pdev, data); 485 if (ret) 486 return ret; 487 488 data->pdev = pdev; 489 490 data->groups[0] = &data->group; 491 492 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power", 493 data, 494 &data->groups[0]); 495 return PTR_ERR_OR_ZERO(hwmon_dev); 496 } 497 498 static const struct pci_device_id fam15h_power_id_table[] = { 499 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) }, 500 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) }, 501 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) }, 502 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) }, 503 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) }, 504 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) }, 505 {} 506 }; 507 MODULE_DEVICE_TABLE(pci, fam15h_power_id_table); 508 509 static struct pci_driver fam15h_power_driver = { 510 .name = "fam15h_power", 511 .id_table = fam15h_power_id_table, 512 .probe = fam15h_power_probe, 513 .resume = fam15h_power_resume, 514 }; 515 516 module_pci_driver(fam15h_power_driver); 517