1 /* 2 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x, SCH5027, 3 * and SCH5127 Super-I/O chips integrated hardware monitoring 4 * features. 5 * Copyright (c) 2007, 2008, 2009, 2010 Juerg Haefliger <juergh@gmail.com> 6 * 7 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access 8 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus 9 * if a SCH311x or SCH5127 chip is found. Both types of chips have very 10 * similar hardware monitoring capabilities but differ in the way they can be 11 * accessed. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30 #include <linux/module.h> 31 #include <linux/init.h> 32 #include <linux/slab.h> 33 #include <linux/jiffies.h> 34 #include <linux/i2c.h> 35 #include <linux/platform_device.h> 36 #include <linux/hwmon.h> 37 #include <linux/hwmon-sysfs.h> 38 #include <linux/hwmon-vid.h> 39 #include <linux/err.h> 40 #include <linux/mutex.h> 41 #include <linux/acpi.h> 42 #include <linux/io.h> 43 44 /* ISA device, if found */ 45 static struct platform_device *pdev; 46 47 /* Module load parameters */ 48 static bool force_start; 49 module_param(force_start, bool, 0); 50 MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs"); 51 52 static unsigned short force_id; 53 module_param(force_id, ushort, 0); 54 MODULE_PARM_DESC(force_id, "Override the detected device ID"); 55 56 static bool probe_all_addr; 57 module_param(probe_all_addr, bool, 0); 58 MODULE_PARM_DESC(probe_all_addr, 59 "Include probing of non-standard LPC addresses"); 60 61 /* Addresses to scan */ 62 static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END}; 63 64 enum chips { dme1737, sch5027, sch311x, sch5127 }; 65 66 #define DO_REPORT "Please report to the driver maintainer." 67 68 /* --------------------------------------------------------------------- 69 * Registers 70 * 71 * The sensors are defined as follows: 72 * 73 * Voltages Temperatures 74 * -------- ------------ 75 * in0 +5VTR (+5V stdby) temp1 Remote diode 1 76 * in1 Vccp (proc core) temp2 Internal temp 77 * in2 VCC (internal +3.3V) temp3 Remote diode 2 78 * in3 +5V 79 * in4 +12V 80 * in5 VTR (+3.3V stby) 81 * in6 Vbat 82 * in7 Vtrip (sch5127 only) 83 * 84 * --------------------------------------------------------------------- */ 85 86 /* Voltages (in) numbered 0-7 (ix) */ 87 #define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \ 88 (ix) < 7 ? 0x94 + (ix) : \ 89 0x1f) 90 #define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \ 91 : 0x91 + (ix) * 2) 92 #define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \ 93 : 0x92 + (ix) * 2) 94 95 /* Temperatures (temp) numbered 0-2 (ix) */ 96 #define DME1737_REG_TEMP(ix) (0x25 + (ix)) 97 #define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2) 98 #define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2) 99 #define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \ 100 : 0x1c + (ix)) 101 102 /* 103 * Voltage and temperature LSBs 104 * The LSBs (4 bits each) are stored in 5 registers with the following layouts: 105 * IN_TEMP_LSB(0) = [in5, in6] 106 * IN_TEMP_LSB(1) = [temp3, temp1] 107 * IN_TEMP_LSB(2) = [in4, temp2] 108 * IN_TEMP_LSB(3) = [in3, in0] 109 * IN_TEMP_LSB(4) = [in2, in1] 110 * IN_TEMP_LSB(5) = [res, in7] 111 */ 112 #define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix)) 113 static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0, 5}; 114 static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4, 4}; 115 static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1}; 116 static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0}; 117 118 /* Fans numbered 0-5 (ix) */ 119 #define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \ 120 : 0xa1 + (ix) * 2) 121 #define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \ 122 : 0xa5 + (ix) * 2) 123 #define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \ 124 : 0xb2 + (ix)) 125 #define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */ 126 127 /* PWMs numbered 0-2, 4-5 (ix) */ 128 #define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \ 129 : 0xa1 + (ix)) 130 #define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */ 131 #define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */ 132 #define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \ 133 : 0xa3 + (ix)) 134 /* 135 * The layout of the ramp rate registers is different from the other pwm 136 * registers. The bits for the 3 PWMs are stored in 2 registers: 137 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0] 138 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0] 139 */ 140 #define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */ 141 142 /* Thermal zones 0-2 */ 143 #define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix)) 144 #define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix)) 145 /* 146 * The layout of the hysteresis registers is different from the other zone 147 * registers. The bits for the 3 zones are stored in 2 registers: 148 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0] 149 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES] 150 */ 151 #define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix)) 152 153 /* 154 * Alarm registers and bit mapping 155 * The 3 8-bit alarm registers will be concatenated to a single 32-bit 156 * alarm value [0, ALARM3, ALARM2, ALARM1]. 157 */ 158 #define DME1737_REG_ALARM1 0x41 159 #define DME1737_REG_ALARM2 0x42 160 #define DME1737_REG_ALARM3 0x83 161 static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17, 18}; 162 static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6}; 163 static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23}; 164 165 /* Miscellaneous registers */ 166 #define DME1737_REG_DEVICE 0x3d 167 #define DME1737_REG_COMPANY 0x3e 168 #define DME1737_REG_VERSTEP 0x3f 169 #define DME1737_REG_CONFIG 0x40 170 #define DME1737_REG_CONFIG2 0x7f 171 #define DME1737_REG_VID 0x43 172 #define DME1737_REG_TACH_PWM 0x81 173 174 /* --------------------------------------------------------------------- 175 * Misc defines 176 * --------------------------------------------------------------------- */ 177 178 /* Chip identification */ 179 #define DME1737_COMPANY_SMSC 0x5c 180 #define DME1737_VERSTEP 0x88 181 #define DME1737_VERSTEP_MASK 0xf8 182 #define SCH311X_DEVICE 0x8c 183 #define SCH5027_VERSTEP 0x69 184 #define SCH5127_DEVICE 0x8e 185 186 /* Device ID values (global configuration register index 0x20) */ 187 #define DME1737_ID_1 0x77 188 #define DME1737_ID_2 0x78 189 #define SCH3112_ID 0x7c 190 #define SCH3114_ID 0x7d 191 #define SCH3116_ID 0x7f 192 #define SCH5027_ID 0x89 193 #define SCH5127_ID 0x86 194 195 /* Length of ISA address segment */ 196 #define DME1737_EXTENT 2 197 198 /* chip-dependent features */ 199 #define HAS_TEMP_OFFSET (1 << 0) /* bit 0 */ 200 #define HAS_VID (1 << 1) /* bit 1 */ 201 #define HAS_ZONE3 (1 << 2) /* bit 2 */ 202 #define HAS_ZONE_HYST (1 << 3) /* bit 3 */ 203 #define HAS_PWM_MIN (1 << 4) /* bit 4 */ 204 #define HAS_FAN(ix) (1 << ((ix) + 5)) /* bits 5-10 */ 205 #define HAS_PWM(ix) (1 << ((ix) + 11)) /* bits 11-16 */ 206 #define HAS_IN7 (1 << 17) /* bit 17 */ 207 208 /* --------------------------------------------------------------------- 209 * Data structures and manipulation thereof 210 * --------------------------------------------------------------------- */ 211 212 struct dme1737_data { 213 struct i2c_client *client; /* for I2C devices only */ 214 struct device *hwmon_dev; 215 const char *name; 216 unsigned int addr; /* for ISA devices only */ 217 218 struct mutex update_lock; 219 int valid; /* !=0 if following fields are valid */ 220 unsigned long last_update; /* in jiffies */ 221 unsigned long last_vbat; /* in jiffies */ 222 enum chips type; 223 const int *in_nominal; /* pointer to IN_NOMINAL array */ 224 225 u8 vid; 226 u8 pwm_rr_en; 227 u32 has_features; 228 229 /* Register values */ 230 u16 in[8]; 231 u8 in_min[8]; 232 u8 in_max[8]; 233 s16 temp[3]; 234 s8 temp_min[3]; 235 s8 temp_max[3]; 236 s8 temp_offset[3]; 237 u8 config; 238 u8 config2; 239 u8 vrm; 240 u16 fan[6]; 241 u16 fan_min[6]; 242 u8 fan_max[2]; 243 u8 fan_opt[6]; 244 u8 pwm[6]; 245 u8 pwm_min[3]; 246 u8 pwm_config[3]; 247 u8 pwm_acz[3]; 248 u8 pwm_freq[6]; 249 u8 pwm_rr[2]; 250 s8 zone_low[3]; 251 s8 zone_abs[3]; 252 u8 zone_hyst[2]; 253 u32 alarms; 254 }; 255 256 /* Nominal voltage values */ 257 static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300, 258 3300}; 259 static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300, 260 3300}; 261 static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300, 262 3300}; 263 static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300, 264 3300, 1500}; 265 #define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \ 266 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \ 267 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \ 268 IN_NOMINAL_DME1737) 269 270 /* 271 * Voltage input 272 * Voltage inputs have 16 bits resolution, limit values have 8 bits 273 * resolution. 274 */ 275 static inline int IN_FROM_REG(int reg, int nominal, int res) 276 { 277 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2)); 278 } 279 280 static inline int IN_TO_REG(long val, int nominal) 281 { 282 val = clamp_val(val, 0, 255 * nominal / 192); 283 return DIV_ROUND_CLOSEST(val * 192, nominal); 284 } 285 286 /* 287 * Temperature input 288 * The register values represent temperatures in 2's complement notation from 289 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit 290 * values have 8 bits resolution. 291 */ 292 static inline int TEMP_FROM_REG(int reg, int res) 293 { 294 return (reg * 1000) >> (res - 8); 295 } 296 297 static inline int TEMP_TO_REG(long val) 298 { 299 val = clamp_val(val, -128000, 127000); 300 return DIV_ROUND_CLOSEST(val, 1000); 301 } 302 303 /* Temperature range */ 304 static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000, 305 10000, 13333, 16000, 20000, 26666, 32000, 306 40000, 53333, 80000}; 307 308 static inline int TEMP_RANGE_FROM_REG(int reg) 309 { 310 return TEMP_RANGE[(reg >> 4) & 0x0f]; 311 } 312 313 static int TEMP_RANGE_TO_REG(long val, int reg) 314 { 315 int i; 316 317 for (i = 15; i > 0; i--) { 318 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2) 319 break; 320 } 321 322 return (reg & 0x0f) | (i << 4); 323 } 324 325 /* 326 * Temperature hysteresis 327 * Register layout: 328 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0] 329 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx] 330 */ 331 static inline int TEMP_HYST_FROM_REG(int reg, int ix) 332 { 333 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000; 334 } 335 336 static inline int TEMP_HYST_TO_REG(int temp, long hyst, int ix, int reg) 337 { 338 hyst = clamp_val(hyst, temp - 15000, temp); 339 hyst = DIV_ROUND_CLOSEST(temp - hyst, 1000); 340 341 return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4); 342 } 343 344 /* Fan input RPM */ 345 static inline int FAN_FROM_REG(int reg, int tpc) 346 { 347 if (tpc) 348 return tpc * reg; 349 else 350 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg; 351 } 352 353 static inline int FAN_TO_REG(long val, int tpc) 354 { 355 if (tpc) { 356 return clamp_val(val / tpc, 0, 0xffff); 357 } else { 358 return (val <= 0) ? 0xffff : 359 clamp_val(90000 * 60 / val, 0, 0xfffe); 360 } 361 } 362 363 /* 364 * Fan TPC (tach pulse count) 365 * Converts a register value to a TPC multiplier or returns 0 if the tachometer 366 * is configured in legacy (non-tpc) mode 367 */ 368 static inline int FAN_TPC_FROM_REG(int reg) 369 { 370 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03); 371 } 372 373 /* 374 * Fan type 375 * The type of a fan is expressed in number of pulses-per-revolution that it 376 * emits 377 */ 378 static inline int FAN_TYPE_FROM_REG(int reg) 379 { 380 int edge = (reg >> 1) & 0x03; 381 382 return (edge > 0) ? 1 << (edge - 1) : 0; 383 } 384 385 static inline int FAN_TYPE_TO_REG(long val, int reg) 386 { 387 int edge = (val == 4) ? 3 : val; 388 389 return (reg & 0xf9) | (edge << 1); 390 } 391 392 /* Fan max RPM */ 393 static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12, 394 0x11, 0x0f, 0x0e}; 395 396 static int FAN_MAX_FROM_REG(int reg) 397 { 398 int i; 399 400 for (i = 10; i > 0; i--) { 401 if (reg == FAN_MAX[i]) 402 break; 403 } 404 405 return 1000 + i * 500; 406 } 407 408 static int FAN_MAX_TO_REG(long val) 409 { 410 int i; 411 412 for (i = 10; i > 0; i--) { 413 if (val > (1000 + (i - 1) * 500)) 414 break; 415 } 416 417 return FAN_MAX[i]; 418 } 419 420 /* 421 * PWM enable 422 * Register to enable mapping: 423 * 000: 2 fan on zone 1 auto 424 * 001: 2 fan on zone 2 auto 425 * 010: 2 fan on zone 3 auto 426 * 011: 0 fan full on 427 * 100: -1 fan disabled 428 * 101: 2 fan on hottest of zones 2,3 auto 429 * 110: 2 fan on hottest of zones 1,2,3 auto 430 * 111: 1 fan in manual mode 431 */ 432 static inline int PWM_EN_FROM_REG(int reg) 433 { 434 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1}; 435 436 return en[(reg >> 5) & 0x07]; 437 } 438 439 static inline int PWM_EN_TO_REG(int val, int reg) 440 { 441 int en = (val == 1) ? 7 : 3; 442 443 return (reg & 0x1f) | ((en & 0x07) << 5); 444 } 445 446 /* 447 * PWM auto channels zone 448 * Register to auto channels zone mapping (ACZ is a bitfield with bit x 449 * corresponding to zone x+1): 450 * 000: 001 fan on zone 1 auto 451 * 001: 010 fan on zone 2 auto 452 * 010: 100 fan on zone 3 auto 453 * 011: 000 fan full on 454 * 100: 000 fan disabled 455 * 101: 110 fan on hottest of zones 2,3 auto 456 * 110: 111 fan on hottest of zones 1,2,3 auto 457 * 111: 000 fan in manual mode 458 */ 459 static inline int PWM_ACZ_FROM_REG(int reg) 460 { 461 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0}; 462 463 return acz[(reg >> 5) & 0x07]; 464 } 465 466 static inline int PWM_ACZ_TO_REG(long val, int reg) 467 { 468 int acz = (val == 4) ? 2 : val - 1; 469 470 return (reg & 0x1f) | ((acz & 0x07) << 5); 471 } 472 473 /* PWM frequency */ 474 static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88, 475 15000, 20000, 30000, 25000, 0, 0, 0, 0}; 476 477 static inline int PWM_FREQ_FROM_REG(int reg) 478 { 479 return PWM_FREQ[reg & 0x0f]; 480 } 481 482 static int PWM_FREQ_TO_REG(long val, int reg) 483 { 484 int i; 485 486 /* the first two cases are special - stupid chip design! */ 487 if (val > 27500) { 488 i = 10; 489 } else if (val > 22500) { 490 i = 11; 491 } else { 492 for (i = 9; i > 0; i--) { 493 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2) 494 break; 495 } 496 } 497 498 return (reg & 0xf0) | i; 499 } 500 501 /* 502 * PWM ramp rate 503 * Register layout: 504 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0] 505 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0] 506 */ 507 static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5}; 508 509 static inline int PWM_RR_FROM_REG(int reg, int ix) 510 { 511 int rr = (ix == 1) ? reg >> 4 : reg; 512 513 return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0; 514 } 515 516 static int PWM_RR_TO_REG(long val, int ix, int reg) 517 { 518 int i; 519 520 for (i = 0; i < 7; i++) { 521 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2) 522 break; 523 } 524 525 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i; 526 } 527 528 /* PWM ramp rate enable */ 529 static inline int PWM_RR_EN_FROM_REG(int reg, int ix) 530 { 531 return PWM_RR_FROM_REG(reg, ix) ? 1 : 0; 532 } 533 534 static inline int PWM_RR_EN_TO_REG(long val, int ix, int reg) 535 { 536 int en = (ix == 1) ? 0x80 : 0x08; 537 538 return val ? reg | en : reg & ~en; 539 } 540 541 /* 542 * PWM min/off 543 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for 544 * the register layout). 545 */ 546 static inline int PWM_OFF_FROM_REG(int reg, int ix) 547 { 548 return (reg >> (ix + 5)) & 0x01; 549 } 550 551 static inline int PWM_OFF_TO_REG(int val, int ix, int reg) 552 { 553 return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5)); 554 } 555 556 /* --------------------------------------------------------------------- 557 * Device I/O access 558 * 559 * ISA access is performed through an index/data register pair and needs to 560 * be protected by a mutex during runtime (not required for initialization). 561 * We use data->update_lock for this and need to ensure that we acquire it 562 * before calling dme1737_read or dme1737_write. 563 * --------------------------------------------------------------------- */ 564 565 static u8 dme1737_read(const struct dme1737_data *data, u8 reg) 566 { 567 struct i2c_client *client = data->client; 568 s32 val; 569 570 if (client) { /* I2C device */ 571 val = i2c_smbus_read_byte_data(client, reg); 572 573 if (val < 0) { 574 dev_warn(&client->dev, 575 "Read from register 0x%02x failed! %s\n", 576 reg, DO_REPORT); 577 } 578 } else { /* ISA device */ 579 outb(reg, data->addr); 580 val = inb(data->addr + 1); 581 } 582 583 return val; 584 } 585 586 static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val) 587 { 588 struct i2c_client *client = data->client; 589 s32 res = 0; 590 591 if (client) { /* I2C device */ 592 res = i2c_smbus_write_byte_data(client, reg, val); 593 594 if (res < 0) { 595 dev_warn(&client->dev, 596 "Write to register 0x%02x failed! %s\n", 597 reg, DO_REPORT); 598 } 599 } else { /* ISA device */ 600 outb(reg, data->addr); 601 outb(val, data->addr + 1); 602 } 603 604 return res; 605 } 606 607 static struct dme1737_data *dme1737_update_device(struct device *dev) 608 { 609 struct dme1737_data *data = dev_get_drvdata(dev); 610 int ix; 611 u8 lsb[6]; 612 613 mutex_lock(&data->update_lock); 614 615 /* Enable a Vbat monitoring cycle every 10 mins */ 616 if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) { 617 dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data, 618 DME1737_REG_CONFIG) | 0x10); 619 data->last_vbat = jiffies; 620 } 621 622 /* Sample register contents every 1 sec */ 623 if (time_after(jiffies, data->last_update + HZ) || !data->valid) { 624 if (data->has_features & HAS_VID) { 625 data->vid = dme1737_read(data, DME1737_REG_VID) & 626 0x3f; 627 } 628 629 /* In (voltage) registers */ 630 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { 631 /* 632 * Voltage inputs are stored as 16 bit values even 633 * though they have only 12 bits resolution. This is 634 * to make it consistent with the temp inputs. 635 */ 636 if (ix == 7 && !(data->has_features & HAS_IN7)) 637 continue; 638 data->in[ix] = dme1737_read(data, 639 DME1737_REG_IN(ix)) << 8; 640 data->in_min[ix] = dme1737_read(data, 641 DME1737_REG_IN_MIN(ix)); 642 data->in_max[ix] = dme1737_read(data, 643 DME1737_REG_IN_MAX(ix)); 644 } 645 646 /* Temp registers */ 647 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { 648 /* 649 * Temp inputs are stored as 16 bit values even 650 * though they have only 12 bits resolution. This is 651 * to take advantage of implicit conversions between 652 * register values (2's complement) and temp values 653 * (signed decimal). 654 */ 655 data->temp[ix] = dme1737_read(data, 656 DME1737_REG_TEMP(ix)) << 8; 657 data->temp_min[ix] = dme1737_read(data, 658 DME1737_REG_TEMP_MIN(ix)); 659 data->temp_max[ix] = dme1737_read(data, 660 DME1737_REG_TEMP_MAX(ix)); 661 if (data->has_features & HAS_TEMP_OFFSET) { 662 data->temp_offset[ix] = dme1737_read(data, 663 DME1737_REG_TEMP_OFFSET(ix)); 664 } 665 } 666 667 /* 668 * In and temp LSB registers 669 * The LSBs are latched when the MSBs are read, so the order in 670 * which the registers are read (MSB first, then LSB) is 671 * important! 672 */ 673 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) { 674 if (ix == 5 && !(data->has_features & HAS_IN7)) 675 continue; 676 lsb[ix] = dme1737_read(data, 677 DME1737_REG_IN_TEMP_LSB(ix)); 678 } 679 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { 680 if (ix == 7 && !(data->has_features & HAS_IN7)) 681 continue; 682 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] << 683 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0; 684 } 685 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { 686 data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] << 687 DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0; 688 } 689 690 /* Fan registers */ 691 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) { 692 /* 693 * Skip reading registers if optional fans are not 694 * present 695 */ 696 if (!(data->has_features & HAS_FAN(ix))) 697 continue; 698 data->fan[ix] = dme1737_read(data, 699 DME1737_REG_FAN(ix)); 700 data->fan[ix] |= dme1737_read(data, 701 DME1737_REG_FAN(ix) + 1) << 8; 702 data->fan_min[ix] = dme1737_read(data, 703 DME1737_REG_FAN_MIN(ix)); 704 data->fan_min[ix] |= dme1737_read(data, 705 DME1737_REG_FAN_MIN(ix) + 1) << 8; 706 data->fan_opt[ix] = dme1737_read(data, 707 DME1737_REG_FAN_OPT(ix)); 708 /* fan_max exists only for fan[5-6] */ 709 if (ix > 3) { 710 data->fan_max[ix - 4] = dme1737_read(data, 711 DME1737_REG_FAN_MAX(ix)); 712 } 713 } 714 715 /* PWM registers */ 716 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) { 717 /* 718 * Skip reading registers if optional PWMs are not 719 * present 720 */ 721 if (!(data->has_features & HAS_PWM(ix))) 722 continue; 723 data->pwm[ix] = dme1737_read(data, 724 DME1737_REG_PWM(ix)); 725 data->pwm_freq[ix] = dme1737_read(data, 726 DME1737_REG_PWM_FREQ(ix)); 727 /* pwm_config and pwm_min exist only for pwm[1-3] */ 728 if (ix < 3) { 729 data->pwm_config[ix] = dme1737_read(data, 730 DME1737_REG_PWM_CONFIG(ix)); 731 data->pwm_min[ix] = dme1737_read(data, 732 DME1737_REG_PWM_MIN(ix)); 733 } 734 } 735 for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) { 736 data->pwm_rr[ix] = dme1737_read(data, 737 DME1737_REG_PWM_RR(ix)); 738 } 739 740 /* Thermal zone registers */ 741 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) { 742 /* Skip reading registers if zone3 is not present */ 743 if ((ix == 2) && !(data->has_features & HAS_ZONE3)) 744 continue; 745 /* sch5127 zone2 registers are special */ 746 if ((ix == 1) && (data->type == sch5127)) { 747 data->zone_low[1] = dme1737_read(data, 748 DME1737_REG_ZONE_LOW(2)); 749 data->zone_abs[1] = dme1737_read(data, 750 DME1737_REG_ZONE_ABS(2)); 751 } else { 752 data->zone_low[ix] = dme1737_read(data, 753 DME1737_REG_ZONE_LOW(ix)); 754 data->zone_abs[ix] = dme1737_read(data, 755 DME1737_REG_ZONE_ABS(ix)); 756 } 757 } 758 if (data->has_features & HAS_ZONE_HYST) { 759 for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) { 760 data->zone_hyst[ix] = dme1737_read(data, 761 DME1737_REG_ZONE_HYST(ix)); 762 } 763 } 764 765 /* Alarm registers */ 766 data->alarms = dme1737_read(data, 767 DME1737_REG_ALARM1); 768 /* 769 * Bit 7 tells us if the other alarm registers are non-zero and 770 * therefore also need to be read 771 */ 772 if (data->alarms & 0x80) { 773 data->alarms |= dme1737_read(data, 774 DME1737_REG_ALARM2) << 8; 775 data->alarms |= dme1737_read(data, 776 DME1737_REG_ALARM3) << 16; 777 } 778 779 /* 780 * The ISA chips require explicit clearing of alarm bits. 781 * Don't worry, an alarm will come back if the condition 782 * that causes it still exists 783 */ 784 if (!data->client) { 785 if (data->alarms & 0xff0000) 786 dme1737_write(data, DME1737_REG_ALARM3, 0xff); 787 if (data->alarms & 0xff00) 788 dme1737_write(data, DME1737_REG_ALARM2, 0xff); 789 if (data->alarms & 0xff) 790 dme1737_write(data, DME1737_REG_ALARM1, 0xff); 791 } 792 793 data->last_update = jiffies; 794 data->valid = 1; 795 } 796 797 mutex_unlock(&data->update_lock); 798 799 return data; 800 } 801 802 /* --------------------------------------------------------------------- 803 * Voltage sysfs attributes 804 * ix = [0-7] 805 * --------------------------------------------------------------------- */ 806 807 #define SYS_IN_INPUT 0 808 #define SYS_IN_MIN 1 809 #define SYS_IN_MAX 2 810 #define SYS_IN_ALARM 3 811 812 static ssize_t show_in(struct device *dev, struct device_attribute *attr, 813 char *buf) 814 { 815 struct dme1737_data *data = dme1737_update_device(dev); 816 struct sensor_device_attribute_2 817 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 818 int ix = sensor_attr_2->index; 819 int fn = sensor_attr_2->nr; 820 int res; 821 822 switch (fn) { 823 case SYS_IN_INPUT: 824 res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16); 825 break; 826 case SYS_IN_MIN: 827 res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8); 828 break; 829 case SYS_IN_MAX: 830 res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8); 831 break; 832 case SYS_IN_ALARM: 833 res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01; 834 break; 835 default: 836 res = 0; 837 dev_dbg(dev, "Unknown function %d.\n", fn); 838 } 839 840 return sprintf(buf, "%d\n", res); 841 } 842 843 static ssize_t set_in(struct device *dev, struct device_attribute *attr, 844 const char *buf, size_t count) 845 { 846 struct dme1737_data *data = dev_get_drvdata(dev); 847 struct sensor_device_attribute_2 848 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 849 int ix = sensor_attr_2->index; 850 int fn = sensor_attr_2->nr; 851 long val; 852 int err; 853 854 err = kstrtol(buf, 10, &val); 855 if (err) 856 return err; 857 858 mutex_lock(&data->update_lock); 859 switch (fn) { 860 case SYS_IN_MIN: 861 data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]); 862 dme1737_write(data, DME1737_REG_IN_MIN(ix), 863 data->in_min[ix]); 864 break; 865 case SYS_IN_MAX: 866 data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]); 867 dme1737_write(data, DME1737_REG_IN_MAX(ix), 868 data->in_max[ix]); 869 break; 870 default: 871 dev_dbg(dev, "Unknown function %d.\n", fn); 872 } 873 mutex_unlock(&data->update_lock); 874 875 return count; 876 } 877 878 /* --------------------------------------------------------------------- 879 * Temperature sysfs attributes 880 * ix = [0-2] 881 * --------------------------------------------------------------------- */ 882 883 #define SYS_TEMP_INPUT 0 884 #define SYS_TEMP_MIN 1 885 #define SYS_TEMP_MAX 2 886 #define SYS_TEMP_OFFSET 3 887 #define SYS_TEMP_ALARM 4 888 #define SYS_TEMP_FAULT 5 889 890 static ssize_t show_temp(struct device *dev, struct device_attribute *attr, 891 char *buf) 892 { 893 struct dme1737_data *data = dme1737_update_device(dev); 894 struct sensor_device_attribute_2 895 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 896 int ix = sensor_attr_2->index; 897 int fn = sensor_attr_2->nr; 898 int res; 899 900 switch (fn) { 901 case SYS_TEMP_INPUT: 902 res = TEMP_FROM_REG(data->temp[ix], 16); 903 break; 904 case SYS_TEMP_MIN: 905 res = TEMP_FROM_REG(data->temp_min[ix], 8); 906 break; 907 case SYS_TEMP_MAX: 908 res = TEMP_FROM_REG(data->temp_max[ix], 8); 909 break; 910 case SYS_TEMP_OFFSET: 911 res = TEMP_FROM_REG(data->temp_offset[ix], 8); 912 break; 913 case SYS_TEMP_ALARM: 914 res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01; 915 break; 916 case SYS_TEMP_FAULT: 917 res = (((u16)data->temp[ix] & 0xff00) == 0x8000); 918 break; 919 default: 920 res = 0; 921 dev_dbg(dev, "Unknown function %d.\n", fn); 922 } 923 924 return sprintf(buf, "%d\n", res); 925 } 926 927 static ssize_t set_temp(struct device *dev, struct device_attribute *attr, 928 const char *buf, size_t count) 929 { 930 struct dme1737_data *data = dev_get_drvdata(dev); 931 struct sensor_device_attribute_2 932 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 933 int ix = sensor_attr_2->index; 934 int fn = sensor_attr_2->nr; 935 long val; 936 int err; 937 938 err = kstrtol(buf, 10, &val); 939 if (err) 940 return err; 941 942 mutex_lock(&data->update_lock); 943 switch (fn) { 944 case SYS_TEMP_MIN: 945 data->temp_min[ix] = TEMP_TO_REG(val); 946 dme1737_write(data, DME1737_REG_TEMP_MIN(ix), 947 data->temp_min[ix]); 948 break; 949 case SYS_TEMP_MAX: 950 data->temp_max[ix] = TEMP_TO_REG(val); 951 dme1737_write(data, DME1737_REG_TEMP_MAX(ix), 952 data->temp_max[ix]); 953 break; 954 case SYS_TEMP_OFFSET: 955 data->temp_offset[ix] = TEMP_TO_REG(val); 956 dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix), 957 data->temp_offset[ix]); 958 break; 959 default: 960 dev_dbg(dev, "Unknown function %d.\n", fn); 961 } 962 mutex_unlock(&data->update_lock); 963 964 return count; 965 } 966 967 /* --------------------------------------------------------------------- 968 * Zone sysfs attributes 969 * ix = [0-2] 970 * --------------------------------------------------------------------- */ 971 972 #define SYS_ZONE_AUTO_CHANNELS_TEMP 0 973 #define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1 974 #define SYS_ZONE_AUTO_POINT1_TEMP 2 975 #define SYS_ZONE_AUTO_POINT2_TEMP 3 976 #define SYS_ZONE_AUTO_POINT3_TEMP 4 977 978 static ssize_t show_zone(struct device *dev, struct device_attribute *attr, 979 char *buf) 980 { 981 struct dme1737_data *data = dme1737_update_device(dev); 982 struct sensor_device_attribute_2 983 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 984 int ix = sensor_attr_2->index; 985 int fn = sensor_attr_2->nr; 986 int res; 987 988 switch (fn) { 989 case SYS_ZONE_AUTO_CHANNELS_TEMP: 990 /* check config2 for non-standard temp-to-zone mapping */ 991 if ((ix == 1) && (data->config2 & 0x02)) 992 res = 4; 993 else 994 res = 1 << ix; 995 break; 996 case SYS_ZONE_AUTO_POINT1_TEMP_HYST: 997 res = TEMP_FROM_REG(data->zone_low[ix], 8) - 998 TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix); 999 break; 1000 case SYS_ZONE_AUTO_POINT1_TEMP: 1001 res = TEMP_FROM_REG(data->zone_low[ix], 8); 1002 break; 1003 case SYS_ZONE_AUTO_POINT2_TEMP: 1004 /* pwm_freq holds the temp range bits in the upper nibble */ 1005 res = TEMP_FROM_REG(data->zone_low[ix], 8) + 1006 TEMP_RANGE_FROM_REG(data->pwm_freq[ix]); 1007 break; 1008 case SYS_ZONE_AUTO_POINT3_TEMP: 1009 res = TEMP_FROM_REG(data->zone_abs[ix], 8); 1010 break; 1011 default: 1012 res = 0; 1013 dev_dbg(dev, "Unknown function %d.\n", fn); 1014 } 1015 1016 return sprintf(buf, "%d\n", res); 1017 } 1018 1019 static ssize_t set_zone(struct device *dev, struct device_attribute *attr, 1020 const char *buf, size_t count) 1021 { 1022 struct dme1737_data *data = dev_get_drvdata(dev); 1023 struct sensor_device_attribute_2 1024 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1025 int ix = sensor_attr_2->index; 1026 int fn = sensor_attr_2->nr; 1027 long val; 1028 int temp; 1029 int err; 1030 u8 reg; 1031 1032 err = kstrtol(buf, 10, &val); 1033 if (err) 1034 return err; 1035 1036 mutex_lock(&data->update_lock); 1037 switch (fn) { 1038 case SYS_ZONE_AUTO_POINT1_TEMP_HYST: 1039 /* Refresh the cache */ 1040 data->zone_low[ix] = dme1737_read(data, 1041 DME1737_REG_ZONE_LOW(ix)); 1042 /* Modify the temp hyst value */ 1043 temp = TEMP_FROM_REG(data->zone_low[ix], 8); 1044 reg = dme1737_read(data, DME1737_REG_ZONE_HYST(ix == 2)); 1045 data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG(temp, val, ix, reg); 1046 dme1737_write(data, DME1737_REG_ZONE_HYST(ix == 2), 1047 data->zone_hyst[ix == 2]); 1048 break; 1049 case SYS_ZONE_AUTO_POINT1_TEMP: 1050 data->zone_low[ix] = TEMP_TO_REG(val); 1051 dme1737_write(data, DME1737_REG_ZONE_LOW(ix), 1052 data->zone_low[ix]); 1053 break; 1054 case SYS_ZONE_AUTO_POINT2_TEMP: 1055 /* Refresh the cache */ 1056 data->zone_low[ix] = dme1737_read(data, 1057 DME1737_REG_ZONE_LOW(ix)); 1058 /* 1059 * Modify the temp range value (which is stored in the upper 1060 * nibble of the pwm_freq register) 1061 */ 1062 temp = TEMP_FROM_REG(data->zone_low[ix], 8); 1063 val = clamp_val(val, temp, temp + 80000); 1064 reg = dme1737_read(data, DME1737_REG_PWM_FREQ(ix)); 1065 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val - temp, reg); 1066 dme1737_write(data, DME1737_REG_PWM_FREQ(ix), 1067 data->pwm_freq[ix]); 1068 break; 1069 case SYS_ZONE_AUTO_POINT3_TEMP: 1070 data->zone_abs[ix] = TEMP_TO_REG(val); 1071 dme1737_write(data, DME1737_REG_ZONE_ABS(ix), 1072 data->zone_abs[ix]); 1073 break; 1074 default: 1075 dev_dbg(dev, "Unknown function %d.\n", fn); 1076 } 1077 mutex_unlock(&data->update_lock); 1078 1079 return count; 1080 } 1081 1082 /* --------------------------------------------------------------------- 1083 * Fan sysfs attributes 1084 * ix = [0-5] 1085 * --------------------------------------------------------------------- */ 1086 1087 #define SYS_FAN_INPUT 0 1088 #define SYS_FAN_MIN 1 1089 #define SYS_FAN_MAX 2 1090 #define SYS_FAN_ALARM 3 1091 #define SYS_FAN_TYPE 4 1092 1093 static ssize_t show_fan(struct device *dev, struct device_attribute *attr, 1094 char *buf) 1095 { 1096 struct dme1737_data *data = dme1737_update_device(dev); 1097 struct sensor_device_attribute_2 1098 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1099 int ix = sensor_attr_2->index; 1100 int fn = sensor_attr_2->nr; 1101 int res; 1102 1103 switch (fn) { 1104 case SYS_FAN_INPUT: 1105 res = FAN_FROM_REG(data->fan[ix], 1106 ix < 4 ? 0 : 1107 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1108 break; 1109 case SYS_FAN_MIN: 1110 res = FAN_FROM_REG(data->fan_min[ix], 1111 ix < 4 ? 0 : 1112 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1113 break; 1114 case SYS_FAN_MAX: 1115 /* only valid for fan[5-6] */ 1116 res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]); 1117 break; 1118 case SYS_FAN_ALARM: 1119 res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01; 1120 break; 1121 case SYS_FAN_TYPE: 1122 /* only valid for fan[1-4] */ 1123 res = FAN_TYPE_FROM_REG(data->fan_opt[ix]); 1124 break; 1125 default: 1126 res = 0; 1127 dev_dbg(dev, "Unknown function %d.\n", fn); 1128 } 1129 1130 return sprintf(buf, "%d\n", res); 1131 } 1132 1133 static ssize_t set_fan(struct device *dev, struct device_attribute *attr, 1134 const char *buf, size_t count) 1135 { 1136 struct dme1737_data *data = dev_get_drvdata(dev); 1137 struct sensor_device_attribute_2 1138 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1139 int ix = sensor_attr_2->index; 1140 int fn = sensor_attr_2->nr; 1141 long val; 1142 int err; 1143 1144 err = kstrtol(buf, 10, &val); 1145 if (err) 1146 return err; 1147 1148 mutex_lock(&data->update_lock); 1149 switch (fn) { 1150 case SYS_FAN_MIN: 1151 if (ix < 4) { 1152 data->fan_min[ix] = FAN_TO_REG(val, 0); 1153 } else { 1154 /* Refresh the cache */ 1155 data->fan_opt[ix] = dme1737_read(data, 1156 DME1737_REG_FAN_OPT(ix)); 1157 /* Modify the fan min value */ 1158 data->fan_min[ix] = FAN_TO_REG(val, 1159 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1160 } 1161 dme1737_write(data, DME1737_REG_FAN_MIN(ix), 1162 data->fan_min[ix] & 0xff); 1163 dme1737_write(data, DME1737_REG_FAN_MIN(ix) + 1, 1164 data->fan_min[ix] >> 8); 1165 break; 1166 case SYS_FAN_MAX: 1167 /* Only valid for fan[5-6] */ 1168 data->fan_max[ix - 4] = FAN_MAX_TO_REG(val); 1169 dme1737_write(data, DME1737_REG_FAN_MAX(ix), 1170 data->fan_max[ix - 4]); 1171 break; 1172 case SYS_FAN_TYPE: 1173 /* Only valid for fan[1-4] */ 1174 if (!(val == 1 || val == 2 || val == 4)) { 1175 count = -EINVAL; 1176 dev_warn(dev, 1177 "Fan type value %ld not supported. Choose one of 1, 2, or 4.\n", 1178 val); 1179 goto exit; 1180 } 1181 data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(data, 1182 DME1737_REG_FAN_OPT(ix))); 1183 dme1737_write(data, DME1737_REG_FAN_OPT(ix), 1184 data->fan_opt[ix]); 1185 break; 1186 default: 1187 dev_dbg(dev, "Unknown function %d.\n", fn); 1188 } 1189 exit: 1190 mutex_unlock(&data->update_lock); 1191 1192 return count; 1193 } 1194 1195 /* --------------------------------------------------------------------- 1196 * PWM sysfs attributes 1197 * ix = [0-4] 1198 * --------------------------------------------------------------------- */ 1199 1200 #define SYS_PWM 0 1201 #define SYS_PWM_FREQ 1 1202 #define SYS_PWM_ENABLE 2 1203 #define SYS_PWM_RAMP_RATE 3 1204 #define SYS_PWM_AUTO_CHANNELS_ZONE 4 1205 #define SYS_PWM_AUTO_PWM_MIN 5 1206 #define SYS_PWM_AUTO_POINT1_PWM 6 1207 #define SYS_PWM_AUTO_POINT2_PWM 7 1208 1209 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, 1210 char *buf) 1211 { 1212 struct dme1737_data *data = dme1737_update_device(dev); 1213 struct sensor_device_attribute_2 1214 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1215 int ix = sensor_attr_2->index; 1216 int fn = sensor_attr_2->nr; 1217 int res; 1218 1219 switch (fn) { 1220 case SYS_PWM: 1221 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0) 1222 res = 255; 1223 else 1224 res = data->pwm[ix]; 1225 break; 1226 case SYS_PWM_FREQ: 1227 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]); 1228 break; 1229 case SYS_PWM_ENABLE: 1230 if (ix >= 3) 1231 res = 1; /* pwm[5-6] hard-wired to manual mode */ 1232 else 1233 res = PWM_EN_FROM_REG(data->pwm_config[ix]); 1234 break; 1235 case SYS_PWM_RAMP_RATE: 1236 /* Only valid for pwm[1-3] */ 1237 res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix); 1238 break; 1239 case SYS_PWM_AUTO_CHANNELS_ZONE: 1240 /* Only valid for pwm[1-3] */ 1241 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) 1242 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]); 1243 else 1244 res = data->pwm_acz[ix]; 1245 break; 1246 case SYS_PWM_AUTO_PWM_MIN: 1247 /* Only valid for pwm[1-3] */ 1248 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix)) 1249 res = data->pwm_min[ix]; 1250 else 1251 res = 0; 1252 break; 1253 case SYS_PWM_AUTO_POINT1_PWM: 1254 /* Only valid for pwm[1-3] */ 1255 res = data->pwm_min[ix]; 1256 break; 1257 case SYS_PWM_AUTO_POINT2_PWM: 1258 /* Only valid for pwm[1-3] */ 1259 res = 255; /* hard-wired */ 1260 break; 1261 default: 1262 res = 0; 1263 dev_dbg(dev, "Unknown function %d.\n", fn); 1264 } 1265 1266 return sprintf(buf, "%d\n", res); 1267 } 1268 1269 static struct attribute *dme1737_pwm_chmod_attr[]; 1270 static void dme1737_chmod_file(struct device*, struct attribute*, umode_t); 1271 1272 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, 1273 const char *buf, size_t count) 1274 { 1275 struct dme1737_data *data = dev_get_drvdata(dev); 1276 struct sensor_device_attribute_2 1277 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1278 int ix = sensor_attr_2->index; 1279 int fn = sensor_attr_2->nr; 1280 long val; 1281 int err; 1282 1283 err = kstrtol(buf, 10, &val); 1284 if (err) 1285 return err; 1286 1287 mutex_lock(&data->update_lock); 1288 switch (fn) { 1289 case SYS_PWM: 1290 data->pwm[ix] = clamp_val(val, 0, 255); 1291 dme1737_write(data, DME1737_REG_PWM(ix), data->pwm[ix]); 1292 break; 1293 case SYS_PWM_FREQ: 1294 data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(data, 1295 DME1737_REG_PWM_FREQ(ix))); 1296 dme1737_write(data, DME1737_REG_PWM_FREQ(ix), 1297 data->pwm_freq[ix]); 1298 break; 1299 case SYS_PWM_ENABLE: 1300 /* Only valid for pwm[1-3] */ 1301 if (val < 0 || val > 2) { 1302 count = -EINVAL; 1303 dev_warn(dev, 1304 "PWM enable %ld not supported. Choose one of 0, 1, or 2.\n", 1305 val); 1306 goto exit; 1307 } 1308 /* Refresh the cache */ 1309 data->pwm_config[ix] = dme1737_read(data, 1310 DME1737_REG_PWM_CONFIG(ix)); 1311 if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) { 1312 /* Bail out if no change */ 1313 goto exit; 1314 } 1315 /* Do some housekeeping if we are currently in auto mode */ 1316 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1317 /* Save the current zone channel assignment */ 1318 data->pwm_acz[ix] = PWM_ACZ_FROM_REG( 1319 data->pwm_config[ix]); 1320 /* Save the current ramp rate state and disable it */ 1321 data->pwm_rr[ix > 0] = dme1737_read(data, 1322 DME1737_REG_PWM_RR(ix > 0)); 1323 data->pwm_rr_en &= ~(1 << ix); 1324 if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) { 1325 data->pwm_rr_en |= (1 << ix); 1326 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix, 1327 data->pwm_rr[ix > 0]); 1328 dme1737_write(data, 1329 DME1737_REG_PWM_RR(ix > 0), 1330 data->pwm_rr[ix > 0]); 1331 } 1332 } 1333 /* Set the new PWM mode */ 1334 switch (val) { 1335 case 0: 1336 /* Change permissions of pwm[ix] to read-only */ 1337 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1338 S_IRUGO); 1339 /* Turn fan fully on */ 1340 data->pwm_config[ix] = PWM_EN_TO_REG(0, 1341 data->pwm_config[ix]); 1342 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1343 data->pwm_config[ix]); 1344 break; 1345 case 1: 1346 /* Turn on manual mode */ 1347 data->pwm_config[ix] = PWM_EN_TO_REG(1, 1348 data->pwm_config[ix]); 1349 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1350 data->pwm_config[ix]); 1351 /* Change permissions of pwm[ix] to read-writeable */ 1352 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1353 S_IRUGO | S_IWUSR); 1354 break; 1355 case 2: 1356 /* Change permissions of pwm[ix] to read-only */ 1357 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1358 S_IRUGO); 1359 /* 1360 * Turn on auto mode using the saved zone channel 1361 * assignment 1362 */ 1363 data->pwm_config[ix] = PWM_ACZ_TO_REG( 1364 data->pwm_acz[ix], 1365 data->pwm_config[ix]); 1366 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1367 data->pwm_config[ix]); 1368 /* Enable PWM ramp rate if previously enabled */ 1369 if (data->pwm_rr_en & (1 << ix)) { 1370 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix, 1371 dme1737_read(data, 1372 DME1737_REG_PWM_RR(ix > 0))); 1373 dme1737_write(data, 1374 DME1737_REG_PWM_RR(ix > 0), 1375 data->pwm_rr[ix > 0]); 1376 } 1377 break; 1378 } 1379 break; 1380 case SYS_PWM_RAMP_RATE: 1381 /* Only valid for pwm[1-3] */ 1382 /* Refresh the cache */ 1383 data->pwm_config[ix] = dme1737_read(data, 1384 DME1737_REG_PWM_CONFIG(ix)); 1385 data->pwm_rr[ix > 0] = dme1737_read(data, 1386 DME1737_REG_PWM_RR(ix > 0)); 1387 /* Set the ramp rate value */ 1388 if (val > 0) { 1389 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix, 1390 data->pwm_rr[ix > 0]); 1391 } 1392 /* 1393 * Enable/disable the feature only if the associated PWM 1394 * output is in automatic mode. 1395 */ 1396 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1397 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix, 1398 data->pwm_rr[ix > 0]); 1399 } 1400 dme1737_write(data, DME1737_REG_PWM_RR(ix > 0), 1401 data->pwm_rr[ix > 0]); 1402 break; 1403 case SYS_PWM_AUTO_CHANNELS_ZONE: 1404 /* Only valid for pwm[1-3] */ 1405 if (!(val == 1 || val == 2 || val == 4 || 1406 val == 6 || val == 7)) { 1407 count = -EINVAL; 1408 dev_warn(dev, 1409 "PWM auto channels zone %ld not supported. Choose one of 1, 2, 4, 6, " 1410 "or 7.\n", val); 1411 goto exit; 1412 } 1413 /* Refresh the cache */ 1414 data->pwm_config[ix] = dme1737_read(data, 1415 DME1737_REG_PWM_CONFIG(ix)); 1416 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1417 /* 1418 * PWM is already in auto mode so update the temp 1419 * channel assignment 1420 */ 1421 data->pwm_config[ix] = PWM_ACZ_TO_REG(val, 1422 data->pwm_config[ix]); 1423 dme1737_write(data, DME1737_REG_PWM_CONFIG(ix), 1424 data->pwm_config[ix]); 1425 } else { 1426 /* 1427 * PWM is not in auto mode so we save the temp 1428 * channel assignment for later use 1429 */ 1430 data->pwm_acz[ix] = val; 1431 } 1432 break; 1433 case SYS_PWM_AUTO_PWM_MIN: 1434 /* Only valid for pwm[1-3] */ 1435 /* Refresh the cache */ 1436 data->pwm_min[ix] = dme1737_read(data, 1437 DME1737_REG_PWM_MIN(ix)); 1438 /* 1439 * There are only 2 values supported for the auto_pwm_min 1440 * value: 0 or auto_point1_pwm. So if the temperature drops 1441 * below the auto_point1_temp_hyst value, the fan either turns 1442 * off or runs at auto_point1_pwm duty-cycle. 1443 */ 1444 if (val > ((data->pwm_min[ix] + 1) / 2)) { 1445 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix, 1446 dme1737_read(data, 1447 DME1737_REG_PWM_RR(0))); 1448 } else { 1449 data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix, 1450 dme1737_read(data, 1451 DME1737_REG_PWM_RR(0))); 1452 } 1453 dme1737_write(data, DME1737_REG_PWM_RR(0), 1454 data->pwm_rr[0]); 1455 break; 1456 case SYS_PWM_AUTO_POINT1_PWM: 1457 /* Only valid for pwm[1-3] */ 1458 data->pwm_min[ix] = clamp_val(val, 0, 255); 1459 dme1737_write(data, DME1737_REG_PWM_MIN(ix), 1460 data->pwm_min[ix]); 1461 break; 1462 default: 1463 dev_dbg(dev, "Unknown function %d.\n", fn); 1464 } 1465 exit: 1466 mutex_unlock(&data->update_lock); 1467 1468 return count; 1469 } 1470 1471 /* --------------------------------------------------------------------- 1472 * Miscellaneous sysfs attributes 1473 * --------------------------------------------------------------------- */ 1474 1475 static ssize_t vrm_show(struct device *dev, struct device_attribute *attr, 1476 char *buf) 1477 { 1478 struct i2c_client *client = to_i2c_client(dev); 1479 struct dme1737_data *data = i2c_get_clientdata(client); 1480 1481 return sprintf(buf, "%d\n", data->vrm); 1482 } 1483 1484 static ssize_t vrm_store(struct device *dev, struct device_attribute *attr, 1485 const char *buf, size_t count) 1486 { 1487 struct dme1737_data *data = dev_get_drvdata(dev); 1488 unsigned long val; 1489 int err; 1490 1491 err = kstrtoul(buf, 10, &val); 1492 if (err) 1493 return err; 1494 1495 if (val > 255) 1496 return -EINVAL; 1497 1498 data->vrm = val; 1499 return count; 1500 } 1501 1502 static ssize_t cpu0_vid_show(struct device *dev, 1503 struct device_attribute *attr, char *buf) 1504 { 1505 struct dme1737_data *data = dme1737_update_device(dev); 1506 1507 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm)); 1508 } 1509 1510 static ssize_t name_show(struct device *dev, struct device_attribute *attr, 1511 char *buf) 1512 { 1513 struct dme1737_data *data = dev_get_drvdata(dev); 1514 1515 return sprintf(buf, "%s\n", data->name); 1516 } 1517 1518 /* --------------------------------------------------------------------- 1519 * Sysfs device attribute defines and structs 1520 * --------------------------------------------------------------------- */ 1521 1522 /* Voltages 0-7 */ 1523 1524 #define SENSOR_DEVICE_ATTR_IN(ix) \ 1525 static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \ 1526 show_in, NULL, SYS_IN_INPUT, ix); \ 1527 static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \ 1528 show_in, set_in, SYS_IN_MIN, ix); \ 1529 static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \ 1530 show_in, set_in, SYS_IN_MAX, ix); \ 1531 static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \ 1532 show_in, NULL, SYS_IN_ALARM, ix) 1533 1534 SENSOR_DEVICE_ATTR_IN(0); 1535 SENSOR_DEVICE_ATTR_IN(1); 1536 SENSOR_DEVICE_ATTR_IN(2); 1537 SENSOR_DEVICE_ATTR_IN(3); 1538 SENSOR_DEVICE_ATTR_IN(4); 1539 SENSOR_DEVICE_ATTR_IN(5); 1540 SENSOR_DEVICE_ATTR_IN(6); 1541 SENSOR_DEVICE_ATTR_IN(7); 1542 1543 /* Temperatures 1-3 */ 1544 1545 #define SENSOR_DEVICE_ATTR_TEMP(ix) \ 1546 static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \ 1547 show_temp, NULL, SYS_TEMP_INPUT, ix-1); \ 1548 static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \ 1549 show_temp, set_temp, SYS_TEMP_MIN, ix-1); \ 1550 static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \ 1551 show_temp, set_temp, SYS_TEMP_MAX, ix-1); \ 1552 static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \ 1553 show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \ 1554 static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \ 1555 show_temp, NULL, SYS_TEMP_ALARM, ix-1); \ 1556 static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \ 1557 show_temp, NULL, SYS_TEMP_FAULT, ix-1) 1558 1559 SENSOR_DEVICE_ATTR_TEMP(1); 1560 SENSOR_DEVICE_ATTR_TEMP(2); 1561 SENSOR_DEVICE_ATTR_TEMP(3); 1562 1563 /* Zones 1-3 */ 1564 1565 #define SENSOR_DEVICE_ATTR_ZONE(ix) \ 1566 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \ 1567 show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \ 1568 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \ 1569 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \ 1570 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \ 1571 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \ 1572 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \ 1573 show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \ 1574 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \ 1575 show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1) 1576 1577 SENSOR_DEVICE_ATTR_ZONE(1); 1578 SENSOR_DEVICE_ATTR_ZONE(2); 1579 SENSOR_DEVICE_ATTR_ZONE(3); 1580 1581 /* Fans 1-4 */ 1582 1583 #define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \ 1584 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \ 1585 show_fan, NULL, SYS_FAN_INPUT, ix-1); \ 1586 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \ 1587 show_fan, set_fan, SYS_FAN_MIN, ix-1); \ 1588 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \ 1589 show_fan, NULL, SYS_FAN_ALARM, ix-1); \ 1590 static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \ 1591 show_fan, set_fan, SYS_FAN_TYPE, ix-1) 1592 1593 SENSOR_DEVICE_ATTR_FAN_1TO4(1); 1594 SENSOR_DEVICE_ATTR_FAN_1TO4(2); 1595 SENSOR_DEVICE_ATTR_FAN_1TO4(3); 1596 SENSOR_DEVICE_ATTR_FAN_1TO4(4); 1597 1598 /* Fans 5-6 */ 1599 1600 #define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \ 1601 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \ 1602 show_fan, NULL, SYS_FAN_INPUT, ix-1); \ 1603 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \ 1604 show_fan, set_fan, SYS_FAN_MIN, ix-1); \ 1605 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \ 1606 show_fan, NULL, SYS_FAN_ALARM, ix-1); \ 1607 static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \ 1608 show_fan, set_fan, SYS_FAN_MAX, ix-1) 1609 1610 SENSOR_DEVICE_ATTR_FAN_5TO6(5); 1611 SENSOR_DEVICE_ATTR_FAN_5TO6(6); 1612 1613 /* PWMs 1-3 */ 1614 1615 #define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \ 1616 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \ 1617 show_pwm, set_pwm, SYS_PWM, ix-1); \ 1618 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \ 1619 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \ 1620 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \ 1621 show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \ 1622 static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \ 1623 show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \ 1624 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \ 1625 show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \ 1626 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \ 1627 show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \ 1628 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \ 1629 show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \ 1630 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \ 1631 show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1) 1632 1633 SENSOR_DEVICE_ATTR_PWM_1TO3(1); 1634 SENSOR_DEVICE_ATTR_PWM_1TO3(2); 1635 SENSOR_DEVICE_ATTR_PWM_1TO3(3); 1636 1637 /* PWMs 5-6 */ 1638 1639 #define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \ 1640 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \ 1641 show_pwm, set_pwm, SYS_PWM, ix-1); \ 1642 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \ 1643 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \ 1644 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \ 1645 show_pwm, NULL, SYS_PWM_ENABLE, ix-1) 1646 1647 SENSOR_DEVICE_ATTR_PWM_5TO6(5); 1648 SENSOR_DEVICE_ATTR_PWM_5TO6(6); 1649 1650 /* Misc */ 1651 1652 static DEVICE_ATTR_RW(vrm); 1653 static DEVICE_ATTR_RO(cpu0_vid); 1654 static DEVICE_ATTR_RO(name); /* for ISA devices */ 1655 1656 /* 1657 * This struct holds all the attributes that are always present and need to be 1658 * created unconditionally. The attributes that need modification of their 1659 * permissions are created read-only and write permissions are added or removed 1660 * on the fly when required 1661 */ 1662 static struct attribute *dme1737_attr[] = { 1663 /* Voltages */ 1664 &sensor_dev_attr_in0_input.dev_attr.attr, 1665 &sensor_dev_attr_in0_min.dev_attr.attr, 1666 &sensor_dev_attr_in0_max.dev_attr.attr, 1667 &sensor_dev_attr_in0_alarm.dev_attr.attr, 1668 &sensor_dev_attr_in1_input.dev_attr.attr, 1669 &sensor_dev_attr_in1_min.dev_attr.attr, 1670 &sensor_dev_attr_in1_max.dev_attr.attr, 1671 &sensor_dev_attr_in1_alarm.dev_attr.attr, 1672 &sensor_dev_attr_in2_input.dev_attr.attr, 1673 &sensor_dev_attr_in2_min.dev_attr.attr, 1674 &sensor_dev_attr_in2_max.dev_attr.attr, 1675 &sensor_dev_attr_in2_alarm.dev_attr.attr, 1676 &sensor_dev_attr_in3_input.dev_attr.attr, 1677 &sensor_dev_attr_in3_min.dev_attr.attr, 1678 &sensor_dev_attr_in3_max.dev_attr.attr, 1679 &sensor_dev_attr_in3_alarm.dev_attr.attr, 1680 &sensor_dev_attr_in4_input.dev_attr.attr, 1681 &sensor_dev_attr_in4_min.dev_attr.attr, 1682 &sensor_dev_attr_in4_max.dev_attr.attr, 1683 &sensor_dev_attr_in4_alarm.dev_attr.attr, 1684 &sensor_dev_attr_in5_input.dev_attr.attr, 1685 &sensor_dev_attr_in5_min.dev_attr.attr, 1686 &sensor_dev_attr_in5_max.dev_attr.attr, 1687 &sensor_dev_attr_in5_alarm.dev_attr.attr, 1688 &sensor_dev_attr_in6_input.dev_attr.attr, 1689 &sensor_dev_attr_in6_min.dev_attr.attr, 1690 &sensor_dev_attr_in6_max.dev_attr.attr, 1691 &sensor_dev_attr_in6_alarm.dev_attr.attr, 1692 /* Temperatures */ 1693 &sensor_dev_attr_temp1_input.dev_attr.attr, 1694 &sensor_dev_attr_temp1_min.dev_attr.attr, 1695 &sensor_dev_attr_temp1_max.dev_attr.attr, 1696 &sensor_dev_attr_temp1_alarm.dev_attr.attr, 1697 &sensor_dev_attr_temp1_fault.dev_attr.attr, 1698 &sensor_dev_attr_temp2_input.dev_attr.attr, 1699 &sensor_dev_attr_temp2_min.dev_attr.attr, 1700 &sensor_dev_attr_temp2_max.dev_attr.attr, 1701 &sensor_dev_attr_temp2_alarm.dev_attr.attr, 1702 &sensor_dev_attr_temp2_fault.dev_attr.attr, 1703 &sensor_dev_attr_temp3_input.dev_attr.attr, 1704 &sensor_dev_attr_temp3_min.dev_attr.attr, 1705 &sensor_dev_attr_temp3_max.dev_attr.attr, 1706 &sensor_dev_attr_temp3_alarm.dev_attr.attr, 1707 &sensor_dev_attr_temp3_fault.dev_attr.attr, 1708 /* Zones */ 1709 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, 1710 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, 1711 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, 1712 &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr, 1713 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, 1714 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, 1715 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, 1716 &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr, 1717 NULL 1718 }; 1719 1720 static const struct attribute_group dme1737_group = { 1721 .attrs = dme1737_attr, 1722 }; 1723 1724 /* 1725 * The following struct holds temp offset attributes, which are not available 1726 * in all chips. The following chips support them: 1727 * DME1737, SCH311x 1728 */ 1729 static struct attribute *dme1737_temp_offset_attr[] = { 1730 &sensor_dev_attr_temp1_offset.dev_attr.attr, 1731 &sensor_dev_attr_temp2_offset.dev_attr.attr, 1732 &sensor_dev_attr_temp3_offset.dev_attr.attr, 1733 NULL 1734 }; 1735 1736 static const struct attribute_group dme1737_temp_offset_group = { 1737 .attrs = dme1737_temp_offset_attr, 1738 }; 1739 1740 /* 1741 * The following struct holds VID related attributes, which are not available 1742 * in all chips. The following chips support them: 1743 * DME1737 1744 */ 1745 static struct attribute *dme1737_vid_attr[] = { 1746 &dev_attr_vrm.attr, 1747 &dev_attr_cpu0_vid.attr, 1748 NULL 1749 }; 1750 1751 static const struct attribute_group dme1737_vid_group = { 1752 .attrs = dme1737_vid_attr, 1753 }; 1754 1755 /* 1756 * The following struct holds temp zone 3 related attributes, which are not 1757 * available in all chips. The following chips support them: 1758 * DME1737, SCH311x, SCH5027 1759 */ 1760 static struct attribute *dme1737_zone3_attr[] = { 1761 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, 1762 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, 1763 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, 1764 &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr, 1765 NULL 1766 }; 1767 1768 static const struct attribute_group dme1737_zone3_group = { 1769 .attrs = dme1737_zone3_attr, 1770 }; 1771 1772 1773 /* 1774 * The following struct holds temp zone hysteresis related attributes, which 1775 * are not available in all chips. The following chips support them: 1776 * DME1737, SCH311x 1777 */ 1778 static struct attribute *dme1737_zone_hyst_attr[] = { 1779 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr, 1780 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr, 1781 &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr, 1782 NULL 1783 }; 1784 1785 static const struct attribute_group dme1737_zone_hyst_group = { 1786 .attrs = dme1737_zone_hyst_attr, 1787 }; 1788 1789 /* 1790 * The following struct holds voltage in7 related attributes, which 1791 * are not available in all chips. The following chips support them: 1792 * SCH5127 1793 */ 1794 static struct attribute *dme1737_in7_attr[] = { 1795 &sensor_dev_attr_in7_input.dev_attr.attr, 1796 &sensor_dev_attr_in7_min.dev_attr.attr, 1797 &sensor_dev_attr_in7_max.dev_attr.attr, 1798 &sensor_dev_attr_in7_alarm.dev_attr.attr, 1799 NULL 1800 }; 1801 1802 static const struct attribute_group dme1737_in7_group = { 1803 .attrs = dme1737_in7_attr, 1804 }; 1805 1806 /* 1807 * The following structs hold the PWM attributes, some of which are optional. 1808 * Their creation depends on the chip configuration which is determined during 1809 * module load. 1810 */ 1811 static struct attribute *dme1737_pwm1_attr[] = { 1812 &sensor_dev_attr_pwm1.dev_attr.attr, 1813 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 1814 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1815 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, 1816 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, 1817 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 1818 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, 1819 NULL 1820 }; 1821 static struct attribute *dme1737_pwm2_attr[] = { 1822 &sensor_dev_attr_pwm2.dev_attr.attr, 1823 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 1824 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 1825 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, 1826 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, 1827 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, 1828 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, 1829 NULL 1830 }; 1831 static struct attribute *dme1737_pwm3_attr[] = { 1832 &sensor_dev_attr_pwm3.dev_attr.attr, 1833 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 1834 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 1835 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, 1836 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, 1837 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, 1838 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, 1839 NULL 1840 }; 1841 static struct attribute *dme1737_pwm5_attr[] = { 1842 &sensor_dev_attr_pwm5.dev_attr.attr, 1843 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 1844 &sensor_dev_attr_pwm5_enable.dev_attr.attr, 1845 NULL 1846 }; 1847 static struct attribute *dme1737_pwm6_attr[] = { 1848 &sensor_dev_attr_pwm6.dev_attr.attr, 1849 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 1850 &sensor_dev_attr_pwm6_enable.dev_attr.attr, 1851 NULL 1852 }; 1853 1854 static const struct attribute_group dme1737_pwm_group[] = { 1855 { .attrs = dme1737_pwm1_attr }, 1856 { .attrs = dme1737_pwm2_attr }, 1857 { .attrs = dme1737_pwm3_attr }, 1858 { .attrs = NULL }, 1859 { .attrs = dme1737_pwm5_attr }, 1860 { .attrs = dme1737_pwm6_attr }, 1861 }; 1862 1863 /* 1864 * The following struct holds auto PWM min attributes, which are not available 1865 * in all chips. Their creation depends on the chip type which is determined 1866 * during module load. 1867 */ 1868 static struct attribute *dme1737_auto_pwm_min_attr[] = { 1869 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr, 1870 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr, 1871 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr, 1872 }; 1873 1874 /* 1875 * The following structs hold the fan attributes, some of which are optional. 1876 * Their creation depends on the chip configuration which is determined during 1877 * module load. 1878 */ 1879 static struct attribute *dme1737_fan1_attr[] = { 1880 &sensor_dev_attr_fan1_input.dev_attr.attr, 1881 &sensor_dev_attr_fan1_min.dev_attr.attr, 1882 &sensor_dev_attr_fan1_alarm.dev_attr.attr, 1883 &sensor_dev_attr_fan1_type.dev_attr.attr, 1884 NULL 1885 }; 1886 static struct attribute *dme1737_fan2_attr[] = { 1887 &sensor_dev_attr_fan2_input.dev_attr.attr, 1888 &sensor_dev_attr_fan2_min.dev_attr.attr, 1889 &sensor_dev_attr_fan2_alarm.dev_attr.attr, 1890 &sensor_dev_attr_fan2_type.dev_attr.attr, 1891 NULL 1892 }; 1893 static struct attribute *dme1737_fan3_attr[] = { 1894 &sensor_dev_attr_fan3_input.dev_attr.attr, 1895 &sensor_dev_attr_fan3_min.dev_attr.attr, 1896 &sensor_dev_attr_fan3_alarm.dev_attr.attr, 1897 &sensor_dev_attr_fan3_type.dev_attr.attr, 1898 NULL 1899 }; 1900 static struct attribute *dme1737_fan4_attr[] = { 1901 &sensor_dev_attr_fan4_input.dev_attr.attr, 1902 &sensor_dev_attr_fan4_min.dev_attr.attr, 1903 &sensor_dev_attr_fan4_alarm.dev_attr.attr, 1904 &sensor_dev_attr_fan4_type.dev_attr.attr, 1905 NULL 1906 }; 1907 static struct attribute *dme1737_fan5_attr[] = { 1908 &sensor_dev_attr_fan5_input.dev_attr.attr, 1909 &sensor_dev_attr_fan5_min.dev_attr.attr, 1910 &sensor_dev_attr_fan5_alarm.dev_attr.attr, 1911 &sensor_dev_attr_fan5_max.dev_attr.attr, 1912 NULL 1913 }; 1914 static struct attribute *dme1737_fan6_attr[] = { 1915 &sensor_dev_attr_fan6_input.dev_attr.attr, 1916 &sensor_dev_attr_fan6_min.dev_attr.attr, 1917 &sensor_dev_attr_fan6_alarm.dev_attr.attr, 1918 &sensor_dev_attr_fan6_max.dev_attr.attr, 1919 NULL 1920 }; 1921 1922 static const struct attribute_group dme1737_fan_group[] = { 1923 { .attrs = dme1737_fan1_attr }, 1924 { .attrs = dme1737_fan2_attr }, 1925 { .attrs = dme1737_fan3_attr }, 1926 { .attrs = dme1737_fan4_attr }, 1927 { .attrs = dme1737_fan5_attr }, 1928 { .attrs = dme1737_fan6_attr }, 1929 }; 1930 1931 /* 1932 * The permissions of the following zone attributes are changed to read- 1933 * writeable if the chip is *not* locked. Otherwise they stay read-only. 1934 */ 1935 static struct attribute *dme1737_zone_chmod_attr[] = { 1936 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, 1937 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, 1938 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, 1939 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, 1940 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, 1941 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, 1942 NULL 1943 }; 1944 1945 static const struct attribute_group dme1737_zone_chmod_group = { 1946 .attrs = dme1737_zone_chmod_attr, 1947 }; 1948 1949 1950 /* 1951 * The permissions of the following zone 3 attributes are changed to read- 1952 * writeable if the chip is *not* locked. Otherwise they stay read-only. 1953 */ 1954 static struct attribute *dme1737_zone3_chmod_attr[] = { 1955 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, 1956 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, 1957 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, 1958 NULL 1959 }; 1960 1961 static const struct attribute_group dme1737_zone3_chmod_group = { 1962 .attrs = dme1737_zone3_chmod_attr, 1963 }; 1964 1965 /* 1966 * The permissions of the following PWM attributes are changed to read- 1967 * writeable if the chip is *not* locked and the respective PWM is available. 1968 * Otherwise they stay read-only. 1969 */ 1970 static struct attribute *dme1737_pwm1_chmod_attr[] = { 1971 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 1972 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1973 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, 1974 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, 1975 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 1976 NULL 1977 }; 1978 static struct attribute *dme1737_pwm2_chmod_attr[] = { 1979 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 1980 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 1981 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, 1982 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, 1983 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, 1984 NULL 1985 }; 1986 static struct attribute *dme1737_pwm3_chmod_attr[] = { 1987 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 1988 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 1989 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, 1990 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, 1991 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, 1992 NULL 1993 }; 1994 static struct attribute *dme1737_pwm5_chmod_attr[] = { 1995 &sensor_dev_attr_pwm5.dev_attr.attr, 1996 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 1997 NULL 1998 }; 1999 static struct attribute *dme1737_pwm6_chmod_attr[] = { 2000 &sensor_dev_attr_pwm6.dev_attr.attr, 2001 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 2002 NULL 2003 }; 2004 2005 static const struct attribute_group dme1737_pwm_chmod_group[] = { 2006 { .attrs = dme1737_pwm1_chmod_attr }, 2007 { .attrs = dme1737_pwm2_chmod_attr }, 2008 { .attrs = dme1737_pwm3_chmod_attr }, 2009 { .attrs = NULL }, 2010 { .attrs = dme1737_pwm5_chmod_attr }, 2011 { .attrs = dme1737_pwm6_chmod_attr }, 2012 }; 2013 2014 /* 2015 * Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the 2016 * chip is not locked. Otherwise they are read-only. 2017 */ 2018 static struct attribute *dme1737_pwm_chmod_attr[] = { 2019 &sensor_dev_attr_pwm1.dev_attr.attr, 2020 &sensor_dev_attr_pwm2.dev_attr.attr, 2021 &sensor_dev_attr_pwm3.dev_attr.attr, 2022 }; 2023 2024 /* --------------------------------------------------------------------- 2025 * Super-IO functions 2026 * --------------------------------------------------------------------- */ 2027 2028 static inline void dme1737_sio_enter(int sio_cip) 2029 { 2030 outb(0x55, sio_cip); 2031 } 2032 2033 static inline void dme1737_sio_exit(int sio_cip) 2034 { 2035 outb(0xaa, sio_cip); 2036 } 2037 2038 static inline int dme1737_sio_inb(int sio_cip, int reg) 2039 { 2040 outb(reg, sio_cip); 2041 return inb(sio_cip + 1); 2042 } 2043 2044 static inline void dme1737_sio_outb(int sio_cip, int reg, int val) 2045 { 2046 outb(reg, sio_cip); 2047 outb(val, sio_cip + 1); 2048 } 2049 2050 /* --------------------------------------------------------------------- 2051 * Device initialization 2052 * --------------------------------------------------------------------- */ 2053 2054 static int dme1737_i2c_get_features(int, struct dme1737_data*); 2055 2056 static void dme1737_chmod_file(struct device *dev, 2057 struct attribute *attr, umode_t mode) 2058 { 2059 if (sysfs_chmod_file(&dev->kobj, attr, mode)) { 2060 dev_warn(dev, "Failed to change permissions of %s.\n", 2061 attr->name); 2062 } 2063 } 2064 2065 static void dme1737_chmod_group(struct device *dev, 2066 const struct attribute_group *group, 2067 umode_t mode) 2068 { 2069 struct attribute **attr; 2070 2071 for (attr = group->attrs; *attr; attr++) 2072 dme1737_chmod_file(dev, *attr, mode); 2073 } 2074 2075 static void dme1737_remove_files(struct device *dev) 2076 { 2077 struct dme1737_data *data = dev_get_drvdata(dev); 2078 int ix; 2079 2080 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { 2081 if (data->has_features & HAS_FAN(ix)) { 2082 sysfs_remove_group(&dev->kobj, 2083 &dme1737_fan_group[ix]); 2084 } 2085 } 2086 2087 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) { 2088 if (data->has_features & HAS_PWM(ix)) { 2089 sysfs_remove_group(&dev->kobj, 2090 &dme1737_pwm_group[ix]); 2091 if ((data->has_features & HAS_PWM_MIN) && ix < 3) { 2092 sysfs_remove_file(&dev->kobj, 2093 dme1737_auto_pwm_min_attr[ix]); 2094 } 2095 } 2096 } 2097 2098 if (data->has_features & HAS_TEMP_OFFSET) 2099 sysfs_remove_group(&dev->kobj, &dme1737_temp_offset_group); 2100 if (data->has_features & HAS_VID) 2101 sysfs_remove_group(&dev->kobj, &dme1737_vid_group); 2102 if (data->has_features & HAS_ZONE3) 2103 sysfs_remove_group(&dev->kobj, &dme1737_zone3_group); 2104 if (data->has_features & HAS_ZONE_HYST) 2105 sysfs_remove_group(&dev->kobj, &dme1737_zone_hyst_group); 2106 if (data->has_features & HAS_IN7) 2107 sysfs_remove_group(&dev->kobj, &dme1737_in7_group); 2108 sysfs_remove_group(&dev->kobj, &dme1737_group); 2109 2110 if (!data->client) 2111 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr); 2112 } 2113 2114 static int dme1737_create_files(struct device *dev) 2115 { 2116 struct dme1737_data *data = dev_get_drvdata(dev); 2117 int err, ix; 2118 2119 /* Create a name attribute for ISA devices */ 2120 if (!data->client) { 2121 err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr); 2122 if (err) 2123 goto exit; 2124 } 2125 2126 /* Create standard sysfs attributes */ 2127 err = sysfs_create_group(&dev->kobj, &dme1737_group); 2128 if (err) 2129 goto exit_remove; 2130 2131 /* Create chip-dependent sysfs attributes */ 2132 if (data->has_features & HAS_TEMP_OFFSET) { 2133 err = sysfs_create_group(&dev->kobj, 2134 &dme1737_temp_offset_group); 2135 if (err) 2136 goto exit_remove; 2137 } 2138 if (data->has_features & HAS_VID) { 2139 err = sysfs_create_group(&dev->kobj, &dme1737_vid_group); 2140 if (err) 2141 goto exit_remove; 2142 } 2143 if (data->has_features & HAS_ZONE3) { 2144 err = sysfs_create_group(&dev->kobj, &dme1737_zone3_group); 2145 if (err) 2146 goto exit_remove; 2147 } 2148 if (data->has_features & HAS_ZONE_HYST) { 2149 err = sysfs_create_group(&dev->kobj, &dme1737_zone_hyst_group); 2150 if (err) 2151 goto exit_remove; 2152 } 2153 if (data->has_features & HAS_IN7) { 2154 err = sysfs_create_group(&dev->kobj, &dme1737_in7_group); 2155 if (err) 2156 goto exit_remove; 2157 } 2158 2159 /* Create fan sysfs attributes */ 2160 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { 2161 if (data->has_features & HAS_FAN(ix)) { 2162 err = sysfs_create_group(&dev->kobj, 2163 &dme1737_fan_group[ix]); 2164 if (err) 2165 goto exit_remove; 2166 } 2167 } 2168 2169 /* Create PWM sysfs attributes */ 2170 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) { 2171 if (data->has_features & HAS_PWM(ix)) { 2172 err = sysfs_create_group(&dev->kobj, 2173 &dme1737_pwm_group[ix]); 2174 if (err) 2175 goto exit_remove; 2176 if ((data->has_features & HAS_PWM_MIN) && (ix < 3)) { 2177 err = sysfs_create_file(&dev->kobj, 2178 dme1737_auto_pwm_min_attr[ix]); 2179 if (err) 2180 goto exit_remove; 2181 } 2182 } 2183 } 2184 2185 /* 2186 * Inform if the device is locked. Otherwise change the permissions of 2187 * selected attributes from read-only to read-writeable. 2188 */ 2189 if (data->config & 0x02) { 2190 dev_info(dev, 2191 "Device is locked. Some attributes will be read-only.\n"); 2192 } else { 2193 /* Change permissions of zone sysfs attributes */ 2194 dme1737_chmod_group(dev, &dme1737_zone_chmod_group, 2195 S_IRUGO | S_IWUSR); 2196 2197 /* Change permissions of chip-dependent sysfs attributes */ 2198 if (data->has_features & HAS_TEMP_OFFSET) { 2199 dme1737_chmod_group(dev, &dme1737_temp_offset_group, 2200 S_IRUGO | S_IWUSR); 2201 } 2202 if (data->has_features & HAS_ZONE3) { 2203 dme1737_chmod_group(dev, &dme1737_zone3_chmod_group, 2204 S_IRUGO | S_IWUSR); 2205 } 2206 if (data->has_features & HAS_ZONE_HYST) { 2207 dme1737_chmod_group(dev, &dme1737_zone_hyst_group, 2208 S_IRUGO | S_IWUSR); 2209 } 2210 2211 /* Change permissions of PWM sysfs attributes */ 2212 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) { 2213 if (data->has_features & HAS_PWM(ix)) { 2214 dme1737_chmod_group(dev, 2215 &dme1737_pwm_chmod_group[ix], 2216 S_IRUGO | S_IWUSR); 2217 if ((data->has_features & HAS_PWM_MIN) && 2218 ix < 3) { 2219 dme1737_chmod_file(dev, 2220 dme1737_auto_pwm_min_attr[ix], 2221 S_IRUGO | S_IWUSR); 2222 } 2223 } 2224 } 2225 2226 /* Change permissions of pwm[1-3] if in manual mode */ 2227 for (ix = 0; ix < 3; ix++) { 2228 if ((data->has_features & HAS_PWM(ix)) && 2229 (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) { 2230 dme1737_chmod_file(dev, 2231 dme1737_pwm_chmod_attr[ix], 2232 S_IRUGO | S_IWUSR); 2233 } 2234 } 2235 } 2236 2237 return 0; 2238 2239 exit_remove: 2240 dme1737_remove_files(dev); 2241 exit: 2242 return err; 2243 } 2244 2245 static int dme1737_init_device(struct device *dev) 2246 { 2247 struct dme1737_data *data = dev_get_drvdata(dev); 2248 struct i2c_client *client = data->client; 2249 int ix; 2250 u8 reg; 2251 2252 /* Point to the right nominal voltages array */ 2253 data->in_nominal = IN_NOMINAL(data->type); 2254 2255 data->config = dme1737_read(data, DME1737_REG_CONFIG); 2256 /* Inform if part is not monitoring/started */ 2257 if (!(data->config & 0x01)) { 2258 if (!force_start) { 2259 dev_err(dev, 2260 "Device is not monitoring. Use the force_start load parameter to override.\n"); 2261 return -EFAULT; 2262 } 2263 2264 /* Force monitoring */ 2265 data->config |= 0x01; 2266 dme1737_write(data, DME1737_REG_CONFIG, data->config); 2267 } 2268 /* Inform if part is not ready */ 2269 if (!(data->config & 0x04)) { 2270 dev_err(dev, "Device is not ready.\n"); 2271 return -EFAULT; 2272 } 2273 2274 /* 2275 * Determine which optional fan and pwm features are enabled (only 2276 * valid for I2C devices) 2277 */ 2278 if (client) { /* I2C chip */ 2279 data->config2 = dme1737_read(data, DME1737_REG_CONFIG2); 2280 /* Check if optional fan3 input is enabled */ 2281 if (data->config2 & 0x04) 2282 data->has_features |= HAS_FAN(2); 2283 2284 /* 2285 * Fan4 and pwm3 are only available if the client's I2C address 2286 * is the default 0x2e. Otherwise the I/Os associated with 2287 * these functions are used for addr enable/select. 2288 */ 2289 if (client->addr == 0x2e) 2290 data->has_features |= HAS_FAN(3) | HAS_PWM(2); 2291 2292 /* 2293 * Determine which of the optional fan[5-6] and pwm[5-6] 2294 * features are enabled. For this, we need to query the runtime 2295 * registers through the Super-IO LPC interface. Try both 2296 * config ports 0x2e and 0x4e. 2297 */ 2298 if (dme1737_i2c_get_features(0x2e, data) && 2299 dme1737_i2c_get_features(0x4e, data)) { 2300 dev_warn(dev, 2301 "Failed to query Super-IO for optional features.\n"); 2302 } 2303 } 2304 2305 /* Fan[1-2] and pwm[1-2] are present in all chips */ 2306 data->has_features |= HAS_FAN(0) | HAS_FAN(1) | HAS_PWM(0) | HAS_PWM(1); 2307 2308 /* Chip-dependent features */ 2309 switch (data->type) { 2310 case dme1737: 2311 data->has_features |= HAS_TEMP_OFFSET | HAS_VID | HAS_ZONE3 | 2312 HAS_ZONE_HYST | HAS_PWM_MIN; 2313 break; 2314 case sch311x: 2315 data->has_features |= HAS_TEMP_OFFSET | HAS_ZONE3 | 2316 HAS_ZONE_HYST | HAS_PWM_MIN | HAS_FAN(2) | HAS_PWM(2); 2317 break; 2318 case sch5027: 2319 data->has_features |= HAS_ZONE3; 2320 break; 2321 case sch5127: 2322 data->has_features |= HAS_FAN(2) | HAS_PWM(2) | HAS_IN7; 2323 break; 2324 default: 2325 break; 2326 } 2327 2328 dev_info(dev, 2329 "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n", 2330 (data->has_features & HAS_PWM(2)) ? "yes" : "no", 2331 (data->has_features & HAS_PWM(4)) ? "yes" : "no", 2332 (data->has_features & HAS_PWM(5)) ? "yes" : "no", 2333 (data->has_features & HAS_FAN(2)) ? "yes" : "no", 2334 (data->has_features & HAS_FAN(3)) ? "yes" : "no", 2335 (data->has_features & HAS_FAN(4)) ? "yes" : "no", 2336 (data->has_features & HAS_FAN(5)) ? "yes" : "no"); 2337 2338 reg = dme1737_read(data, DME1737_REG_TACH_PWM); 2339 /* Inform if fan-to-pwm mapping differs from the default */ 2340 if (client && reg != 0xa4) { /* I2C chip */ 2341 dev_warn(dev, 2342 "Non-standard fan to pwm mapping: fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, fan4->pwm%d. %s\n", 2343 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1, 2344 ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1, 2345 DO_REPORT); 2346 } else if (!client && reg != 0x24) { /* ISA chip */ 2347 dev_warn(dev, 2348 "Non-standard fan to pwm mapping: fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. %s\n", 2349 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1, 2350 ((reg >> 4) & 0x03) + 1, DO_REPORT); 2351 } 2352 2353 /* 2354 * Switch pwm[1-3] to manual mode if they are currently disabled and 2355 * set the duty-cycles to 0% (which is identical to the PWMs being 2356 * disabled). 2357 */ 2358 if (!(data->config & 0x02)) { 2359 for (ix = 0; ix < 3; ix++) { 2360 data->pwm_config[ix] = dme1737_read(data, 2361 DME1737_REG_PWM_CONFIG(ix)); 2362 if ((data->has_features & HAS_PWM(ix)) && 2363 (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) { 2364 dev_info(dev, 2365 "Switching pwm%d to manual mode.\n", 2366 ix + 1); 2367 data->pwm_config[ix] = PWM_EN_TO_REG(1, 2368 data->pwm_config[ix]); 2369 dme1737_write(data, DME1737_REG_PWM(ix), 0); 2370 dme1737_write(data, 2371 DME1737_REG_PWM_CONFIG(ix), 2372 data->pwm_config[ix]); 2373 } 2374 } 2375 } 2376 2377 /* Initialize the default PWM auto channels zone (acz) assignments */ 2378 data->pwm_acz[0] = 1; /* pwm1 -> zone1 */ 2379 data->pwm_acz[1] = 2; /* pwm2 -> zone2 */ 2380 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */ 2381 2382 /* Set VRM */ 2383 if (data->has_features & HAS_VID) 2384 data->vrm = vid_which_vrm(); 2385 2386 return 0; 2387 } 2388 2389 /* --------------------------------------------------------------------- 2390 * I2C device detection and registration 2391 * --------------------------------------------------------------------- */ 2392 2393 static struct i2c_driver dme1737_i2c_driver; 2394 2395 static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data) 2396 { 2397 int err = 0, reg; 2398 u16 addr; 2399 2400 dme1737_sio_enter(sio_cip); 2401 2402 /* 2403 * Check device ID 2404 * We currently know about two kinds of DME1737 and SCH5027. 2405 */ 2406 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); 2407 if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 || 2408 reg == SCH5027_ID)) { 2409 err = -ENODEV; 2410 goto exit; 2411 } 2412 2413 /* Select logical device A (runtime registers) */ 2414 dme1737_sio_outb(sio_cip, 0x07, 0x0a); 2415 2416 /* Get the base address of the runtime registers */ 2417 addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) | 2418 dme1737_sio_inb(sio_cip, 0x61); 2419 if (!addr) { 2420 err = -ENODEV; 2421 goto exit; 2422 } 2423 2424 /* 2425 * Read the runtime registers to determine which optional features 2426 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set 2427 * to '10' if the respective feature is enabled. 2428 */ 2429 if ((inb(addr + 0x43) & 0x0c) == 0x08) /* fan6 */ 2430 data->has_features |= HAS_FAN(5); 2431 if ((inb(addr + 0x44) & 0x0c) == 0x08) /* pwm6 */ 2432 data->has_features |= HAS_PWM(5); 2433 if ((inb(addr + 0x45) & 0x0c) == 0x08) /* fan5 */ 2434 data->has_features |= HAS_FAN(4); 2435 if ((inb(addr + 0x46) & 0x0c) == 0x08) /* pwm5 */ 2436 data->has_features |= HAS_PWM(4); 2437 2438 exit: 2439 dme1737_sio_exit(sio_cip); 2440 2441 return err; 2442 } 2443 2444 /* Return 0 if detection is successful, -ENODEV otherwise */ 2445 static int dme1737_i2c_detect(struct i2c_client *client, 2446 struct i2c_board_info *info) 2447 { 2448 struct i2c_adapter *adapter = client->adapter; 2449 struct device *dev = &adapter->dev; 2450 u8 company, verstep = 0; 2451 const char *name; 2452 2453 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2454 return -ENODEV; 2455 2456 company = i2c_smbus_read_byte_data(client, DME1737_REG_COMPANY); 2457 verstep = i2c_smbus_read_byte_data(client, DME1737_REG_VERSTEP); 2458 2459 if (company == DME1737_COMPANY_SMSC && 2460 verstep == SCH5027_VERSTEP) { 2461 name = "sch5027"; 2462 } else if (company == DME1737_COMPANY_SMSC && 2463 (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) { 2464 name = "dme1737"; 2465 } else { 2466 return -ENODEV; 2467 } 2468 2469 dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n", 2470 verstep == SCH5027_VERSTEP ? "SCH5027" : "DME1737", 2471 client->addr, verstep); 2472 strlcpy(info->type, name, I2C_NAME_SIZE); 2473 2474 return 0; 2475 } 2476 2477 static int dme1737_i2c_probe(struct i2c_client *client, 2478 const struct i2c_device_id *id) 2479 { 2480 struct dme1737_data *data; 2481 struct device *dev = &client->dev; 2482 int err; 2483 2484 data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL); 2485 if (!data) 2486 return -ENOMEM; 2487 2488 i2c_set_clientdata(client, data); 2489 data->type = id->driver_data; 2490 data->client = client; 2491 data->name = client->name; 2492 mutex_init(&data->update_lock); 2493 2494 /* Initialize the DME1737 chip */ 2495 err = dme1737_init_device(dev); 2496 if (err) { 2497 dev_err(dev, "Failed to initialize device.\n"); 2498 return err; 2499 } 2500 2501 /* Create sysfs files */ 2502 err = dme1737_create_files(dev); 2503 if (err) { 2504 dev_err(dev, "Failed to create sysfs files.\n"); 2505 return err; 2506 } 2507 2508 /* Register device */ 2509 data->hwmon_dev = hwmon_device_register(dev); 2510 if (IS_ERR(data->hwmon_dev)) { 2511 dev_err(dev, "Failed to register device.\n"); 2512 err = PTR_ERR(data->hwmon_dev); 2513 goto exit_remove; 2514 } 2515 2516 return 0; 2517 2518 exit_remove: 2519 dme1737_remove_files(dev); 2520 return err; 2521 } 2522 2523 static int dme1737_i2c_remove(struct i2c_client *client) 2524 { 2525 struct dme1737_data *data = i2c_get_clientdata(client); 2526 2527 hwmon_device_unregister(data->hwmon_dev); 2528 dme1737_remove_files(&client->dev); 2529 2530 return 0; 2531 } 2532 2533 static const struct i2c_device_id dme1737_id[] = { 2534 { "dme1737", dme1737 }, 2535 { "sch5027", sch5027 }, 2536 { } 2537 }; 2538 MODULE_DEVICE_TABLE(i2c, dme1737_id); 2539 2540 static struct i2c_driver dme1737_i2c_driver = { 2541 .class = I2C_CLASS_HWMON, 2542 .driver = { 2543 .name = "dme1737", 2544 }, 2545 .probe = dme1737_i2c_probe, 2546 .remove = dme1737_i2c_remove, 2547 .id_table = dme1737_id, 2548 .detect = dme1737_i2c_detect, 2549 .address_list = normal_i2c, 2550 }; 2551 2552 /* --------------------------------------------------------------------- 2553 * ISA device detection and registration 2554 * --------------------------------------------------------------------- */ 2555 2556 static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr) 2557 { 2558 int err = 0, reg; 2559 unsigned short base_addr; 2560 2561 dme1737_sio_enter(sio_cip); 2562 2563 /* 2564 * Check device ID 2565 * We currently know about SCH3112, SCH3114, SCH3116, and SCH5127 2566 */ 2567 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); 2568 if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID || 2569 reg == SCH5127_ID)) { 2570 err = -ENODEV; 2571 goto exit; 2572 } 2573 2574 /* Select logical device A (runtime registers) */ 2575 dme1737_sio_outb(sio_cip, 0x07, 0x0a); 2576 2577 /* Get the base address of the runtime registers */ 2578 base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) | 2579 dme1737_sio_inb(sio_cip, 0x61); 2580 if (!base_addr) { 2581 pr_err("Base address not set\n"); 2582 err = -ENODEV; 2583 goto exit; 2584 } 2585 2586 /* 2587 * Access to the hwmon registers is through an index/data register 2588 * pair located at offset 0x70/0x71. 2589 */ 2590 *addr = base_addr + 0x70; 2591 2592 exit: 2593 dme1737_sio_exit(sio_cip); 2594 return err; 2595 } 2596 2597 static int __init dme1737_isa_device_add(unsigned short addr) 2598 { 2599 struct resource res = { 2600 .start = addr, 2601 .end = addr + DME1737_EXTENT - 1, 2602 .name = "dme1737", 2603 .flags = IORESOURCE_IO, 2604 }; 2605 int err; 2606 2607 err = acpi_check_resource_conflict(&res); 2608 if (err) 2609 goto exit; 2610 2611 pdev = platform_device_alloc("dme1737", addr); 2612 if (!pdev) { 2613 pr_err("Failed to allocate device\n"); 2614 err = -ENOMEM; 2615 goto exit; 2616 } 2617 2618 err = platform_device_add_resources(pdev, &res, 1); 2619 if (err) { 2620 pr_err("Failed to add device resource (err = %d)\n", err); 2621 goto exit_device_put; 2622 } 2623 2624 err = platform_device_add(pdev); 2625 if (err) { 2626 pr_err("Failed to add device (err = %d)\n", err); 2627 goto exit_device_put; 2628 } 2629 2630 return 0; 2631 2632 exit_device_put: 2633 platform_device_put(pdev); 2634 pdev = NULL; 2635 exit: 2636 return err; 2637 } 2638 2639 static int dme1737_isa_probe(struct platform_device *pdev) 2640 { 2641 u8 company, device; 2642 struct resource *res; 2643 struct dme1737_data *data; 2644 struct device *dev = &pdev->dev; 2645 int err; 2646 2647 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 2648 if (!devm_request_region(dev, res->start, DME1737_EXTENT, "dme1737")) { 2649 dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n", 2650 (unsigned short)res->start, 2651 (unsigned short)res->start + DME1737_EXTENT - 1); 2652 return -EBUSY; 2653 } 2654 2655 data = devm_kzalloc(dev, sizeof(struct dme1737_data), GFP_KERNEL); 2656 if (!data) 2657 return -ENOMEM; 2658 2659 data->addr = res->start; 2660 platform_set_drvdata(pdev, data); 2661 2662 /* Skip chip detection if module is loaded with force_id parameter */ 2663 switch (force_id) { 2664 case SCH3112_ID: 2665 case SCH3114_ID: 2666 case SCH3116_ID: 2667 data->type = sch311x; 2668 break; 2669 case SCH5127_ID: 2670 data->type = sch5127; 2671 break; 2672 default: 2673 company = dme1737_read(data, DME1737_REG_COMPANY); 2674 device = dme1737_read(data, DME1737_REG_DEVICE); 2675 2676 if ((company == DME1737_COMPANY_SMSC) && 2677 (device == SCH311X_DEVICE)) { 2678 data->type = sch311x; 2679 } else if ((company == DME1737_COMPANY_SMSC) && 2680 (device == SCH5127_DEVICE)) { 2681 data->type = sch5127; 2682 } else { 2683 return -ENODEV; 2684 } 2685 } 2686 2687 if (data->type == sch5127) 2688 data->name = "sch5127"; 2689 else 2690 data->name = "sch311x"; 2691 2692 /* Initialize the mutex */ 2693 mutex_init(&data->update_lock); 2694 2695 dev_info(dev, "Found a %s chip at 0x%04x\n", 2696 data->type == sch5127 ? "SCH5127" : "SCH311x", data->addr); 2697 2698 /* Initialize the chip */ 2699 err = dme1737_init_device(dev); 2700 if (err) { 2701 dev_err(dev, "Failed to initialize device.\n"); 2702 return err; 2703 } 2704 2705 /* Create sysfs files */ 2706 err = dme1737_create_files(dev); 2707 if (err) { 2708 dev_err(dev, "Failed to create sysfs files.\n"); 2709 return err; 2710 } 2711 2712 /* Register device */ 2713 data->hwmon_dev = hwmon_device_register(dev); 2714 if (IS_ERR(data->hwmon_dev)) { 2715 dev_err(dev, "Failed to register device.\n"); 2716 err = PTR_ERR(data->hwmon_dev); 2717 goto exit_remove_files; 2718 } 2719 2720 return 0; 2721 2722 exit_remove_files: 2723 dme1737_remove_files(dev); 2724 return err; 2725 } 2726 2727 static int dme1737_isa_remove(struct platform_device *pdev) 2728 { 2729 struct dme1737_data *data = platform_get_drvdata(pdev); 2730 2731 hwmon_device_unregister(data->hwmon_dev); 2732 dme1737_remove_files(&pdev->dev); 2733 2734 return 0; 2735 } 2736 2737 static struct platform_driver dme1737_isa_driver = { 2738 .driver = { 2739 .name = "dme1737", 2740 }, 2741 .probe = dme1737_isa_probe, 2742 .remove = dme1737_isa_remove, 2743 }; 2744 2745 /* --------------------------------------------------------------------- 2746 * Module initialization and cleanup 2747 * --------------------------------------------------------------------- */ 2748 2749 static int __init dme1737_init(void) 2750 { 2751 int err; 2752 unsigned short addr; 2753 2754 err = i2c_add_driver(&dme1737_i2c_driver); 2755 if (err) 2756 goto exit; 2757 2758 if (dme1737_isa_detect(0x2e, &addr) && 2759 dme1737_isa_detect(0x4e, &addr) && 2760 (!probe_all_addr || 2761 (dme1737_isa_detect(0x162e, &addr) && 2762 dme1737_isa_detect(0x164e, &addr)))) { 2763 /* Return 0 if we didn't find an ISA device */ 2764 return 0; 2765 } 2766 2767 err = platform_driver_register(&dme1737_isa_driver); 2768 if (err) 2769 goto exit_del_i2c_driver; 2770 2771 /* Sets global pdev as a side effect */ 2772 err = dme1737_isa_device_add(addr); 2773 if (err) 2774 goto exit_del_isa_driver; 2775 2776 return 0; 2777 2778 exit_del_isa_driver: 2779 platform_driver_unregister(&dme1737_isa_driver); 2780 exit_del_i2c_driver: 2781 i2c_del_driver(&dme1737_i2c_driver); 2782 exit: 2783 return err; 2784 } 2785 2786 static void __exit dme1737_exit(void) 2787 { 2788 if (pdev) { 2789 platform_device_unregister(pdev); 2790 platform_driver_unregister(&dme1737_isa_driver); 2791 } 2792 2793 i2c_del_driver(&dme1737_i2c_driver); 2794 } 2795 2796 MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>"); 2797 MODULE_DESCRIPTION("DME1737 sensors"); 2798 MODULE_LICENSE("GPL"); 2799 2800 module_init(dme1737_init); 2801 module_exit(dme1737_exit); 2802