1 /* 2 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x and 3 * SCH5027 Super-I/O chips integrated hardware monitoring features. 4 * Copyright (c) 2007, 2008 Juerg Haefliger <juergh@gmail.com> 5 * 6 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access 7 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus 8 * if a SCH311x chip is found. Both types of chips have very similar hardware 9 * monitoring capabilities but differ in the way they can be accessed. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/init.h> 28 #include <linux/slab.h> 29 #include <linux/jiffies.h> 30 #include <linux/i2c.h> 31 #include <linux/platform_device.h> 32 #include <linux/hwmon.h> 33 #include <linux/hwmon-sysfs.h> 34 #include <linux/hwmon-vid.h> 35 #include <linux/err.h> 36 #include <linux/mutex.h> 37 #include <asm/io.h> 38 39 /* ISA device, if found */ 40 static struct platform_device *pdev; 41 42 /* Module load parameters */ 43 static int force_start; 44 module_param(force_start, bool, 0); 45 MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs"); 46 47 static unsigned short force_id; 48 module_param(force_id, ushort, 0); 49 MODULE_PARM_DESC(force_id, "Override the detected device ID"); 50 51 static int probe_all_addr; 52 module_param(probe_all_addr, bool, 0); 53 MODULE_PARM_DESC(probe_all_addr, "Include probing of non-standard LPC " 54 "addresses"); 55 56 /* Addresses to scan */ 57 static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END}; 58 59 /* Insmod parameters */ 60 I2C_CLIENT_INSMOD_2(dme1737, sch5027); 61 62 /* ISA chip types */ 63 enum isa_chips { sch311x = sch5027 + 1 }; 64 65 /* --------------------------------------------------------------------- 66 * Registers 67 * 68 * The sensors are defined as follows: 69 * 70 * Voltages Temperatures 71 * -------- ------------ 72 * in0 +5VTR (+5V stdby) temp1 Remote diode 1 73 * in1 Vccp (proc core) temp2 Internal temp 74 * in2 VCC (internal +3.3V) temp3 Remote diode 2 75 * in3 +5V 76 * in4 +12V 77 * in5 VTR (+3.3V stby) 78 * in6 Vbat 79 * 80 * --------------------------------------------------------------------- */ 81 82 /* Voltages (in) numbered 0-6 (ix) */ 83 #define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) \ 84 : 0x94 + (ix)) 85 #define DME1737_REG_IN_MIN(ix) ((ix) < 5 ? 0x44 + (ix) * 2 \ 86 : 0x91 + (ix) * 2) 87 #define DME1737_REG_IN_MAX(ix) ((ix) < 5 ? 0x45 + (ix) * 2 \ 88 : 0x92 + (ix) * 2) 89 90 /* Temperatures (temp) numbered 0-2 (ix) */ 91 #define DME1737_REG_TEMP(ix) (0x25 + (ix)) 92 #define DME1737_REG_TEMP_MIN(ix) (0x4e + (ix) * 2) 93 #define DME1737_REG_TEMP_MAX(ix) (0x4f + (ix) * 2) 94 #define DME1737_REG_TEMP_OFFSET(ix) ((ix) == 0 ? 0x1f \ 95 : 0x1c + (ix)) 96 97 /* Voltage and temperature LSBs 98 * The LSBs (4 bits each) are stored in 5 registers with the following layouts: 99 * IN_TEMP_LSB(0) = [in5, in6] 100 * IN_TEMP_LSB(1) = [temp3, temp1] 101 * IN_TEMP_LSB(2) = [in4, temp2] 102 * IN_TEMP_LSB(3) = [in3, in0] 103 * IN_TEMP_LSB(4) = [in2, in1] */ 104 #define DME1737_REG_IN_TEMP_LSB(ix) (0x84 + (ix)) 105 static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0}; 106 static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4}; 107 static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1}; 108 static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0}; 109 110 /* Fans numbered 0-5 (ix) */ 111 #define DME1737_REG_FAN(ix) ((ix) < 4 ? 0x28 + (ix) * 2 \ 112 : 0xa1 + (ix) * 2) 113 #define DME1737_REG_FAN_MIN(ix) ((ix) < 4 ? 0x54 + (ix) * 2 \ 114 : 0xa5 + (ix) * 2) 115 #define DME1737_REG_FAN_OPT(ix) ((ix) < 4 ? 0x90 + (ix) \ 116 : 0xb2 + (ix)) 117 #define DME1737_REG_FAN_MAX(ix) (0xb4 + (ix)) /* only for fan[4-5] */ 118 119 /* PWMs numbered 0-2, 4-5 (ix) */ 120 #define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \ 121 : 0xa1 + (ix)) 122 #define DME1737_REG_PWM_CONFIG(ix) (0x5c + (ix)) /* only for pwm[0-2] */ 123 #define DME1737_REG_PWM_MIN(ix) (0x64 + (ix)) /* only for pwm[0-2] */ 124 #define DME1737_REG_PWM_FREQ(ix) ((ix) < 3 ? 0x5f + (ix) \ 125 : 0xa3 + (ix)) 126 /* The layout of the ramp rate registers is different from the other pwm 127 * registers. The bits for the 3 PWMs are stored in 2 registers: 128 * PWM_RR(0) = [OFF3, OFF2, OFF1, RES, RR1E, RR1-2, RR1-1, RR1-0] 129 * PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0] */ 130 #define DME1737_REG_PWM_RR(ix) (0x62 + (ix)) /* only for pwm[0-2] */ 131 132 /* Thermal zones 0-2 */ 133 #define DME1737_REG_ZONE_LOW(ix) (0x67 + (ix)) 134 #define DME1737_REG_ZONE_ABS(ix) (0x6a + (ix)) 135 /* The layout of the hysteresis registers is different from the other zone 136 * registers. The bits for the 3 zones are stored in 2 registers: 137 * ZONE_HYST(0) = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0] 138 * ZONE_HYST(1) = [H3-3, H3-2, H3-1, H3-0, RES, RES, RES, RES] */ 139 #define DME1737_REG_ZONE_HYST(ix) (0x6d + (ix)) 140 141 /* Alarm registers and bit mapping 142 * The 3 8-bit alarm registers will be concatenated to a single 32-bit 143 * alarm value [0, ALARM3, ALARM2, ALARM1]. */ 144 #define DME1737_REG_ALARM1 0x41 145 #define DME1737_REG_ALARM2 0x42 146 #define DME1737_REG_ALARM3 0x83 147 static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17}; 148 static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6}; 149 static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23}; 150 151 /* Miscellaneous registers */ 152 #define DME1737_REG_DEVICE 0x3d 153 #define DME1737_REG_COMPANY 0x3e 154 #define DME1737_REG_VERSTEP 0x3f 155 #define DME1737_REG_CONFIG 0x40 156 #define DME1737_REG_CONFIG2 0x7f 157 #define DME1737_REG_VID 0x43 158 #define DME1737_REG_TACH_PWM 0x81 159 160 /* --------------------------------------------------------------------- 161 * Misc defines 162 * --------------------------------------------------------------------- */ 163 164 /* Chip identification */ 165 #define DME1737_COMPANY_SMSC 0x5c 166 #define DME1737_VERSTEP 0x88 167 #define DME1737_VERSTEP_MASK 0xf8 168 #define SCH311X_DEVICE 0x8c 169 #define SCH5027_VERSTEP 0x69 170 171 /* Length of ISA address segment */ 172 #define DME1737_EXTENT 2 173 174 /* --------------------------------------------------------------------- 175 * Data structures and manipulation thereof 176 * --------------------------------------------------------------------- */ 177 178 /* For ISA chips, we abuse the i2c_client addr and name fields. We also use 179 the driver field to differentiate between I2C and ISA chips. */ 180 struct dme1737_data { 181 struct i2c_client client; 182 struct device *hwmon_dev; 183 184 struct mutex update_lock; 185 int valid; /* !=0 if following fields are valid */ 186 unsigned long last_update; /* in jiffies */ 187 unsigned long last_vbat; /* in jiffies */ 188 enum chips type; 189 const int *in_nominal; /* pointer to IN_NOMINAL array */ 190 191 u8 vid; 192 u8 pwm_rr_en; 193 u8 has_pwm; 194 u8 has_fan; 195 196 /* Register values */ 197 u16 in[7]; 198 u8 in_min[7]; 199 u8 in_max[7]; 200 s16 temp[3]; 201 s8 temp_min[3]; 202 s8 temp_max[3]; 203 s8 temp_offset[3]; 204 u8 config; 205 u8 config2; 206 u8 vrm; 207 u16 fan[6]; 208 u16 fan_min[6]; 209 u8 fan_max[2]; 210 u8 fan_opt[6]; 211 u8 pwm[6]; 212 u8 pwm_min[3]; 213 u8 pwm_config[3]; 214 u8 pwm_acz[3]; 215 u8 pwm_freq[6]; 216 u8 pwm_rr[2]; 217 u8 zone_low[3]; 218 u8 zone_abs[3]; 219 u8 zone_hyst[2]; 220 u32 alarms; 221 }; 222 223 /* Nominal voltage values */ 224 static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300, 225 3300}; 226 static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300, 227 3300}; 228 static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300, 229 3300}; 230 #define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \ 231 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \ 232 IN_NOMINAL_DME1737) 233 234 /* Voltage input 235 * Voltage inputs have 16 bits resolution, limit values have 8 bits 236 * resolution. */ 237 static inline int IN_FROM_REG(int reg, int nominal, int res) 238 { 239 return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2)); 240 } 241 242 static inline int IN_TO_REG(int val, int nominal) 243 { 244 return SENSORS_LIMIT((val * 192 + nominal / 2) / nominal, 0, 255); 245 } 246 247 /* Temperature input 248 * The register values represent temperatures in 2's complement notation from 249 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit 250 * values have 8 bits resolution. */ 251 static inline int TEMP_FROM_REG(int reg, int res) 252 { 253 return (reg * 1000) >> (res - 8); 254 } 255 256 static inline int TEMP_TO_REG(int val) 257 { 258 return SENSORS_LIMIT((val < 0 ? val - 500 : val + 500) / 1000, 259 -128, 127); 260 } 261 262 /* Temperature range */ 263 static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000, 264 10000, 13333, 16000, 20000, 26666, 32000, 265 40000, 53333, 80000}; 266 267 static inline int TEMP_RANGE_FROM_REG(int reg) 268 { 269 return TEMP_RANGE[(reg >> 4) & 0x0f]; 270 } 271 272 static int TEMP_RANGE_TO_REG(int val, int reg) 273 { 274 int i; 275 276 for (i = 15; i > 0; i--) { 277 if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2) { 278 break; 279 } 280 } 281 282 return (reg & 0x0f) | (i << 4); 283 } 284 285 /* Temperature hysteresis 286 * Register layout: 287 * reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0] 288 * reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx] */ 289 static inline int TEMP_HYST_FROM_REG(int reg, int ix) 290 { 291 return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000; 292 } 293 294 static inline int TEMP_HYST_TO_REG(int val, int ix, int reg) 295 { 296 int hyst = SENSORS_LIMIT((val + 500) / 1000, 0, 15); 297 298 return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4); 299 } 300 301 /* Fan input RPM */ 302 static inline int FAN_FROM_REG(int reg, int tpc) 303 { 304 if (tpc) { 305 return tpc * reg; 306 } else { 307 return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg; 308 } 309 } 310 311 static inline int FAN_TO_REG(int val, int tpc) 312 { 313 if (tpc) { 314 return SENSORS_LIMIT(val / tpc, 0, 0xffff); 315 } else { 316 return (val <= 0) ? 0xffff : 317 SENSORS_LIMIT(90000 * 60 / val, 0, 0xfffe); 318 } 319 } 320 321 /* Fan TPC (tach pulse count) 322 * Converts a register value to a TPC multiplier or returns 0 if the tachometer 323 * is configured in legacy (non-tpc) mode */ 324 static inline int FAN_TPC_FROM_REG(int reg) 325 { 326 return (reg & 0x20) ? 0 : 60 >> (reg & 0x03); 327 } 328 329 /* Fan type 330 * The type of a fan is expressed in number of pulses-per-revolution that it 331 * emits */ 332 static inline int FAN_TYPE_FROM_REG(int reg) 333 { 334 int edge = (reg >> 1) & 0x03; 335 336 return (edge > 0) ? 1 << (edge - 1) : 0; 337 } 338 339 static inline int FAN_TYPE_TO_REG(int val, int reg) 340 { 341 int edge = (val == 4) ? 3 : val; 342 343 return (reg & 0xf9) | (edge << 1); 344 } 345 346 /* Fan max RPM */ 347 static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12, 348 0x11, 0x0f, 0x0e}; 349 350 static int FAN_MAX_FROM_REG(int reg) 351 { 352 int i; 353 354 for (i = 10; i > 0; i--) { 355 if (reg == FAN_MAX[i]) { 356 break; 357 } 358 } 359 360 return 1000 + i * 500; 361 } 362 363 static int FAN_MAX_TO_REG(int val) 364 { 365 int i; 366 367 for (i = 10; i > 0; i--) { 368 if (val > (1000 + (i - 1) * 500)) { 369 break; 370 } 371 } 372 373 return FAN_MAX[i]; 374 } 375 376 /* PWM enable 377 * Register to enable mapping: 378 * 000: 2 fan on zone 1 auto 379 * 001: 2 fan on zone 2 auto 380 * 010: 2 fan on zone 3 auto 381 * 011: 0 fan full on 382 * 100: -1 fan disabled 383 * 101: 2 fan on hottest of zones 2,3 auto 384 * 110: 2 fan on hottest of zones 1,2,3 auto 385 * 111: 1 fan in manual mode */ 386 static inline int PWM_EN_FROM_REG(int reg) 387 { 388 static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1}; 389 390 return en[(reg >> 5) & 0x07]; 391 } 392 393 static inline int PWM_EN_TO_REG(int val, int reg) 394 { 395 int en = (val == 1) ? 7 : 3; 396 397 return (reg & 0x1f) | ((en & 0x07) << 5); 398 } 399 400 /* PWM auto channels zone 401 * Register to auto channels zone mapping (ACZ is a bitfield with bit x 402 * corresponding to zone x+1): 403 * 000: 001 fan on zone 1 auto 404 * 001: 010 fan on zone 2 auto 405 * 010: 100 fan on zone 3 auto 406 * 011: 000 fan full on 407 * 100: 000 fan disabled 408 * 101: 110 fan on hottest of zones 2,3 auto 409 * 110: 111 fan on hottest of zones 1,2,3 auto 410 * 111: 000 fan in manual mode */ 411 static inline int PWM_ACZ_FROM_REG(int reg) 412 { 413 static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0}; 414 415 return acz[(reg >> 5) & 0x07]; 416 } 417 418 static inline int PWM_ACZ_TO_REG(int val, int reg) 419 { 420 int acz = (val == 4) ? 2 : val - 1; 421 422 return (reg & 0x1f) | ((acz & 0x07) << 5); 423 } 424 425 /* PWM frequency */ 426 static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88, 427 15000, 20000, 30000, 25000, 0, 0, 0, 0}; 428 429 static inline int PWM_FREQ_FROM_REG(int reg) 430 { 431 return PWM_FREQ[reg & 0x0f]; 432 } 433 434 static int PWM_FREQ_TO_REG(int val, int reg) 435 { 436 int i; 437 438 /* the first two cases are special - stupid chip design! */ 439 if (val > 27500) { 440 i = 10; 441 } else if (val > 22500) { 442 i = 11; 443 } else { 444 for (i = 9; i > 0; i--) { 445 if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2) { 446 break; 447 } 448 } 449 } 450 451 return (reg & 0xf0) | i; 452 } 453 454 /* PWM ramp rate 455 * Register layout: 456 * reg[0] = [OFF3, OFF2, OFF1, RES, RR1-E, RR1-2, RR1-1, RR1-0] 457 * reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0] */ 458 static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5}; 459 460 static inline int PWM_RR_FROM_REG(int reg, int ix) 461 { 462 int rr = (ix == 1) ? reg >> 4 : reg; 463 464 return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0; 465 } 466 467 static int PWM_RR_TO_REG(int val, int ix, int reg) 468 { 469 int i; 470 471 for (i = 0; i < 7; i++) { 472 if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2) { 473 break; 474 } 475 } 476 477 return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i; 478 } 479 480 /* PWM ramp rate enable */ 481 static inline int PWM_RR_EN_FROM_REG(int reg, int ix) 482 { 483 return PWM_RR_FROM_REG(reg, ix) ? 1 : 0; 484 } 485 486 static inline int PWM_RR_EN_TO_REG(int val, int ix, int reg) 487 { 488 int en = (ix == 1) ? 0x80 : 0x08; 489 490 return val ? reg | en : reg & ~en; 491 } 492 493 /* PWM min/off 494 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for 495 * the register layout). */ 496 static inline int PWM_OFF_FROM_REG(int reg, int ix) 497 { 498 return (reg >> (ix + 5)) & 0x01; 499 } 500 501 static inline int PWM_OFF_TO_REG(int val, int ix, int reg) 502 { 503 return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5)); 504 } 505 506 /* --------------------------------------------------------------------- 507 * Device I/O access 508 * 509 * ISA access is performed through an index/data register pair and needs to 510 * be protected by a mutex during runtime (not required for initialization). 511 * We use data->update_lock for this and need to ensure that we acquire it 512 * before calling dme1737_read or dme1737_write. 513 * --------------------------------------------------------------------- */ 514 515 static u8 dme1737_read(struct i2c_client *client, u8 reg) 516 { 517 s32 val; 518 519 if (client->driver) { /* I2C device */ 520 val = i2c_smbus_read_byte_data(client, reg); 521 522 if (val < 0) { 523 dev_warn(&client->dev, "Read from register " 524 "0x%02x failed! Please report to the driver " 525 "maintainer.\n", reg); 526 } 527 } else { /* ISA device */ 528 outb(reg, client->addr); 529 val = inb(client->addr + 1); 530 } 531 532 return val; 533 } 534 535 static s32 dme1737_write(struct i2c_client *client, u8 reg, u8 val) 536 { 537 s32 res = 0; 538 539 if (client->driver) { /* I2C device */ 540 res = i2c_smbus_write_byte_data(client, reg, val); 541 542 if (res < 0) { 543 dev_warn(&client->dev, "Write to register " 544 "0x%02x failed! Please report to the driver " 545 "maintainer.\n", reg); 546 } 547 } else { /* ISA device */ 548 outb(reg, client->addr); 549 outb(val, client->addr + 1); 550 } 551 552 return res; 553 } 554 555 static struct dme1737_data *dme1737_update_device(struct device *dev) 556 { 557 struct dme1737_data *data = dev_get_drvdata(dev); 558 struct i2c_client *client = &data->client; 559 int ix; 560 u8 lsb[5]; 561 562 mutex_lock(&data->update_lock); 563 564 /* Enable a Vbat monitoring cycle every 10 mins */ 565 if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) { 566 dme1737_write(client, DME1737_REG_CONFIG, dme1737_read(client, 567 DME1737_REG_CONFIG) | 0x10); 568 data->last_vbat = jiffies; 569 } 570 571 /* Sample register contents every 1 sec */ 572 if (time_after(jiffies, data->last_update + HZ) || !data->valid) { 573 if (data->type != sch5027) { 574 data->vid = dme1737_read(client, DME1737_REG_VID) & 575 0x3f; 576 } 577 578 /* In (voltage) registers */ 579 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { 580 /* Voltage inputs are stored as 16 bit values even 581 * though they have only 12 bits resolution. This is 582 * to make it consistent with the temp inputs. */ 583 data->in[ix] = dme1737_read(client, 584 DME1737_REG_IN(ix)) << 8; 585 data->in_min[ix] = dme1737_read(client, 586 DME1737_REG_IN_MIN(ix)); 587 data->in_max[ix] = dme1737_read(client, 588 DME1737_REG_IN_MAX(ix)); 589 } 590 591 /* Temp registers */ 592 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { 593 /* Temp inputs are stored as 16 bit values even 594 * though they have only 12 bits resolution. This is 595 * to take advantage of implicit conversions between 596 * register values (2's complement) and temp values 597 * (signed decimal). */ 598 data->temp[ix] = dme1737_read(client, 599 DME1737_REG_TEMP(ix)) << 8; 600 data->temp_min[ix] = dme1737_read(client, 601 DME1737_REG_TEMP_MIN(ix)); 602 data->temp_max[ix] = dme1737_read(client, 603 DME1737_REG_TEMP_MAX(ix)); 604 if (data->type != sch5027) { 605 data->temp_offset[ix] = dme1737_read(client, 606 DME1737_REG_TEMP_OFFSET(ix)); 607 } 608 } 609 610 /* In and temp LSB registers 611 * The LSBs are latched when the MSBs are read, so the order in 612 * which the registers are read (MSB first, then LSB) is 613 * important! */ 614 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) { 615 lsb[ix] = dme1737_read(client, 616 DME1737_REG_IN_TEMP_LSB(ix)); 617 } 618 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { 619 data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] << 620 DME1737_REG_IN_LSB_SHL[ix]) & 0xf0; 621 } 622 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { 623 data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] << 624 DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0; 625 } 626 627 /* Fan registers */ 628 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) { 629 /* Skip reading registers if optional fans are not 630 * present */ 631 if (!(data->has_fan & (1 << ix))) { 632 continue; 633 } 634 data->fan[ix] = dme1737_read(client, 635 DME1737_REG_FAN(ix)); 636 data->fan[ix] |= dme1737_read(client, 637 DME1737_REG_FAN(ix) + 1) << 8; 638 data->fan_min[ix] = dme1737_read(client, 639 DME1737_REG_FAN_MIN(ix)); 640 data->fan_min[ix] |= dme1737_read(client, 641 DME1737_REG_FAN_MIN(ix) + 1) << 8; 642 data->fan_opt[ix] = dme1737_read(client, 643 DME1737_REG_FAN_OPT(ix)); 644 /* fan_max exists only for fan[5-6] */ 645 if (ix > 3) { 646 data->fan_max[ix - 4] = dme1737_read(client, 647 DME1737_REG_FAN_MAX(ix)); 648 } 649 } 650 651 /* PWM registers */ 652 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) { 653 /* Skip reading registers if optional PWMs are not 654 * present */ 655 if (!(data->has_pwm & (1 << ix))) { 656 continue; 657 } 658 data->pwm[ix] = dme1737_read(client, 659 DME1737_REG_PWM(ix)); 660 data->pwm_freq[ix] = dme1737_read(client, 661 DME1737_REG_PWM_FREQ(ix)); 662 /* pwm_config and pwm_min exist only for pwm[1-3] */ 663 if (ix < 3) { 664 data->pwm_config[ix] = dme1737_read(client, 665 DME1737_REG_PWM_CONFIG(ix)); 666 data->pwm_min[ix] = dme1737_read(client, 667 DME1737_REG_PWM_MIN(ix)); 668 } 669 } 670 for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) { 671 data->pwm_rr[ix] = dme1737_read(client, 672 DME1737_REG_PWM_RR(ix)); 673 } 674 675 /* Thermal zone registers */ 676 for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) { 677 data->zone_low[ix] = dme1737_read(client, 678 DME1737_REG_ZONE_LOW(ix)); 679 data->zone_abs[ix] = dme1737_read(client, 680 DME1737_REG_ZONE_ABS(ix)); 681 } 682 if (data->type != sch5027) { 683 for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) { 684 data->zone_hyst[ix] = dme1737_read(client, 685 DME1737_REG_ZONE_HYST(ix)); 686 } 687 } 688 689 /* Alarm registers */ 690 data->alarms = dme1737_read(client, 691 DME1737_REG_ALARM1); 692 /* Bit 7 tells us if the other alarm registers are non-zero and 693 * therefore also need to be read */ 694 if (data->alarms & 0x80) { 695 data->alarms |= dme1737_read(client, 696 DME1737_REG_ALARM2) << 8; 697 data->alarms |= dme1737_read(client, 698 DME1737_REG_ALARM3) << 16; 699 } 700 701 /* The ISA chips require explicit clearing of alarm bits. 702 * Don't worry, an alarm will come back if the condition 703 * that causes it still exists */ 704 if (!client->driver) { 705 if (data->alarms & 0xff0000) { 706 dme1737_write(client, DME1737_REG_ALARM3, 707 0xff); 708 } 709 if (data->alarms & 0xff00) { 710 dme1737_write(client, DME1737_REG_ALARM2, 711 0xff); 712 } 713 if (data->alarms & 0xff) { 714 dme1737_write(client, DME1737_REG_ALARM1, 715 0xff); 716 } 717 } 718 719 data->last_update = jiffies; 720 data->valid = 1; 721 } 722 723 mutex_unlock(&data->update_lock); 724 725 return data; 726 } 727 728 /* --------------------------------------------------------------------- 729 * Voltage sysfs attributes 730 * ix = [0-5] 731 * --------------------------------------------------------------------- */ 732 733 #define SYS_IN_INPUT 0 734 #define SYS_IN_MIN 1 735 #define SYS_IN_MAX 2 736 #define SYS_IN_ALARM 3 737 738 static ssize_t show_in(struct device *dev, struct device_attribute *attr, 739 char *buf) 740 { 741 struct dme1737_data *data = dme1737_update_device(dev); 742 struct sensor_device_attribute_2 743 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 744 int ix = sensor_attr_2->index; 745 int fn = sensor_attr_2->nr; 746 int res; 747 748 switch (fn) { 749 case SYS_IN_INPUT: 750 res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16); 751 break; 752 case SYS_IN_MIN: 753 res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8); 754 break; 755 case SYS_IN_MAX: 756 res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8); 757 break; 758 case SYS_IN_ALARM: 759 res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01; 760 break; 761 default: 762 res = 0; 763 dev_dbg(dev, "Unknown function %d.\n", fn); 764 } 765 766 return sprintf(buf, "%d\n", res); 767 } 768 769 static ssize_t set_in(struct device *dev, struct device_attribute *attr, 770 const char *buf, size_t count) 771 { 772 struct dme1737_data *data = dev_get_drvdata(dev); 773 struct i2c_client *client = &data->client; 774 struct sensor_device_attribute_2 775 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 776 int ix = sensor_attr_2->index; 777 int fn = sensor_attr_2->nr; 778 long val = simple_strtol(buf, NULL, 10); 779 780 mutex_lock(&data->update_lock); 781 switch (fn) { 782 case SYS_IN_MIN: 783 data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]); 784 dme1737_write(client, DME1737_REG_IN_MIN(ix), 785 data->in_min[ix]); 786 break; 787 case SYS_IN_MAX: 788 data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]); 789 dme1737_write(client, DME1737_REG_IN_MAX(ix), 790 data->in_max[ix]); 791 break; 792 default: 793 dev_dbg(dev, "Unknown function %d.\n", fn); 794 } 795 mutex_unlock(&data->update_lock); 796 797 return count; 798 } 799 800 /* --------------------------------------------------------------------- 801 * Temperature sysfs attributes 802 * ix = [0-2] 803 * --------------------------------------------------------------------- */ 804 805 #define SYS_TEMP_INPUT 0 806 #define SYS_TEMP_MIN 1 807 #define SYS_TEMP_MAX 2 808 #define SYS_TEMP_OFFSET 3 809 #define SYS_TEMP_ALARM 4 810 #define SYS_TEMP_FAULT 5 811 812 static ssize_t show_temp(struct device *dev, struct device_attribute *attr, 813 char *buf) 814 { 815 struct dme1737_data *data = dme1737_update_device(dev); 816 struct sensor_device_attribute_2 817 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 818 int ix = sensor_attr_2->index; 819 int fn = sensor_attr_2->nr; 820 int res; 821 822 switch (fn) { 823 case SYS_TEMP_INPUT: 824 res = TEMP_FROM_REG(data->temp[ix], 16); 825 break; 826 case SYS_TEMP_MIN: 827 res = TEMP_FROM_REG(data->temp_min[ix], 8); 828 break; 829 case SYS_TEMP_MAX: 830 res = TEMP_FROM_REG(data->temp_max[ix], 8); 831 break; 832 case SYS_TEMP_OFFSET: 833 res = TEMP_FROM_REG(data->temp_offset[ix], 8); 834 break; 835 case SYS_TEMP_ALARM: 836 res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01; 837 break; 838 case SYS_TEMP_FAULT: 839 res = (((u16)data->temp[ix] & 0xff00) == 0x8000); 840 break; 841 default: 842 res = 0; 843 dev_dbg(dev, "Unknown function %d.\n", fn); 844 } 845 846 return sprintf(buf, "%d\n", res); 847 } 848 849 static ssize_t set_temp(struct device *dev, struct device_attribute *attr, 850 const char *buf, size_t count) 851 { 852 struct dme1737_data *data = dev_get_drvdata(dev); 853 struct i2c_client *client = &data->client; 854 struct sensor_device_attribute_2 855 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 856 int ix = sensor_attr_2->index; 857 int fn = sensor_attr_2->nr; 858 long val = simple_strtol(buf, NULL, 10); 859 860 mutex_lock(&data->update_lock); 861 switch (fn) { 862 case SYS_TEMP_MIN: 863 data->temp_min[ix] = TEMP_TO_REG(val); 864 dme1737_write(client, DME1737_REG_TEMP_MIN(ix), 865 data->temp_min[ix]); 866 break; 867 case SYS_TEMP_MAX: 868 data->temp_max[ix] = TEMP_TO_REG(val); 869 dme1737_write(client, DME1737_REG_TEMP_MAX(ix), 870 data->temp_max[ix]); 871 break; 872 case SYS_TEMP_OFFSET: 873 data->temp_offset[ix] = TEMP_TO_REG(val); 874 dme1737_write(client, DME1737_REG_TEMP_OFFSET(ix), 875 data->temp_offset[ix]); 876 break; 877 default: 878 dev_dbg(dev, "Unknown function %d.\n", fn); 879 } 880 mutex_unlock(&data->update_lock); 881 882 return count; 883 } 884 885 /* --------------------------------------------------------------------- 886 * Zone sysfs attributes 887 * ix = [0-2] 888 * --------------------------------------------------------------------- */ 889 890 #define SYS_ZONE_AUTO_CHANNELS_TEMP 0 891 #define SYS_ZONE_AUTO_POINT1_TEMP_HYST 1 892 #define SYS_ZONE_AUTO_POINT1_TEMP 2 893 #define SYS_ZONE_AUTO_POINT2_TEMP 3 894 #define SYS_ZONE_AUTO_POINT3_TEMP 4 895 896 static ssize_t show_zone(struct device *dev, struct device_attribute *attr, 897 char *buf) 898 { 899 struct dme1737_data *data = dme1737_update_device(dev); 900 struct sensor_device_attribute_2 901 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 902 int ix = sensor_attr_2->index; 903 int fn = sensor_attr_2->nr; 904 int res; 905 906 switch (fn) { 907 case SYS_ZONE_AUTO_CHANNELS_TEMP: 908 /* check config2 for non-standard temp-to-zone mapping */ 909 if ((ix == 1) && (data->config2 & 0x02)) { 910 res = 4; 911 } else { 912 res = 1 << ix; 913 } 914 break; 915 case SYS_ZONE_AUTO_POINT1_TEMP_HYST: 916 res = TEMP_FROM_REG(data->zone_low[ix], 8) - 917 TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix); 918 break; 919 case SYS_ZONE_AUTO_POINT1_TEMP: 920 res = TEMP_FROM_REG(data->zone_low[ix], 8); 921 break; 922 case SYS_ZONE_AUTO_POINT2_TEMP: 923 /* pwm_freq holds the temp range bits in the upper nibble */ 924 res = TEMP_FROM_REG(data->zone_low[ix], 8) + 925 TEMP_RANGE_FROM_REG(data->pwm_freq[ix]); 926 break; 927 case SYS_ZONE_AUTO_POINT3_TEMP: 928 res = TEMP_FROM_REG(data->zone_abs[ix], 8); 929 break; 930 default: 931 res = 0; 932 dev_dbg(dev, "Unknown function %d.\n", fn); 933 } 934 935 return sprintf(buf, "%d\n", res); 936 } 937 938 static ssize_t set_zone(struct device *dev, struct device_attribute *attr, 939 const char *buf, size_t count) 940 { 941 struct dme1737_data *data = dev_get_drvdata(dev); 942 struct i2c_client *client = &data->client; 943 struct sensor_device_attribute_2 944 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 945 int ix = sensor_attr_2->index; 946 int fn = sensor_attr_2->nr; 947 long val = simple_strtol(buf, NULL, 10); 948 949 mutex_lock(&data->update_lock); 950 switch (fn) { 951 case SYS_ZONE_AUTO_POINT1_TEMP_HYST: 952 /* Refresh the cache */ 953 data->zone_low[ix] = dme1737_read(client, 954 DME1737_REG_ZONE_LOW(ix)); 955 /* Modify the temp hyst value */ 956 data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG( 957 TEMP_FROM_REG(data->zone_low[ix], 8) - 958 val, ix, dme1737_read(client, 959 DME1737_REG_ZONE_HYST(ix == 2))); 960 dme1737_write(client, DME1737_REG_ZONE_HYST(ix == 2), 961 data->zone_hyst[ix == 2]); 962 break; 963 case SYS_ZONE_AUTO_POINT1_TEMP: 964 data->zone_low[ix] = TEMP_TO_REG(val); 965 dme1737_write(client, DME1737_REG_ZONE_LOW(ix), 966 data->zone_low[ix]); 967 break; 968 case SYS_ZONE_AUTO_POINT2_TEMP: 969 /* Refresh the cache */ 970 data->zone_low[ix] = dme1737_read(client, 971 DME1737_REG_ZONE_LOW(ix)); 972 /* Modify the temp range value (which is stored in the upper 973 * nibble of the pwm_freq register) */ 974 data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val - 975 TEMP_FROM_REG(data->zone_low[ix], 8), 976 dme1737_read(client, 977 DME1737_REG_PWM_FREQ(ix))); 978 dme1737_write(client, DME1737_REG_PWM_FREQ(ix), 979 data->pwm_freq[ix]); 980 break; 981 case SYS_ZONE_AUTO_POINT3_TEMP: 982 data->zone_abs[ix] = TEMP_TO_REG(val); 983 dme1737_write(client, DME1737_REG_ZONE_ABS(ix), 984 data->zone_abs[ix]); 985 break; 986 default: 987 dev_dbg(dev, "Unknown function %d.\n", fn); 988 } 989 mutex_unlock(&data->update_lock); 990 991 return count; 992 } 993 994 /* --------------------------------------------------------------------- 995 * Fan sysfs attributes 996 * ix = [0-5] 997 * --------------------------------------------------------------------- */ 998 999 #define SYS_FAN_INPUT 0 1000 #define SYS_FAN_MIN 1 1001 #define SYS_FAN_MAX 2 1002 #define SYS_FAN_ALARM 3 1003 #define SYS_FAN_TYPE 4 1004 1005 static ssize_t show_fan(struct device *dev, struct device_attribute *attr, 1006 char *buf) 1007 { 1008 struct dme1737_data *data = dme1737_update_device(dev); 1009 struct sensor_device_attribute_2 1010 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1011 int ix = sensor_attr_2->index; 1012 int fn = sensor_attr_2->nr; 1013 int res; 1014 1015 switch (fn) { 1016 case SYS_FAN_INPUT: 1017 res = FAN_FROM_REG(data->fan[ix], 1018 ix < 4 ? 0 : 1019 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1020 break; 1021 case SYS_FAN_MIN: 1022 res = FAN_FROM_REG(data->fan_min[ix], 1023 ix < 4 ? 0 : 1024 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1025 break; 1026 case SYS_FAN_MAX: 1027 /* only valid for fan[5-6] */ 1028 res = FAN_MAX_FROM_REG(data->fan_max[ix - 4]); 1029 break; 1030 case SYS_FAN_ALARM: 1031 res = (data->alarms >> DME1737_BIT_ALARM_FAN[ix]) & 0x01; 1032 break; 1033 case SYS_FAN_TYPE: 1034 /* only valid for fan[1-4] */ 1035 res = FAN_TYPE_FROM_REG(data->fan_opt[ix]); 1036 break; 1037 default: 1038 res = 0; 1039 dev_dbg(dev, "Unknown function %d.\n", fn); 1040 } 1041 1042 return sprintf(buf, "%d\n", res); 1043 } 1044 1045 static ssize_t set_fan(struct device *dev, struct device_attribute *attr, 1046 const char *buf, size_t count) 1047 { 1048 struct dme1737_data *data = dev_get_drvdata(dev); 1049 struct i2c_client *client = &data->client; 1050 struct sensor_device_attribute_2 1051 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1052 int ix = sensor_attr_2->index; 1053 int fn = sensor_attr_2->nr; 1054 long val = simple_strtol(buf, NULL, 10); 1055 1056 mutex_lock(&data->update_lock); 1057 switch (fn) { 1058 case SYS_FAN_MIN: 1059 if (ix < 4) { 1060 data->fan_min[ix] = FAN_TO_REG(val, 0); 1061 } else { 1062 /* Refresh the cache */ 1063 data->fan_opt[ix] = dme1737_read(client, 1064 DME1737_REG_FAN_OPT(ix)); 1065 /* Modify the fan min value */ 1066 data->fan_min[ix] = FAN_TO_REG(val, 1067 FAN_TPC_FROM_REG(data->fan_opt[ix])); 1068 } 1069 dme1737_write(client, DME1737_REG_FAN_MIN(ix), 1070 data->fan_min[ix] & 0xff); 1071 dme1737_write(client, DME1737_REG_FAN_MIN(ix) + 1, 1072 data->fan_min[ix] >> 8); 1073 break; 1074 case SYS_FAN_MAX: 1075 /* Only valid for fan[5-6] */ 1076 data->fan_max[ix - 4] = FAN_MAX_TO_REG(val); 1077 dme1737_write(client, DME1737_REG_FAN_MAX(ix), 1078 data->fan_max[ix - 4]); 1079 break; 1080 case SYS_FAN_TYPE: 1081 /* Only valid for fan[1-4] */ 1082 if (!(val == 1 || val == 2 || val == 4)) { 1083 count = -EINVAL; 1084 dev_warn(dev, "Fan type value %ld not " 1085 "supported. Choose one of 1, 2, or 4.\n", 1086 val); 1087 goto exit; 1088 } 1089 data->fan_opt[ix] = FAN_TYPE_TO_REG(val, dme1737_read(client, 1090 DME1737_REG_FAN_OPT(ix))); 1091 dme1737_write(client, DME1737_REG_FAN_OPT(ix), 1092 data->fan_opt[ix]); 1093 break; 1094 default: 1095 dev_dbg(dev, "Unknown function %d.\n", fn); 1096 } 1097 exit: 1098 mutex_unlock(&data->update_lock); 1099 1100 return count; 1101 } 1102 1103 /* --------------------------------------------------------------------- 1104 * PWM sysfs attributes 1105 * ix = [0-4] 1106 * --------------------------------------------------------------------- */ 1107 1108 #define SYS_PWM 0 1109 #define SYS_PWM_FREQ 1 1110 #define SYS_PWM_ENABLE 2 1111 #define SYS_PWM_RAMP_RATE 3 1112 #define SYS_PWM_AUTO_CHANNELS_ZONE 4 1113 #define SYS_PWM_AUTO_PWM_MIN 5 1114 #define SYS_PWM_AUTO_POINT1_PWM 6 1115 #define SYS_PWM_AUTO_POINT2_PWM 7 1116 1117 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, 1118 char *buf) 1119 { 1120 struct dme1737_data *data = dme1737_update_device(dev); 1121 struct sensor_device_attribute_2 1122 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1123 int ix = sensor_attr_2->index; 1124 int fn = sensor_attr_2->nr; 1125 int res; 1126 1127 switch (fn) { 1128 case SYS_PWM: 1129 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 0) { 1130 res = 255; 1131 } else { 1132 res = data->pwm[ix]; 1133 } 1134 break; 1135 case SYS_PWM_FREQ: 1136 res = PWM_FREQ_FROM_REG(data->pwm_freq[ix]); 1137 break; 1138 case SYS_PWM_ENABLE: 1139 if (ix > 3) { 1140 res = 1; /* pwm[5-6] hard-wired to manual mode */ 1141 } else { 1142 res = PWM_EN_FROM_REG(data->pwm_config[ix]); 1143 } 1144 break; 1145 case SYS_PWM_RAMP_RATE: 1146 /* Only valid for pwm[1-3] */ 1147 res = PWM_RR_FROM_REG(data->pwm_rr[ix > 0], ix); 1148 break; 1149 case SYS_PWM_AUTO_CHANNELS_ZONE: 1150 /* Only valid for pwm[1-3] */ 1151 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1152 res = PWM_ACZ_FROM_REG(data->pwm_config[ix]); 1153 } else { 1154 res = data->pwm_acz[ix]; 1155 } 1156 break; 1157 case SYS_PWM_AUTO_PWM_MIN: 1158 /* Only valid for pwm[1-3] */ 1159 if (PWM_OFF_FROM_REG(data->pwm_rr[0], ix)) { 1160 res = data->pwm_min[ix]; 1161 } else { 1162 res = 0; 1163 } 1164 break; 1165 case SYS_PWM_AUTO_POINT1_PWM: 1166 /* Only valid for pwm[1-3] */ 1167 res = data->pwm_min[ix]; 1168 break; 1169 case SYS_PWM_AUTO_POINT2_PWM: 1170 /* Only valid for pwm[1-3] */ 1171 res = 255; /* hard-wired */ 1172 break; 1173 default: 1174 res = 0; 1175 dev_dbg(dev, "Unknown function %d.\n", fn); 1176 } 1177 1178 return sprintf(buf, "%d\n", res); 1179 } 1180 1181 static struct attribute *dme1737_pwm_chmod_attr[]; 1182 static void dme1737_chmod_file(struct device*, struct attribute*, mode_t); 1183 1184 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, 1185 const char *buf, size_t count) 1186 { 1187 struct dme1737_data *data = dev_get_drvdata(dev); 1188 struct i2c_client *client = &data->client; 1189 struct sensor_device_attribute_2 1190 *sensor_attr_2 = to_sensor_dev_attr_2(attr); 1191 int ix = sensor_attr_2->index; 1192 int fn = sensor_attr_2->nr; 1193 long val = simple_strtol(buf, NULL, 10); 1194 1195 mutex_lock(&data->update_lock); 1196 switch (fn) { 1197 case SYS_PWM: 1198 data->pwm[ix] = SENSORS_LIMIT(val, 0, 255); 1199 dme1737_write(client, DME1737_REG_PWM(ix), data->pwm[ix]); 1200 break; 1201 case SYS_PWM_FREQ: 1202 data->pwm_freq[ix] = PWM_FREQ_TO_REG(val, dme1737_read(client, 1203 DME1737_REG_PWM_FREQ(ix))); 1204 dme1737_write(client, DME1737_REG_PWM_FREQ(ix), 1205 data->pwm_freq[ix]); 1206 break; 1207 case SYS_PWM_ENABLE: 1208 /* Only valid for pwm[1-3] */ 1209 if (val < 0 || val > 2) { 1210 count = -EINVAL; 1211 dev_warn(dev, "PWM enable %ld not " 1212 "supported. Choose one of 0, 1, or 2.\n", 1213 val); 1214 goto exit; 1215 } 1216 /* Refresh the cache */ 1217 data->pwm_config[ix] = dme1737_read(client, 1218 DME1737_REG_PWM_CONFIG(ix)); 1219 if (val == PWM_EN_FROM_REG(data->pwm_config[ix])) { 1220 /* Bail out if no change */ 1221 goto exit; 1222 } 1223 /* Do some housekeeping if we are currently in auto mode */ 1224 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1225 /* Save the current zone channel assignment */ 1226 data->pwm_acz[ix] = PWM_ACZ_FROM_REG( 1227 data->pwm_config[ix]); 1228 /* Save the current ramp rate state and disable it */ 1229 data->pwm_rr[ix > 0] = dme1737_read(client, 1230 DME1737_REG_PWM_RR(ix > 0)); 1231 data->pwm_rr_en &= ~(1 << ix); 1232 if (PWM_RR_EN_FROM_REG(data->pwm_rr[ix > 0], ix)) { 1233 data->pwm_rr_en |= (1 << ix); 1234 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(0, ix, 1235 data->pwm_rr[ix > 0]); 1236 dme1737_write(client, 1237 DME1737_REG_PWM_RR(ix > 0), 1238 data->pwm_rr[ix > 0]); 1239 } 1240 } 1241 /* Set the new PWM mode */ 1242 switch (val) { 1243 case 0: 1244 /* Change permissions of pwm[ix] to read-only */ 1245 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1246 S_IRUGO); 1247 /* Turn fan fully on */ 1248 data->pwm_config[ix] = PWM_EN_TO_REG(0, 1249 data->pwm_config[ix]); 1250 dme1737_write(client, DME1737_REG_PWM_CONFIG(ix), 1251 data->pwm_config[ix]); 1252 break; 1253 case 1: 1254 /* Turn on manual mode */ 1255 data->pwm_config[ix] = PWM_EN_TO_REG(1, 1256 data->pwm_config[ix]); 1257 dme1737_write(client, DME1737_REG_PWM_CONFIG(ix), 1258 data->pwm_config[ix]); 1259 /* Change permissions of pwm[ix] to read-writeable */ 1260 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1261 S_IRUGO | S_IWUSR); 1262 break; 1263 case 2: 1264 /* Change permissions of pwm[ix] to read-only */ 1265 dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], 1266 S_IRUGO); 1267 /* Turn on auto mode using the saved zone channel 1268 * assignment */ 1269 data->pwm_config[ix] = PWM_ACZ_TO_REG( 1270 data->pwm_acz[ix], 1271 data->pwm_config[ix]); 1272 dme1737_write(client, DME1737_REG_PWM_CONFIG(ix), 1273 data->pwm_config[ix]); 1274 /* Enable PWM ramp rate if previously enabled */ 1275 if (data->pwm_rr_en & (1 << ix)) { 1276 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(1, ix, 1277 dme1737_read(client, 1278 DME1737_REG_PWM_RR(ix > 0))); 1279 dme1737_write(client, 1280 DME1737_REG_PWM_RR(ix > 0), 1281 data->pwm_rr[ix > 0]); 1282 } 1283 break; 1284 } 1285 break; 1286 case SYS_PWM_RAMP_RATE: 1287 /* Only valid for pwm[1-3] */ 1288 /* Refresh the cache */ 1289 data->pwm_config[ix] = dme1737_read(client, 1290 DME1737_REG_PWM_CONFIG(ix)); 1291 data->pwm_rr[ix > 0] = dme1737_read(client, 1292 DME1737_REG_PWM_RR(ix > 0)); 1293 /* Set the ramp rate value */ 1294 if (val > 0) { 1295 data->pwm_rr[ix > 0] = PWM_RR_TO_REG(val, ix, 1296 data->pwm_rr[ix > 0]); 1297 } 1298 /* Enable/disable the feature only if the associated PWM 1299 * output is in automatic mode. */ 1300 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1301 data->pwm_rr[ix > 0] = PWM_RR_EN_TO_REG(val > 0, ix, 1302 data->pwm_rr[ix > 0]); 1303 } 1304 dme1737_write(client, DME1737_REG_PWM_RR(ix > 0), 1305 data->pwm_rr[ix > 0]); 1306 break; 1307 case SYS_PWM_AUTO_CHANNELS_ZONE: 1308 /* Only valid for pwm[1-3] */ 1309 if (!(val == 1 || val == 2 || val == 4 || 1310 val == 6 || val == 7)) { 1311 count = -EINVAL; 1312 dev_warn(dev, "PWM auto channels zone %ld " 1313 "not supported. Choose one of 1, 2, 4, 6, " 1314 "or 7.\n", val); 1315 goto exit; 1316 } 1317 /* Refresh the cache */ 1318 data->pwm_config[ix] = dme1737_read(client, 1319 DME1737_REG_PWM_CONFIG(ix)); 1320 if (PWM_EN_FROM_REG(data->pwm_config[ix]) == 2) { 1321 /* PWM is already in auto mode so update the temp 1322 * channel assignment */ 1323 data->pwm_config[ix] = PWM_ACZ_TO_REG(val, 1324 data->pwm_config[ix]); 1325 dme1737_write(client, DME1737_REG_PWM_CONFIG(ix), 1326 data->pwm_config[ix]); 1327 } else { 1328 /* PWM is not in auto mode so we save the temp 1329 * channel assignment for later use */ 1330 data->pwm_acz[ix] = val; 1331 } 1332 break; 1333 case SYS_PWM_AUTO_PWM_MIN: 1334 /* Only valid for pwm[1-3] */ 1335 /* Refresh the cache */ 1336 data->pwm_min[ix] = dme1737_read(client, 1337 DME1737_REG_PWM_MIN(ix)); 1338 /* There are only 2 values supported for the auto_pwm_min 1339 * value: 0 or auto_point1_pwm. So if the temperature drops 1340 * below the auto_point1_temp_hyst value, the fan either turns 1341 * off or runs at auto_point1_pwm duty-cycle. */ 1342 if (val > ((data->pwm_min[ix] + 1) / 2)) { 1343 data->pwm_rr[0] = PWM_OFF_TO_REG(1, ix, 1344 dme1737_read(client, 1345 DME1737_REG_PWM_RR(0))); 1346 } else { 1347 data->pwm_rr[0] = PWM_OFF_TO_REG(0, ix, 1348 dme1737_read(client, 1349 DME1737_REG_PWM_RR(0))); 1350 } 1351 dme1737_write(client, DME1737_REG_PWM_RR(0), 1352 data->pwm_rr[0]); 1353 break; 1354 case SYS_PWM_AUTO_POINT1_PWM: 1355 /* Only valid for pwm[1-3] */ 1356 data->pwm_min[ix] = SENSORS_LIMIT(val, 0, 255); 1357 dme1737_write(client, DME1737_REG_PWM_MIN(ix), 1358 data->pwm_min[ix]); 1359 break; 1360 default: 1361 dev_dbg(dev, "Unknown function %d.\n", fn); 1362 } 1363 exit: 1364 mutex_unlock(&data->update_lock); 1365 1366 return count; 1367 } 1368 1369 /* --------------------------------------------------------------------- 1370 * Miscellaneous sysfs attributes 1371 * --------------------------------------------------------------------- */ 1372 1373 static ssize_t show_vrm(struct device *dev, struct device_attribute *attr, 1374 char *buf) 1375 { 1376 struct i2c_client *client = to_i2c_client(dev); 1377 struct dme1737_data *data = i2c_get_clientdata(client); 1378 1379 return sprintf(buf, "%d\n", data->vrm); 1380 } 1381 1382 static ssize_t set_vrm(struct device *dev, struct device_attribute *attr, 1383 const char *buf, size_t count) 1384 { 1385 struct dme1737_data *data = dev_get_drvdata(dev); 1386 long val = simple_strtol(buf, NULL, 10); 1387 1388 data->vrm = val; 1389 return count; 1390 } 1391 1392 static ssize_t show_vid(struct device *dev, struct device_attribute *attr, 1393 char *buf) 1394 { 1395 struct dme1737_data *data = dme1737_update_device(dev); 1396 1397 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm)); 1398 } 1399 1400 static ssize_t show_name(struct device *dev, struct device_attribute *attr, 1401 char *buf) 1402 { 1403 struct dme1737_data *data = dev_get_drvdata(dev); 1404 1405 return sprintf(buf, "%s\n", data->client.name); 1406 } 1407 1408 /* --------------------------------------------------------------------- 1409 * Sysfs device attribute defines and structs 1410 * --------------------------------------------------------------------- */ 1411 1412 /* Voltages 0-6 */ 1413 1414 #define SENSOR_DEVICE_ATTR_IN(ix) \ 1415 static SENSOR_DEVICE_ATTR_2(in##ix##_input, S_IRUGO, \ 1416 show_in, NULL, SYS_IN_INPUT, ix); \ 1417 static SENSOR_DEVICE_ATTR_2(in##ix##_min, S_IRUGO | S_IWUSR, \ 1418 show_in, set_in, SYS_IN_MIN, ix); \ 1419 static SENSOR_DEVICE_ATTR_2(in##ix##_max, S_IRUGO | S_IWUSR, \ 1420 show_in, set_in, SYS_IN_MAX, ix); \ 1421 static SENSOR_DEVICE_ATTR_2(in##ix##_alarm, S_IRUGO, \ 1422 show_in, NULL, SYS_IN_ALARM, ix) 1423 1424 SENSOR_DEVICE_ATTR_IN(0); 1425 SENSOR_DEVICE_ATTR_IN(1); 1426 SENSOR_DEVICE_ATTR_IN(2); 1427 SENSOR_DEVICE_ATTR_IN(3); 1428 SENSOR_DEVICE_ATTR_IN(4); 1429 SENSOR_DEVICE_ATTR_IN(5); 1430 SENSOR_DEVICE_ATTR_IN(6); 1431 1432 /* Temperatures 1-3 */ 1433 1434 #define SENSOR_DEVICE_ATTR_TEMP(ix) \ 1435 static SENSOR_DEVICE_ATTR_2(temp##ix##_input, S_IRUGO, \ 1436 show_temp, NULL, SYS_TEMP_INPUT, ix-1); \ 1437 static SENSOR_DEVICE_ATTR_2(temp##ix##_min, S_IRUGO | S_IWUSR, \ 1438 show_temp, set_temp, SYS_TEMP_MIN, ix-1); \ 1439 static SENSOR_DEVICE_ATTR_2(temp##ix##_max, S_IRUGO | S_IWUSR, \ 1440 show_temp, set_temp, SYS_TEMP_MAX, ix-1); \ 1441 static SENSOR_DEVICE_ATTR_2(temp##ix##_offset, S_IRUGO, \ 1442 show_temp, set_temp, SYS_TEMP_OFFSET, ix-1); \ 1443 static SENSOR_DEVICE_ATTR_2(temp##ix##_alarm, S_IRUGO, \ 1444 show_temp, NULL, SYS_TEMP_ALARM, ix-1); \ 1445 static SENSOR_DEVICE_ATTR_2(temp##ix##_fault, S_IRUGO, \ 1446 show_temp, NULL, SYS_TEMP_FAULT, ix-1) 1447 1448 SENSOR_DEVICE_ATTR_TEMP(1); 1449 SENSOR_DEVICE_ATTR_TEMP(2); 1450 SENSOR_DEVICE_ATTR_TEMP(3); 1451 1452 /* Zones 1-3 */ 1453 1454 #define SENSOR_DEVICE_ATTR_ZONE(ix) \ 1455 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_channels_temp, S_IRUGO, \ 1456 show_zone, NULL, SYS_ZONE_AUTO_CHANNELS_TEMP, ix-1); \ 1457 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp_hyst, S_IRUGO, \ 1458 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP_HYST, ix-1); \ 1459 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point1_temp, S_IRUGO, \ 1460 show_zone, set_zone, SYS_ZONE_AUTO_POINT1_TEMP, ix-1); \ 1461 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point2_temp, S_IRUGO, \ 1462 show_zone, set_zone, SYS_ZONE_AUTO_POINT2_TEMP, ix-1); \ 1463 static SENSOR_DEVICE_ATTR_2(zone##ix##_auto_point3_temp, S_IRUGO, \ 1464 show_zone, set_zone, SYS_ZONE_AUTO_POINT3_TEMP, ix-1) 1465 1466 SENSOR_DEVICE_ATTR_ZONE(1); 1467 SENSOR_DEVICE_ATTR_ZONE(2); 1468 SENSOR_DEVICE_ATTR_ZONE(3); 1469 1470 /* Fans 1-4 */ 1471 1472 #define SENSOR_DEVICE_ATTR_FAN_1TO4(ix) \ 1473 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \ 1474 show_fan, NULL, SYS_FAN_INPUT, ix-1); \ 1475 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \ 1476 show_fan, set_fan, SYS_FAN_MIN, ix-1); \ 1477 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \ 1478 show_fan, NULL, SYS_FAN_ALARM, ix-1); \ 1479 static SENSOR_DEVICE_ATTR_2(fan##ix##_type, S_IRUGO | S_IWUSR, \ 1480 show_fan, set_fan, SYS_FAN_TYPE, ix-1) 1481 1482 SENSOR_DEVICE_ATTR_FAN_1TO4(1); 1483 SENSOR_DEVICE_ATTR_FAN_1TO4(2); 1484 SENSOR_DEVICE_ATTR_FAN_1TO4(3); 1485 SENSOR_DEVICE_ATTR_FAN_1TO4(4); 1486 1487 /* Fans 5-6 */ 1488 1489 #define SENSOR_DEVICE_ATTR_FAN_5TO6(ix) \ 1490 static SENSOR_DEVICE_ATTR_2(fan##ix##_input, S_IRUGO, \ 1491 show_fan, NULL, SYS_FAN_INPUT, ix-1); \ 1492 static SENSOR_DEVICE_ATTR_2(fan##ix##_min, S_IRUGO | S_IWUSR, \ 1493 show_fan, set_fan, SYS_FAN_MIN, ix-1); \ 1494 static SENSOR_DEVICE_ATTR_2(fan##ix##_alarm, S_IRUGO, \ 1495 show_fan, NULL, SYS_FAN_ALARM, ix-1); \ 1496 static SENSOR_DEVICE_ATTR_2(fan##ix##_max, S_IRUGO | S_IWUSR, \ 1497 show_fan, set_fan, SYS_FAN_MAX, ix-1) 1498 1499 SENSOR_DEVICE_ATTR_FAN_5TO6(5); 1500 SENSOR_DEVICE_ATTR_FAN_5TO6(6); 1501 1502 /* PWMs 1-3 */ 1503 1504 #define SENSOR_DEVICE_ATTR_PWM_1TO3(ix) \ 1505 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \ 1506 show_pwm, set_pwm, SYS_PWM, ix-1); \ 1507 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \ 1508 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \ 1509 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \ 1510 show_pwm, set_pwm, SYS_PWM_ENABLE, ix-1); \ 1511 static SENSOR_DEVICE_ATTR_2(pwm##ix##_ramp_rate, S_IRUGO, \ 1512 show_pwm, set_pwm, SYS_PWM_RAMP_RATE, ix-1); \ 1513 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_channels_zone, S_IRUGO, \ 1514 show_pwm, set_pwm, SYS_PWM_AUTO_CHANNELS_ZONE, ix-1); \ 1515 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_pwm_min, S_IRUGO, \ 1516 show_pwm, set_pwm, SYS_PWM_AUTO_PWM_MIN, ix-1); \ 1517 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point1_pwm, S_IRUGO, \ 1518 show_pwm, set_pwm, SYS_PWM_AUTO_POINT1_PWM, ix-1); \ 1519 static SENSOR_DEVICE_ATTR_2(pwm##ix##_auto_point2_pwm, S_IRUGO, \ 1520 show_pwm, NULL, SYS_PWM_AUTO_POINT2_PWM, ix-1) 1521 1522 SENSOR_DEVICE_ATTR_PWM_1TO3(1); 1523 SENSOR_DEVICE_ATTR_PWM_1TO3(2); 1524 SENSOR_DEVICE_ATTR_PWM_1TO3(3); 1525 1526 /* PWMs 5-6 */ 1527 1528 #define SENSOR_DEVICE_ATTR_PWM_5TO6(ix) \ 1529 static SENSOR_DEVICE_ATTR_2(pwm##ix, S_IRUGO, \ 1530 show_pwm, set_pwm, SYS_PWM, ix-1); \ 1531 static SENSOR_DEVICE_ATTR_2(pwm##ix##_freq, S_IRUGO, \ 1532 show_pwm, set_pwm, SYS_PWM_FREQ, ix-1); \ 1533 static SENSOR_DEVICE_ATTR_2(pwm##ix##_enable, S_IRUGO, \ 1534 show_pwm, NULL, SYS_PWM_ENABLE, ix-1) 1535 1536 SENSOR_DEVICE_ATTR_PWM_5TO6(5); 1537 SENSOR_DEVICE_ATTR_PWM_5TO6(6); 1538 1539 /* Misc */ 1540 1541 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm, set_vrm); 1542 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL); 1543 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL); /* for ISA devices */ 1544 1545 /* This struct holds all the attributes that are always present and need to be 1546 * created unconditionally. The attributes that need modification of their 1547 * permissions are created read-only and write permissions are added or removed 1548 * on the fly when required */ 1549 static struct attribute *dme1737_attr[] ={ 1550 /* Voltages */ 1551 &sensor_dev_attr_in0_input.dev_attr.attr, 1552 &sensor_dev_attr_in0_min.dev_attr.attr, 1553 &sensor_dev_attr_in0_max.dev_attr.attr, 1554 &sensor_dev_attr_in0_alarm.dev_attr.attr, 1555 &sensor_dev_attr_in1_input.dev_attr.attr, 1556 &sensor_dev_attr_in1_min.dev_attr.attr, 1557 &sensor_dev_attr_in1_max.dev_attr.attr, 1558 &sensor_dev_attr_in1_alarm.dev_attr.attr, 1559 &sensor_dev_attr_in2_input.dev_attr.attr, 1560 &sensor_dev_attr_in2_min.dev_attr.attr, 1561 &sensor_dev_attr_in2_max.dev_attr.attr, 1562 &sensor_dev_attr_in2_alarm.dev_attr.attr, 1563 &sensor_dev_attr_in3_input.dev_attr.attr, 1564 &sensor_dev_attr_in3_min.dev_attr.attr, 1565 &sensor_dev_attr_in3_max.dev_attr.attr, 1566 &sensor_dev_attr_in3_alarm.dev_attr.attr, 1567 &sensor_dev_attr_in4_input.dev_attr.attr, 1568 &sensor_dev_attr_in4_min.dev_attr.attr, 1569 &sensor_dev_attr_in4_max.dev_attr.attr, 1570 &sensor_dev_attr_in4_alarm.dev_attr.attr, 1571 &sensor_dev_attr_in5_input.dev_attr.attr, 1572 &sensor_dev_attr_in5_min.dev_attr.attr, 1573 &sensor_dev_attr_in5_max.dev_attr.attr, 1574 &sensor_dev_attr_in5_alarm.dev_attr.attr, 1575 &sensor_dev_attr_in6_input.dev_attr.attr, 1576 &sensor_dev_attr_in6_min.dev_attr.attr, 1577 &sensor_dev_attr_in6_max.dev_attr.attr, 1578 &sensor_dev_attr_in6_alarm.dev_attr.attr, 1579 /* Temperatures */ 1580 &sensor_dev_attr_temp1_input.dev_attr.attr, 1581 &sensor_dev_attr_temp1_min.dev_attr.attr, 1582 &sensor_dev_attr_temp1_max.dev_attr.attr, 1583 &sensor_dev_attr_temp1_alarm.dev_attr.attr, 1584 &sensor_dev_attr_temp1_fault.dev_attr.attr, 1585 &sensor_dev_attr_temp2_input.dev_attr.attr, 1586 &sensor_dev_attr_temp2_min.dev_attr.attr, 1587 &sensor_dev_attr_temp2_max.dev_attr.attr, 1588 &sensor_dev_attr_temp2_alarm.dev_attr.attr, 1589 &sensor_dev_attr_temp2_fault.dev_attr.attr, 1590 &sensor_dev_attr_temp3_input.dev_attr.attr, 1591 &sensor_dev_attr_temp3_min.dev_attr.attr, 1592 &sensor_dev_attr_temp3_max.dev_attr.attr, 1593 &sensor_dev_attr_temp3_alarm.dev_attr.attr, 1594 &sensor_dev_attr_temp3_fault.dev_attr.attr, 1595 /* Zones */ 1596 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, 1597 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, 1598 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, 1599 &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr, 1600 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, 1601 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, 1602 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, 1603 &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr, 1604 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, 1605 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, 1606 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, 1607 &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr, 1608 NULL 1609 }; 1610 1611 static const struct attribute_group dme1737_group = { 1612 .attrs = dme1737_attr, 1613 }; 1614 1615 /* The following struct holds misc attributes, which are not available in all 1616 * chips. Their creation depends on the chip type which is determined during 1617 * module load. */ 1618 static struct attribute *dme1737_misc_attr[] = { 1619 /* Temperatures */ 1620 &sensor_dev_attr_temp1_offset.dev_attr.attr, 1621 &sensor_dev_attr_temp2_offset.dev_attr.attr, 1622 &sensor_dev_attr_temp3_offset.dev_attr.attr, 1623 /* Zones */ 1624 &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr, 1625 &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr, 1626 &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr, 1627 /* Misc */ 1628 &dev_attr_vrm.attr, 1629 &dev_attr_cpu0_vid.attr, 1630 NULL 1631 }; 1632 1633 static const struct attribute_group dme1737_misc_group = { 1634 .attrs = dme1737_misc_attr, 1635 }; 1636 1637 /* The following structs hold the PWM attributes, some of which are optional. 1638 * Their creation depends on the chip configuration which is determined during 1639 * module load. */ 1640 static struct attribute *dme1737_pwm1_attr[] = { 1641 &sensor_dev_attr_pwm1.dev_attr.attr, 1642 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 1643 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1644 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, 1645 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, 1646 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 1647 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, 1648 NULL 1649 }; 1650 static struct attribute *dme1737_pwm2_attr[] = { 1651 &sensor_dev_attr_pwm2.dev_attr.attr, 1652 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 1653 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 1654 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, 1655 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, 1656 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, 1657 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, 1658 NULL 1659 }; 1660 static struct attribute *dme1737_pwm3_attr[] = { 1661 &sensor_dev_attr_pwm3.dev_attr.attr, 1662 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 1663 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 1664 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, 1665 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, 1666 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, 1667 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, 1668 NULL 1669 }; 1670 static struct attribute *dme1737_pwm5_attr[] = { 1671 &sensor_dev_attr_pwm5.dev_attr.attr, 1672 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 1673 &sensor_dev_attr_pwm5_enable.dev_attr.attr, 1674 NULL 1675 }; 1676 static struct attribute *dme1737_pwm6_attr[] = { 1677 &sensor_dev_attr_pwm6.dev_attr.attr, 1678 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 1679 &sensor_dev_attr_pwm6_enable.dev_attr.attr, 1680 NULL 1681 }; 1682 1683 static const struct attribute_group dme1737_pwm_group[] = { 1684 { .attrs = dme1737_pwm1_attr }, 1685 { .attrs = dme1737_pwm2_attr }, 1686 { .attrs = dme1737_pwm3_attr }, 1687 { .attrs = NULL }, 1688 { .attrs = dme1737_pwm5_attr }, 1689 { .attrs = dme1737_pwm6_attr }, 1690 }; 1691 1692 /* The following struct holds misc PWM attributes, which are not available in 1693 * all chips. Their creation depends on the chip type which is determined 1694 * during module load. */ 1695 static struct attribute *dme1737_pwm_misc_attr[] = { 1696 &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr, 1697 &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr, 1698 &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr, 1699 }; 1700 1701 /* The following structs hold the fan attributes, some of which are optional. 1702 * Their creation depends on the chip configuration which is determined during 1703 * module load. */ 1704 static struct attribute *dme1737_fan1_attr[] = { 1705 &sensor_dev_attr_fan1_input.dev_attr.attr, 1706 &sensor_dev_attr_fan1_min.dev_attr.attr, 1707 &sensor_dev_attr_fan1_alarm.dev_attr.attr, 1708 &sensor_dev_attr_fan1_type.dev_attr.attr, 1709 NULL 1710 }; 1711 static struct attribute *dme1737_fan2_attr[] = { 1712 &sensor_dev_attr_fan2_input.dev_attr.attr, 1713 &sensor_dev_attr_fan2_min.dev_attr.attr, 1714 &sensor_dev_attr_fan2_alarm.dev_attr.attr, 1715 &sensor_dev_attr_fan2_type.dev_attr.attr, 1716 NULL 1717 }; 1718 static struct attribute *dme1737_fan3_attr[] = { 1719 &sensor_dev_attr_fan3_input.dev_attr.attr, 1720 &sensor_dev_attr_fan3_min.dev_attr.attr, 1721 &sensor_dev_attr_fan3_alarm.dev_attr.attr, 1722 &sensor_dev_attr_fan3_type.dev_attr.attr, 1723 NULL 1724 }; 1725 static struct attribute *dme1737_fan4_attr[] = { 1726 &sensor_dev_attr_fan4_input.dev_attr.attr, 1727 &sensor_dev_attr_fan4_min.dev_attr.attr, 1728 &sensor_dev_attr_fan4_alarm.dev_attr.attr, 1729 &sensor_dev_attr_fan4_type.dev_attr.attr, 1730 NULL 1731 }; 1732 static struct attribute *dme1737_fan5_attr[] = { 1733 &sensor_dev_attr_fan5_input.dev_attr.attr, 1734 &sensor_dev_attr_fan5_min.dev_attr.attr, 1735 &sensor_dev_attr_fan5_alarm.dev_attr.attr, 1736 &sensor_dev_attr_fan5_max.dev_attr.attr, 1737 NULL 1738 }; 1739 static struct attribute *dme1737_fan6_attr[] = { 1740 &sensor_dev_attr_fan6_input.dev_attr.attr, 1741 &sensor_dev_attr_fan6_min.dev_attr.attr, 1742 &sensor_dev_attr_fan6_alarm.dev_attr.attr, 1743 &sensor_dev_attr_fan6_max.dev_attr.attr, 1744 NULL 1745 }; 1746 1747 static const struct attribute_group dme1737_fan_group[] = { 1748 { .attrs = dme1737_fan1_attr }, 1749 { .attrs = dme1737_fan2_attr }, 1750 { .attrs = dme1737_fan3_attr }, 1751 { .attrs = dme1737_fan4_attr }, 1752 { .attrs = dme1737_fan5_attr }, 1753 { .attrs = dme1737_fan6_attr }, 1754 }; 1755 1756 /* The permissions of the following zone attributes are changed to read- 1757 * writeable if the chip is *not* locked. Otherwise they stay read-only. */ 1758 static struct attribute *dme1737_zone_chmod_attr[] = { 1759 &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, 1760 &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, 1761 &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, 1762 &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, 1763 &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, 1764 &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, 1765 &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, 1766 &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, 1767 &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, 1768 NULL 1769 }; 1770 1771 static const struct attribute_group dme1737_zone_chmod_group = { 1772 .attrs = dme1737_zone_chmod_attr, 1773 }; 1774 1775 /* The permissions of the following PWM attributes are changed to read- 1776 * writeable if the chip is *not* locked and the respective PWM is available. 1777 * Otherwise they stay read-only. */ 1778 static struct attribute *dme1737_pwm1_chmod_attr[] = { 1779 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 1780 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1781 &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, 1782 &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, 1783 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 1784 NULL 1785 }; 1786 static struct attribute *dme1737_pwm2_chmod_attr[] = { 1787 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 1788 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 1789 &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, 1790 &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, 1791 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, 1792 NULL 1793 }; 1794 static struct attribute *dme1737_pwm3_chmod_attr[] = { 1795 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 1796 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 1797 &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, 1798 &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, 1799 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, 1800 NULL 1801 }; 1802 static struct attribute *dme1737_pwm5_chmod_attr[] = { 1803 &sensor_dev_attr_pwm5.dev_attr.attr, 1804 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 1805 NULL 1806 }; 1807 static struct attribute *dme1737_pwm6_chmod_attr[] = { 1808 &sensor_dev_attr_pwm6.dev_attr.attr, 1809 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 1810 NULL 1811 }; 1812 1813 static const struct attribute_group dme1737_pwm_chmod_group[] = { 1814 { .attrs = dme1737_pwm1_chmod_attr }, 1815 { .attrs = dme1737_pwm2_chmod_attr }, 1816 { .attrs = dme1737_pwm3_chmod_attr }, 1817 { .attrs = NULL }, 1818 { .attrs = dme1737_pwm5_chmod_attr }, 1819 { .attrs = dme1737_pwm6_chmod_attr }, 1820 }; 1821 1822 /* Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the 1823 * chip is not locked. Otherwise they are read-only. */ 1824 static struct attribute *dme1737_pwm_chmod_attr[] = { 1825 &sensor_dev_attr_pwm1.dev_attr.attr, 1826 &sensor_dev_attr_pwm2.dev_attr.attr, 1827 &sensor_dev_attr_pwm3.dev_attr.attr, 1828 }; 1829 1830 /* --------------------------------------------------------------------- 1831 * Super-IO functions 1832 * --------------------------------------------------------------------- */ 1833 1834 static inline void dme1737_sio_enter(int sio_cip) 1835 { 1836 outb(0x55, sio_cip); 1837 } 1838 1839 static inline void dme1737_sio_exit(int sio_cip) 1840 { 1841 outb(0xaa, sio_cip); 1842 } 1843 1844 static inline int dme1737_sio_inb(int sio_cip, int reg) 1845 { 1846 outb(reg, sio_cip); 1847 return inb(sio_cip + 1); 1848 } 1849 1850 static inline void dme1737_sio_outb(int sio_cip, int reg, int val) 1851 { 1852 outb(reg, sio_cip); 1853 outb(val, sio_cip + 1); 1854 } 1855 1856 /* --------------------------------------------------------------------- 1857 * Device initialization 1858 * --------------------------------------------------------------------- */ 1859 1860 static int dme1737_i2c_get_features(int, struct dme1737_data*); 1861 1862 static void dme1737_chmod_file(struct device *dev, 1863 struct attribute *attr, mode_t mode) 1864 { 1865 if (sysfs_chmod_file(&dev->kobj, attr, mode)) { 1866 dev_warn(dev, "Failed to change permissions of %s.\n", 1867 attr->name); 1868 } 1869 } 1870 1871 static void dme1737_chmod_group(struct device *dev, 1872 const struct attribute_group *group, 1873 mode_t mode) 1874 { 1875 struct attribute **attr; 1876 1877 for (attr = group->attrs; *attr; attr++) { 1878 dme1737_chmod_file(dev, *attr, mode); 1879 } 1880 } 1881 1882 static void dme1737_remove_files(struct device *dev) 1883 { 1884 struct dme1737_data *data = dev_get_drvdata(dev); 1885 int ix; 1886 1887 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { 1888 if (data->has_fan & (1 << ix)) { 1889 sysfs_remove_group(&dev->kobj, 1890 &dme1737_fan_group[ix]); 1891 } 1892 } 1893 1894 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) { 1895 if (data->has_pwm & (1 << ix)) { 1896 sysfs_remove_group(&dev->kobj, 1897 &dme1737_pwm_group[ix]); 1898 if (data->type != sch5027 && ix < 3) { 1899 sysfs_remove_file(&dev->kobj, 1900 dme1737_pwm_misc_attr[ix]); 1901 } 1902 } 1903 } 1904 1905 if (data->type != sch5027) { 1906 sysfs_remove_group(&dev->kobj, &dme1737_misc_group); 1907 } 1908 1909 sysfs_remove_group(&dev->kobj, &dme1737_group); 1910 1911 if (!data->client.driver) { 1912 sysfs_remove_file(&dev->kobj, &dev_attr_name.attr); 1913 } 1914 } 1915 1916 static int dme1737_create_files(struct device *dev) 1917 { 1918 struct dme1737_data *data = dev_get_drvdata(dev); 1919 int err, ix; 1920 1921 /* Create a name attribute for ISA devices */ 1922 if (!data->client.driver && 1923 (err = sysfs_create_file(&dev->kobj, &dev_attr_name.attr))) { 1924 goto exit; 1925 } 1926 1927 /* Create standard sysfs attributes */ 1928 if ((err = sysfs_create_group(&dev->kobj, &dme1737_group))) { 1929 goto exit_remove; 1930 } 1931 1932 /* Create misc sysfs attributes */ 1933 if ((data->type != sch5027) && 1934 (err = sysfs_create_group(&dev->kobj, 1935 &dme1737_misc_group))) { 1936 goto exit_remove; 1937 } 1938 1939 /* Create fan sysfs attributes */ 1940 for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { 1941 if (data->has_fan & (1 << ix)) { 1942 if ((err = sysfs_create_group(&dev->kobj, 1943 &dme1737_fan_group[ix]))) { 1944 goto exit_remove; 1945 } 1946 } 1947 } 1948 1949 /* Create PWM sysfs attributes */ 1950 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_group); ix++) { 1951 if (data->has_pwm & (1 << ix)) { 1952 if ((err = sysfs_create_group(&dev->kobj, 1953 &dme1737_pwm_group[ix]))) { 1954 goto exit_remove; 1955 } 1956 if (data->type != sch5027 && ix < 3 && 1957 (err = sysfs_create_file(&dev->kobj, 1958 dme1737_pwm_misc_attr[ix]))) { 1959 goto exit_remove; 1960 } 1961 } 1962 } 1963 1964 /* Inform if the device is locked. Otherwise change the permissions of 1965 * selected attributes from read-only to read-writeable. */ 1966 if (data->config & 0x02) { 1967 dev_info(dev, "Device is locked. Some attributes " 1968 "will be read-only.\n"); 1969 } else { 1970 /* Change permissions of zone sysfs attributes */ 1971 dme1737_chmod_group(dev, &dme1737_zone_chmod_group, 1972 S_IRUGO | S_IWUSR); 1973 1974 /* Change permissions of misc sysfs attributes */ 1975 if (data->type != sch5027) { 1976 dme1737_chmod_group(dev, &dme1737_misc_group, 1977 S_IRUGO | S_IWUSR); 1978 } 1979 1980 /* Change permissions of PWM sysfs attributes */ 1981 for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) { 1982 if (data->has_pwm & (1 << ix)) { 1983 dme1737_chmod_group(dev, 1984 &dme1737_pwm_chmod_group[ix], 1985 S_IRUGO | S_IWUSR); 1986 if (data->type != sch5027 && ix < 3) { 1987 dme1737_chmod_file(dev, 1988 dme1737_pwm_misc_attr[ix], 1989 S_IRUGO | S_IWUSR); 1990 } 1991 } 1992 } 1993 1994 /* Change permissions of pwm[1-3] if in manual mode */ 1995 for (ix = 0; ix < 3; ix++) { 1996 if ((data->has_pwm & (1 << ix)) && 1997 (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) { 1998 dme1737_chmod_file(dev, 1999 dme1737_pwm_chmod_attr[ix], 2000 S_IRUGO | S_IWUSR); 2001 } 2002 } 2003 } 2004 2005 return 0; 2006 2007 exit_remove: 2008 dme1737_remove_files(dev); 2009 exit: 2010 return err; 2011 } 2012 2013 static int dme1737_init_device(struct device *dev) 2014 { 2015 struct dme1737_data *data = dev_get_drvdata(dev); 2016 struct i2c_client *client = &data->client; 2017 int ix; 2018 u8 reg; 2019 2020 /* Point to the right nominal voltages array */ 2021 data->in_nominal = IN_NOMINAL(data->type); 2022 2023 data->config = dme1737_read(client, DME1737_REG_CONFIG); 2024 /* Inform if part is not monitoring/started */ 2025 if (!(data->config & 0x01)) { 2026 if (!force_start) { 2027 dev_err(dev, "Device is not monitoring. " 2028 "Use the force_start load parameter to " 2029 "override.\n"); 2030 return -EFAULT; 2031 } 2032 2033 /* Force monitoring */ 2034 data->config |= 0x01; 2035 dme1737_write(client, DME1737_REG_CONFIG, data->config); 2036 } 2037 /* Inform if part is not ready */ 2038 if (!(data->config & 0x04)) { 2039 dev_err(dev, "Device is not ready.\n"); 2040 return -EFAULT; 2041 } 2042 2043 /* Determine which optional fan and pwm features are enabled/present */ 2044 if (client->driver) { /* I2C chip */ 2045 data->config2 = dme1737_read(client, DME1737_REG_CONFIG2); 2046 /* Check if optional fan3 input is enabled */ 2047 if (data->config2 & 0x04) { 2048 data->has_fan |= (1 << 2); 2049 } 2050 2051 /* Fan4 and pwm3 are only available if the client's I2C address 2052 * is the default 0x2e. Otherwise the I/Os associated with 2053 * these functions are used for addr enable/select. */ 2054 if (data->client.addr == 0x2e) { 2055 data->has_fan |= (1 << 3); 2056 data->has_pwm |= (1 << 2); 2057 } 2058 2059 /* Determine which of the optional fan[5-6] and pwm[5-6] 2060 * features are enabled. For this, we need to query the runtime 2061 * registers through the Super-IO LPC interface. Try both 2062 * config ports 0x2e and 0x4e. */ 2063 if (dme1737_i2c_get_features(0x2e, data) && 2064 dme1737_i2c_get_features(0x4e, data)) { 2065 dev_warn(dev, "Failed to query Super-IO for optional " 2066 "features.\n"); 2067 } 2068 } else { /* ISA chip */ 2069 /* Fan3 and pwm3 are always available. Fan[4-5] and pwm[5-6] 2070 * don't exist in the ISA chip. */ 2071 data->has_fan |= (1 << 2); 2072 data->has_pwm |= (1 << 2); 2073 } 2074 2075 /* Fan1, fan2, pwm1, and pwm2 are always present */ 2076 data->has_fan |= 0x03; 2077 data->has_pwm |= 0x03; 2078 2079 dev_info(dev, "Optional features: pwm3=%s, pwm5=%s, pwm6=%s, " 2080 "fan3=%s, fan4=%s, fan5=%s, fan6=%s.\n", 2081 (data->has_pwm & (1 << 2)) ? "yes" : "no", 2082 (data->has_pwm & (1 << 4)) ? "yes" : "no", 2083 (data->has_pwm & (1 << 5)) ? "yes" : "no", 2084 (data->has_fan & (1 << 2)) ? "yes" : "no", 2085 (data->has_fan & (1 << 3)) ? "yes" : "no", 2086 (data->has_fan & (1 << 4)) ? "yes" : "no", 2087 (data->has_fan & (1 << 5)) ? "yes" : "no"); 2088 2089 reg = dme1737_read(client, DME1737_REG_TACH_PWM); 2090 /* Inform if fan-to-pwm mapping differs from the default */ 2091 if (client->driver && reg != 0xa4) { /* I2C chip */ 2092 dev_warn(dev, "Non-standard fan to pwm mapping: " 2093 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d, " 2094 "fan4->pwm%d. Please report to the driver " 2095 "maintainer.\n", 2096 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1, 2097 ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1); 2098 } else if (!client->driver && reg != 0x24) { /* ISA chip */ 2099 dev_warn(dev, "Non-standard fan to pwm mapping: " 2100 "fan1->pwm%d, fan2->pwm%d, fan3->pwm%d. " 2101 "Please report to the driver maintainer.\n", 2102 (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1, 2103 ((reg >> 4) & 0x03) + 1); 2104 } 2105 2106 /* Switch pwm[1-3] to manual mode if they are currently disabled and 2107 * set the duty-cycles to 0% (which is identical to the PWMs being 2108 * disabled). */ 2109 if (!(data->config & 0x02)) { 2110 for (ix = 0; ix < 3; ix++) { 2111 data->pwm_config[ix] = dme1737_read(client, 2112 DME1737_REG_PWM_CONFIG(ix)); 2113 if ((data->has_pwm & (1 << ix)) && 2114 (PWM_EN_FROM_REG(data->pwm_config[ix]) == -1)) { 2115 dev_info(dev, "Switching pwm%d to " 2116 "manual mode.\n", ix + 1); 2117 data->pwm_config[ix] = PWM_EN_TO_REG(1, 2118 data->pwm_config[ix]); 2119 dme1737_write(client, DME1737_REG_PWM(ix), 0); 2120 dme1737_write(client, 2121 DME1737_REG_PWM_CONFIG(ix), 2122 data->pwm_config[ix]); 2123 } 2124 } 2125 } 2126 2127 /* Initialize the default PWM auto channels zone (acz) assignments */ 2128 data->pwm_acz[0] = 1; /* pwm1 -> zone1 */ 2129 data->pwm_acz[1] = 2; /* pwm2 -> zone2 */ 2130 data->pwm_acz[2] = 4; /* pwm3 -> zone3 */ 2131 2132 /* Set VRM */ 2133 if (data->type != sch5027) { 2134 data->vrm = vid_which_vrm(); 2135 } 2136 2137 return 0; 2138 } 2139 2140 /* --------------------------------------------------------------------- 2141 * I2C device detection and registration 2142 * --------------------------------------------------------------------- */ 2143 2144 static struct i2c_driver dme1737_i2c_driver; 2145 2146 static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data) 2147 { 2148 int err = 0, reg; 2149 u16 addr; 2150 2151 dme1737_sio_enter(sio_cip); 2152 2153 /* Check device ID 2154 * The DME1737 can return either 0x78 or 0x77 as its device ID. 2155 * The SCH5027 returns 0x89 as its device ID. */ 2156 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); 2157 if (!(reg == 0x77 || reg == 0x78 || reg == 0x89)) { 2158 err = -ENODEV; 2159 goto exit; 2160 } 2161 2162 /* Select logical device A (runtime registers) */ 2163 dme1737_sio_outb(sio_cip, 0x07, 0x0a); 2164 2165 /* Get the base address of the runtime registers */ 2166 if (!(addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) | 2167 dme1737_sio_inb(sio_cip, 0x61))) { 2168 err = -ENODEV; 2169 goto exit; 2170 } 2171 2172 /* Read the runtime registers to determine which optional features 2173 * are enabled and available. Bits [3:2] of registers 0x43-0x46 are set 2174 * to '10' if the respective feature is enabled. */ 2175 if ((inb(addr + 0x43) & 0x0c) == 0x08) { /* fan6 */ 2176 data->has_fan |= (1 << 5); 2177 } 2178 if ((inb(addr + 0x44) & 0x0c) == 0x08) { /* pwm6 */ 2179 data->has_pwm |= (1 << 5); 2180 } 2181 if ((inb(addr + 0x45) & 0x0c) == 0x08) { /* fan5 */ 2182 data->has_fan |= (1 << 4); 2183 } 2184 if ((inb(addr + 0x46) & 0x0c) == 0x08) { /* pwm5 */ 2185 data->has_pwm |= (1 << 4); 2186 } 2187 2188 exit: 2189 dme1737_sio_exit(sio_cip); 2190 2191 return err; 2192 } 2193 2194 static int dme1737_i2c_detect(struct i2c_adapter *adapter, int address, 2195 int kind) 2196 { 2197 u8 company, verstep = 0; 2198 struct i2c_client *client; 2199 struct dme1737_data *data; 2200 struct device *dev; 2201 int err = 0; 2202 const char *name; 2203 2204 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { 2205 goto exit; 2206 } 2207 2208 if (!(data = kzalloc(sizeof(struct dme1737_data), GFP_KERNEL))) { 2209 err = -ENOMEM; 2210 goto exit; 2211 } 2212 2213 client = &data->client; 2214 i2c_set_clientdata(client, data); 2215 client->addr = address; 2216 client->adapter = adapter; 2217 client->driver = &dme1737_i2c_driver; 2218 dev = &client->dev; 2219 2220 /* A negative kind means that the driver was loaded with no force 2221 * parameter (default), so we must identify the chip. */ 2222 if (kind < 0) { 2223 company = dme1737_read(client, DME1737_REG_COMPANY); 2224 verstep = dme1737_read(client, DME1737_REG_VERSTEP); 2225 2226 if (company == DME1737_COMPANY_SMSC && 2227 (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) { 2228 kind = dme1737; 2229 } else if (company == DME1737_COMPANY_SMSC && 2230 verstep == SCH5027_VERSTEP) { 2231 kind = sch5027; 2232 } else { 2233 err = -ENODEV; 2234 goto exit_kfree; 2235 } 2236 } 2237 2238 if (kind == sch5027) { 2239 name = "sch5027"; 2240 } else { 2241 kind = dme1737; 2242 name = "dme1737"; 2243 } 2244 data->type = kind; 2245 2246 /* Fill in the remaining client fields and put it into the global 2247 * list */ 2248 strlcpy(client->name, name, I2C_NAME_SIZE); 2249 mutex_init(&data->update_lock); 2250 2251 /* Tell the I2C layer a new client has arrived */ 2252 if ((err = i2c_attach_client(client))) { 2253 goto exit_kfree; 2254 } 2255 2256 dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n", 2257 kind == sch5027 ? "SCH5027" : "DME1737", client->addr, 2258 verstep); 2259 2260 /* Initialize the DME1737 chip */ 2261 if ((err = dme1737_init_device(dev))) { 2262 dev_err(dev, "Failed to initialize device.\n"); 2263 goto exit_detach; 2264 } 2265 2266 /* Create sysfs files */ 2267 if ((err = dme1737_create_files(dev))) { 2268 dev_err(dev, "Failed to create sysfs files.\n"); 2269 goto exit_detach; 2270 } 2271 2272 /* Register device */ 2273 data->hwmon_dev = hwmon_device_register(dev); 2274 if (IS_ERR(data->hwmon_dev)) { 2275 dev_err(dev, "Failed to register device.\n"); 2276 err = PTR_ERR(data->hwmon_dev); 2277 goto exit_remove; 2278 } 2279 2280 return 0; 2281 2282 exit_remove: 2283 dme1737_remove_files(dev); 2284 exit_detach: 2285 i2c_detach_client(client); 2286 exit_kfree: 2287 kfree(data); 2288 exit: 2289 return err; 2290 } 2291 2292 static int dme1737_i2c_attach_adapter(struct i2c_adapter *adapter) 2293 { 2294 if (!(adapter->class & I2C_CLASS_HWMON)) { 2295 return 0; 2296 } 2297 2298 return i2c_probe(adapter, &addr_data, dme1737_i2c_detect); 2299 } 2300 2301 static int dme1737_i2c_detach_client(struct i2c_client *client) 2302 { 2303 struct dme1737_data *data = i2c_get_clientdata(client); 2304 int err; 2305 2306 hwmon_device_unregister(data->hwmon_dev); 2307 dme1737_remove_files(&client->dev); 2308 2309 if ((err = i2c_detach_client(client))) { 2310 return err; 2311 } 2312 2313 kfree(data); 2314 return 0; 2315 } 2316 2317 static struct i2c_driver dme1737_i2c_driver = { 2318 .driver = { 2319 .name = "dme1737", 2320 }, 2321 .attach_adapter = dme1737_i2c_attach_adapter, 2322 .detach_client = dme1737_i2c_detach_client, 2323 }; 2324 2325 /* --------------------------------------------------------------------- 2326 * ISA device detection and registration 2327 * --------------------------------------------------------------------- */ 2328 2329 static int __init dme1737_isa_detect(int sio_cip, unsigned short *addr) 2330 { 2331 int err = 0, reg; 2332 unsigned short base_addr; 2333 2334 dme1737_sio_enter(sio_cip); 2335 2336 /* Check device ID 2337 * We currently know about SCH3112 (0x7c), SCH3114 (0x7d), and 2338 * SCH3116 (0x7f). */ 2339 reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); 2340 if (!(reg == 0x7c || reg == 0x7d || reg == 0x7f)) { 2341 err = -ENODEV; 2342 goto exit; 2343 } 2344 2345 /* Select logical device A (runtime registers) */ 2346 dme1737_sio_outb(sio_cip, 0x07, 0x0a); 2347 2348 /* Get the base address of the runtime registers */ 2349 if (!(base_addr = (dme1737_sio_inb(sio_cip, 0x60) << 8) | 2350 dme1737_sio_inb(sio_cip, 0x61))) { 2351 printk(KERN_ERR "dme1737: Base address not set.\n"); 2352 err = -ENODEV; 2353 goto exit; 2354 } 2355 2356 /* Access to the hwmon registers is through an index/data register 2357 * pair located at offset 0x70/0x71. */ 2358 *addr = base_addr + 0x70; 2359 2360 exit: 2361 dme1737_sio_exit(sio_cip); 2362 return err; 2363 } 2364 2365 static int __init dme1737_isa_device_add(unsigned short addr) 2366 { 2367 struct resource res = { 2368 .start = addr, 2369 .end = addr + DME1737_EXTENT - 1, 2370 .name = "dme1737", 2371 .flags = IORESOURCE_IO, 2372 }; 2373 int err; 2374 2375 if (!(pdev = platform_device_alloc("dme1737", addr))) { 2376 printk(KERN_ERR "dme1737: Failed to allocate device.\n"); 2377 err = -ENOMEM; 2378 goto exit; 2379 } 2380 2381 if ((err = platform_device_add_resources(pdev, &res, 1))) { 2382 printk(KERN_ERR "dme1737: Failed to add device resource " 2383 "(err = %d).\n", err); 2384 goto exit_device_put; 2385 } 2386 2387 if ((err = platform_device_add(pdev))) { 2388 printk(KERN_ERR "dme1737: Failed to add device (err = %d).\n", 2389 err); 2390 goto exit_device_put; 2391 } 2392 2393 return 0; 2394 2395 exit_device_put: 2396 platform_device_put(pdev); 2397 pdev = NULL; 2398 exit: 2399 return err; 2400 } 2401 2402 static int __devinit dme1737_isa_probe(struct platform_device *pdev) 2403 { 2404 u8 company, device; 2405 struct resource *res; 2406 struct i2c_client *client; 2407 struct dme1737_data *data; 2408 struct device *dev = &pdev->dev; 2409 int err; 2410 2411 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 2412 if (!request_region(res->start, DME1737_EXTENT, "dme1737")) { 2413 dev_err(dev, "Failed to request region 0x%04x-0x%04x.\n", 2414 (unsigned short)res->start, 2415 (unsigned short)res->start + DME1737_EXTENT - 1); 2416 err = -EBUSY; 2417 goto exit; 2418 } 2419 2420 if (!(data = kzalloc(sizeof(struct dme1737_data), GFP_KERNEL))) { 2421 err = -ENOMEM; 2422 goto exit_release_region; 2423 } 2424 2425 client = &data->client; 2426 i2c_set_clientdata(client, data); 2427 client->addr = res->start; 2428 platform_set_drvdata(pdev, data); 2429 2430 /* Skip chip detection if module is loaded with force_id parameter */ 2431 if (!force_id) { 2432 company = dme1737_read(client, DME1737_REG_COMPANY); 2433 device = dme1737_read(client, DME1737_REG_DEVICE); 2434 2435 if (!((company == DME1737_COMPANY_SMSC) && 2436 (device == SCH311X_DEVICE))) { 2437 err = -ENODEV; 2438 goto exit_kfree; 2439 } 2440 } 2441 data->type = sch311x; 2442 2443 /* Fill in the remaining client fields and initialize the mutex */ 2444 strlcpy(client->name, "sch311x", I2C_NAME_SIZE); 2445 mutex_init(&data->update_lock); 2446 2447 dev_info(dev, "Found a SCH311x chip at 0x%04x\n", client->addr); 2448 2449 /* Initialize the chip */ 2450 if ((err = dme1737_init_device(dev))) { 2451 dev_err(dev, "Failed to initialize device.\n"); 2452 goto exit_kfree; 2453 } 2454 2455 /* Create sysfs files */ 2456 if ((err = dme1737_create_files(dev))) { 2457 dev_err(dev, "Failed to create sysfs files.\n"); 2458 goto exit_kfree; 2459 } 2460 2461 /* Register device */ 2462 data->hwmon_dev = hwmon_device_register(dev); 2463 if (IS_ERR(data->hwmon_dev)) { 2464 dev_err(dev, "Failed to register device.\n"); 2465 err = PTR_ERR(data->hwmon_dev); 2466 goto exit_remove_files; 2467 } 2468 2469 return 0; 2470 2471 exit_remove_files: 2472 dme1737_remove_files(dev); 2473 exit_kfree: 2474 platform_set_drvdata(pdev, NULL); 2475 kfree(data); 2476 exit_release_region: 2477 release_region(res->start, DME1737_EXTENT); 2478 exit: 2479 return err; 2480 } 2481 2482 static int __devexit dme1737_isa_remove(struct platform_device *pdev) 2483 { 2484 struct dme1737_data *data = platform_get_drvdata(pdev); 2485 2486 hwmon_device_unregister(data->hwmon_dev); 2487 dme1737_remove_files(&pdev->dev); 2488 release_region(data->client.addr, DME1737_EXTENT); 2489 platform_set_drvdata(pdev, NULL); 2490 kfree(data); 2491 2492 return 0; 2493 } 2494 2495 static struct platform_driver dme1737_isa_driver = { 2496 .driver = { 2497 .owner = THIS_MODULE, 2498 .name = "dme1737", 2499 }, 2500 .probe = dme1737_isa_probe, 2501 .remove = __devexit_p(dme1737_isa_remove), 2502 }; 2503 2504 /* --------------------------------------------------------------------- 2505 * Module initialization and cleanup 2506 * --------------------------------------------------------------------- */ 2507 2508 static int __init dme1737_init(void) 2509 { 2510 int err; 2511 unsigned short addr; 2512 2513 if ((err = i2c_add_driver(&dme1737_i2c_driver))) { 2514 goto exit; 2515 } 2516 2517 if (dme1737_isa_detect(0x2e, &addr) && 2518 dme1737_isa_detect(0x4e, &addr) && 2519 (!probe_all_addr || 2520 (dme1737_isa_detect(0x162e, &addr) && 2521 dme1737_isa_detect(0x164e, &addr)))) { 2522 /* Return 0 if we didn't find an ISA device */ 2523 return 0; 2524 } 2525 2526 if ((err = platform_driver_register(&dme1737_isa_driver))) { 2527 goto exit_del_i2c_driver; 2528 } 2529 2530 /* Sets global pdev as a side effect */ 2531 if ((err = dme1737_isa_device_add(addr))) { 2532 goto exit_del_isa_driver; 2533 } 2534 2535 return 0; 2536 2537 exit_del_isa_driver: 2538 platform_driver_unregister(&dme1737_isa_driver); 2539 exit_del_i2c_driver: 2540 i2c_del_driver(&dme1737_i2c_driver); 2541 exit: 2542 return err; 2543 } 2544 2545 static void __exit dme1737_exit(void) 2546 { 2547 if (pdev) { 2548 platform_device_unregister(pdev); 2549 platform_driver_unregister(&dme1737_isa_driver); 2550 } 2551 2552 i2c_del_driver(&dme1737_i2c_driver); 2553 } 2554 2555 MODULE_AUTHOR("Juerg Haefliger <juergh@gmail.com>"); 2556 MODULE_DESCRIPTION("DME1737 sensors"); 2557 MODULE_LICENSE("GPL"); 2558 2559 module_init(dme1737_init); 2560 module_exit(dme1737_exit); 2561