1 /* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 or later as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/errno.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/delay.h> 13 #include <linux/hwmon.h> 14 #include <linux/hwmon-sysfs.h> 15 #include <linux/io.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_device.h> 20 #include <linux/platform_device.h> 21 #include <linux/sysfs.h> 22 #include <linux/regmap.h> 23 24 /* ASPEED PWM & FAN Tach Register Definition */ 25 #define ASPEED_PTCR_CTRL 0x00 26 #define ASPEED_PTCR_CLK_CTRL 0x04 27 #define ASPEED_PTCR_DUTY0_CTRL 0x08 28 #define ASPEED_PTCR_DUTY1_CTRL 0x0c 29 #define ASPEED_PTCR_TYPEM_CTRL 0x10 30 #define ASPEED_PTCR_TYPEM_CTRL1 0x14 31 #define ASPEED_PTCR_TYPEN_CTRL 0x18 32 #define ASPEED_PTCR_TYPEN_CTRL1 0x1c 33 #define ASPEED_PTCR_TACH_SOURCE 0x20 34 #define ASPEED_PTCR_TRIGGER 0x28 35 #define ASPEED_PTCR_RESULT 0x2c 36 #define ASPEED_PTCR_INTR_CTRL 0x30 37 #define ASPEED_PTCR_INTR_STS 0x34 38 #define ASPEED_PTCR_TYPEM_LIMIT 0x38 39 #define ASPEED_PTCR_TYPEN_LIMIT 0x3C 40 #define ASPEED_PTCR_CTRL_EXT 0x40 41 #define ASPEED_PTCR_CLK_CTRL_EXT 0x44 42 #define ASPEED_PTCR_DUTY2_CTRL 0x48 43 #define ASPEED_PTCR_DUTY3_CTRL 0x4c 44 #define ASPEED_PTCR_TYPEO_CTRL 0x50 45 #define ASPEED_PTCR_TYPEO_CTRL1 0x54 46 #define ASPEED_PTCR_TACH_SOURCE_EXT 0x60 47 #define ASPEED_PTCR_TYPEO_LIMIT 0x78 48 49 /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */ 50 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1 15 51 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2 6 52 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK (BIT(7) | BIT(15)) 53 54 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1 14 55 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2 5 56 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK (BIT(6) | BIT(14)) 57 58 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1 13 59 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2 4 60 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK (BIT(5) | BIT(13)) 61 62 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1 12 63 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2 3 64 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK (BIT(4) | BIT(12)) 65 66 #define ASPEED_PTCR_CTRL_FAN_NUM_EN(x) BIT(16 + (x)) 67 68 #define ASPEED_PTCR_CTRL_PWMD_EN BIT(11) 69 #define ASPEED_PTCR_CTRL_PWMC_EN BIT(10) 70 #define ASPEED_PTCR_CTRL_PWMB_EN BIT(9) 71 #define ASPEED_PTCR_CTRL_PWMA_EN BIT(8) 72 73 #define ASPEED_PTCR_CTRL_CLK_SRC BIT(1) 74 #define ASPEED_PTCR_CTRL_CLK_EN BIT(0) 75 76 /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */ 77 /* TYPE N */ 78 #define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK GENMASK(31, 16) 79 #define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT 24 80 #define ASPEED_PTCR_CLK_CTRL_TYPEN_H 20 81 #define ASPEED_PTCR_CLK_CTRL_TYPEN_L 16 82 /* TYPE M */ 83 #define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK GENMASK(15, 0) 84 #define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT 8 85 #define ASPEED_PTCR_CLK_CTRL_TYPEM_H 4 86 #define ASPEED_PTCR_CLK_CTRL_TYPEM_L 0 87 88 /* 89 * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control 90 * 0/1/2/3 register 91 */ 92 #define DUTY_CTRL_PWM2_FALL_POINT 24 93 #define DUTY_CTRL_PWM2_RISE_POINT 16 94 #define DUTY_CTRL_PWM2_RISE_FALL_MASK GENMASK(31, 16) 95 #define DUTY_CTRL_PWM1_FALL_POINT 8 96 #define DUTY_CTRL_PWM1_RISE_POINT 0 97 #define DUTY_CTRL_PWM1_RISE_FALL_MASK GENMASK(15, 0) 98 99 /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */ 100 #define TYPE_CTRL_FAN_MASK (GENMASK(5, 1) | GENMASK(31, 16)) 101 #define TYPE_CTRL_FAN1_MASK GENMASK(31, 0) 102 #define TYPE_CTRL_FAN_PERIOD 16 103 #define TYPE_CTRL_FAN_MODE 4 104 #define TYPE_CTRL_FAN_DIVISION 1 105 #define TYPE_CTRL_FAN_TYPE_EN 1 106 107 /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */ 108 /* bit [0,1] at 0x20, bit [2] at 0x60 */ 109 #define TACH_PWM_SOURCE_BIT01(x) ((x) * 2) 110 #define TACH_PWM_SOURCE_BIT2(x) ((x) * 2) 111 #define TACH_PWM_SOURCE_MASK_BIT01(x) (0x3 << ((x) * 2)) 112 #define TACH_PWM_SOURCE_MASK_BIT2(x) BIT((x) * 2) 113 114 /* ASPEED_PTCR_RESULT : 0x2c - Result Register */ 115 #define RESULT_STATUS_MASK BIT(31) 116 #define RESULT_VALUE_MASK 0xfffff 117 118 /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */ 119 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1 15 120 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2 6 121 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK (BIT(7) | BIT(15)) 122 123 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1 14 124 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2 5 125 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK (BIT(6) | BIT(14)) 126 127 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1 13 128 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2 4 129 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK (BIT(5) | BIT(13)) 130 131 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1 12 132 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2 3 133 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK (BIT(4) | BIT(12)) 134 135 #define ASPEED_PTCR_CTRL_PWMH_EN BIT(11) 136 #define ASPEED_PTCR_CTRL_PWMG_EN BIT(10) 137 #define ASPEED_PTCR_CTRL_PWMF_EN BIT(9) 138 #define ASPEED_PTCR_CTRL_PWME_EN BIT(8) 139 140 /* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */ 141 /* TYPE O */ 142 #define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK GENMASK(15, 0) 143 #define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT 8 144 #define ASPEED_PTCR_CLK_CTRL_TYPEO_H 4 145 #define ASPEED_PTCR_CLK_CTRL_TYPEO_L 0 146 147 #define PWM_MAX 255 148 149 #define M_PWM_DIV_H 0x00 150 #define M_PWM_DIV_L 0x05 151 #define M_PWM_PERIOD 0x5F 152 #define M_TACH_CLK_DIV 0x00 153 #define M_TACH_MODE 0x00 154 #define M_TACH_UNIT 0x1000 155 #define INIT_FAN_CTRL 0xFF 156 157 struct aspeed_pwm_tacho_data { 158 struct regmap *regmap; 159 unsigned long clk_freq; 160 bool pwm_present[8]; 161 bool fan_tach_present[16]; 162 u8 type_pwm_clock_unit[3]; 163 u8 type_pwm_clock_division_h[3]; 164 u8 type_pwm_clock_division_l[3]; 165 u8 type_fan_tach_clock_division[3]; 166 u16 type_fan_tach_unit[3]; 167 u8 pwm_port_type[8]; 168 u8 pwm_port_fan_ctrl[8]; 169 u8 fan_tach_ch_source[16]; 170 const struct attribute_group *groups[3]; 171 }; 172 173 enum type { TYPEM, TYPEN, TYPEO }; 174 175 struct type_params { 176 u32 l_value; 177 u32 h_value; 178 u32 unit_value; 179 u32 clk_ctrl_mask; 180 u32 clk_ctrl_reg; 181 u32 ctrl_reg; 182 u32 ctrl_reg1; 183 }; 184 185 static const struct type_params type_params[] = { 186 [TYPEM] = { 187 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L, 188 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H, 189 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT, 190 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK, 191 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL, 192 .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL, 193 .ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1, 194 }, 195 [TYPEN] = { 196 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L, 197 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H, 198 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT, 199 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK, 200 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL, 201 .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL, 202 .ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1, 203 }, 204 [TYPEO] = { 205 .l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L, 206 .h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H, 207 .unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT, 208 .clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK, 209 .clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT, 210 .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL, 211 .ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1, 212 } 213 }; 214 215 enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH }; 216 217 struct pwm_port_params { 218 u32 pwm_en; 219 u32 ctrl_reg; 220 u32 type_part1; 221 u32 type_part2; 222 u32 type_mask; 223 u32 duty_ctrl_rise_point; 224 u32 duty_ctrl_fall_point; 225 u32 duty_ctrl_reg; 226 u32 duty_ctrl_rise_fall_mask; 227 }; 228 229 static const struct pwm_port_params pwm_port_params[] = { 230 [PWMA] = { 231 .pwm_en = ASPEED_PTCR_CTRL_PWMA_EN, 232 .ctrl_reg = ASPEED_PTCR_CTRL, 233 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1, 234 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2, 235 .type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK, 236 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 237 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 238 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL, 239 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 240 }, 241 [PWMB] = { 242 .pwm_en = ASPEED_PTCR_CTRL_PWMB_EN, 243 .ctrl_reg = ASPEED_PTCR_CTRL, 244 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1, 245 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2, 246 .type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK, 247 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 248 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 249 .duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL, 250 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 251 }, 252 [PWMC] = { 253 .pwm_en = ASPEED_PTCR_CTRL_PWMC_EN, 254 .ctrl_reg = ASPEED_PTCR_CTRL, 255 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1, 256 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2, 257 .type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK, 258 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 259 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 260 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL, 261 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 262 }, 263 [PWMD] = { 264 .pwm_en = ASPEED_PTCR_CTRL_PWMD_EN, 265 .ctrl_reg = ASPEED_PTCR_CTRL, 266 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1, 267 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2, 268 .type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK, 269 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 270 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 271 .duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL, 272 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 273 }, 274 [PWME] = { 275 .pwm_en = ASPEED_PTCR_CTRL_PWME_EN, 276 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 277 .type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1, 278 .type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2, 279 .type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK, 280 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 281 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 282 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL, 283 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 284 }, 285 [PWMF] = { 286 .pwm_en = ASPEED_PTCR_CTRL_PWMF_EN, 287 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 288 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1, 289 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2, 290 .type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK, 291 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 292 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 293 .duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL, 294 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 295 }, 296 [PWMG] = { 297 .pwm_en = ASPEED_PTCR_CTRL_PWMG_EN, 298 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 299 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1, 300 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2, 301 .type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK, 302 .duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT, 303 .duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT, 304 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL, 305 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK, 306 }, 307 [PWMH] = { 308 .pwm_en = ASPEED_PTCR_CTRL_PWMH_EN, 309 .ctrl_reg = ASPEED_PTCR_CTRL_EXT, 310 .type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1, 311 .type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2, 312 .type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK, 313 .duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT, 314 .duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT, 315 .duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL, 316 .duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK, 317 } 318 }; 319 320 static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg, 321 unsigned int val) 322 { 323 void __iomem *regs = (void __iomem *)context; 324 325 writel(val, regs + reg); 326 return 0; 327 } 328 329 static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg, 330 unsigned int *val) 331 { 332 void __iomem *regs = (void __iomem *)context; 333 334 *val = readl(regs + reg); 335 return 0; 336 } 337 338 static const struct regmap_config aspeed_pwm_tacho_regmap_config = { 339 .reg_bits = 32, 340 .val_bits = 32, 341 .reg_stride = 4, 342 .max_register = ASPEED_PTCR_TYPEO_LIMIT, 343 .reg_write = regmap_aspeed_pwm_tacho_reg_write, 344 .reg_read = regmap_aspeed_pwm_tacho_reg_read, 345 .fast_io = true, 346 }; 347 348 static void aspeed_set_clock_enable(struct regmap *regmap, bool val) 349 { 350 regmap_update_bits(regmap, ASPEED_PTCR_CTRL, 351 ASPEED_PTCR_CTRL_CLK_EN, 352 val ? ASPEED_PTCR_CTRL_CLK_EN : 0); 353 } 354 355 static void aspeed_set_clock_source(struct regmap *regmap, int val) 356 { 357 regmap_update_bits(regmap, ASPEED_PTCR_CTRL, 358 ASPEED_PTCR_CTRL_CLK_SRC, 359 val ? ASPEED_PTCR_CTRL_CLK_SRC : 0); 360 } 361 362 static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type, 363 u8 div_high, u8 div_low, u8 unit) 364 { 365 u32 reg_value = ((div_high << type_params[type].h_value) | 366 (div_low << type_params[type].l_value) | 367 (unit << type_params[type].unit_value)); 368 369 regmap_update_bits(regmap, type_params[type].clk_ctrl_reg, 370 type_params[type].clk_ctrl_mask, reg_value); 371 } 372 373 static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port, 374 bool enable) 375 { 376 regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg, 377 pwm_port_params[pwm_port].pwm_en, 378 enable ? pwm_port_params[pwm_port].pwm_en : 0); 379 } 380 381 static void aspeed_set_pwm_port_type(struct regmap *regmap, 382 u8 pwm_port, u8 type) 383 { 384 u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1; 385 386 reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2; 387 388 regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg, 389 pwm_port_params[pwm_port].type_mask, reg_value); 390 } 391 392 static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap, 393 u8 pwm_port, u8 rising, 394 u8 falling) 395 { 396 u32 reg_value = (rising << 397 pwm_port_params[pwm_port].duty_ctrl_rise_point); 398 reg_value |= (falling << 399 pwm_port_params[pwm_port].duty_ctrl_fall_point); 400 401 regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg, 402 pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask, 403 reg_value); 404 } 405 406 static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type, 407 bool enable) 408 { 409 regmap_update_bits(regmap, type_params[type].ctrl_reg, 410 TYPE_CTRL_FAN_TYPE_EN, 411 enable ? TYPE_CTRL_FAN_TYPE_EN : 0); 412 } 413 414 static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type, 415 u8 mode, u16 unit, u8 division) 416 { 417 u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) | 418 (unit << TYPE_CTRL_FAN_PERIOD) | 419 (division << TYPE_CTRL_FAN_DIVISION)); 420 421 regmap_update_bits(regmap, type_params[type].ctrl_reg, 422 TYPE_CTRL_FAN_MASK, reg_value); 423 regmap_update_bits(regmap, type_params[type].ctrl_reg1, 424 TYPE_CTRL_FAN1_MASK, unit << 16); 425 } 426 427 static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch, 428 bool enable) 429 { 430 regmap_update_bits(regmap, ASPEED_PTCR_CTRL, 431 ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch), 432 enable ? 433 ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0); 434 } 435 436 static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch, 437 u8 fan_tach_ch_source) 438 { 439 u32 reg_value1 = ((fan_tach_ch_source & 0x3) << 440 TACH_PWM_SOURCE_BIT01(fan_tach_ch)); 441 u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) << 442 TACH_PWM_SOURCE_BIT2(fan_tach_ch)); 443 444 regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE, 445 TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch), 446 reg_value1); 447 448 regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 449 TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch), 450 reg_value2); 451 } 452 453 static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv, 454 u8 index, u8 fan_ctrl) 455 { 456 u16 period, dc_time_on; 457 458 period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]]; 459 period += 1; 460 dc_time_on = (fan_ctrl * period) / PWM_MAX; 461 462 if (dc_time_on == 0) { 463 aspeed_set_pwm_port_enable(priv->regmap, index, false); 464 } else { 465 if (dc_time_on == period) 466 dc_time_on = 0; 467 468 aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0, 469 dc_time_on); 470 aspeed_set_pwm_port_enable(priv->regmap, index, true); 471 } 472 } 473 474 static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data 475 *priv, u8 type) 476 { 477 u32 clk; 478 u16 tacho_unit; 479 u8 clk_unit, div_h, div_l, tacho_div; 480 481 clk = priv->clk_freq; 482 clk_unit = priv->type_pwm_clock_unit[type]; 483 div_h = priv->type_pwm_clock_division_h[type]; 484 div_h = 0x1 << div_h; 485 div_l = priv->type_pwm_clock_division_l[type]; 486 if (div_l == 0) 487 div_l = 1; 488 else 489 div_l = div_l * 2; 490 491 tacho_unit = priv->type_fan_tach_unit[type]; 492 tacho_div = priv->type_fan_tach_clock_division[type]; 493 494 tacho_div = 0x4 << (tacho_div * 2); 495 return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit); 496 } 497 498 static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv, 499 u8 fan_tach_ch) 500 { 501 u32 raw_data, tach_div, clk_source, sec, val; 502 u8 fan_tach_ch_source, type; 503 504 regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0); 505 regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch); 506 507 fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch]; 508 type = priv->pwm_port_type[fan_tach_ch_source]; 509 510 sec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type)); 511 msleep(sec); 512 513 regmap_read(priv->regmap, ASPEED_PTCR_RESULT, &val); 514 if (!(val & RESULT_STATUS_MASK)) 515 return -ETIMEDOUT; 516 517 raw_data = val & RESULT_VALUE_MASK; 518 tach_div = priv->type_fan_tach_clock_division[type]; 519 tach_div = 0x4 << (tach_div * 2); 520 clk_source = priv->clk_freq; 521 522 if (raw_data == 0) 523 return 0; 524 525 return (clk_source * 60) / (2 * raw_data * tach_div); 526 } 527 528 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, 529 const char *buf, size_t count) 530 { 531 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 532 int index = sensor_attr->index; 533 int ret; 534 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 535 long fan_ctrl; 536 537 ret = kstrtol(buf, 10, &fan_ctrl); 538 if (ret != 0) 539 return ret; 540 541 if (fan_ctrl < 0 || fan_ctrl > PWM_MAX) 542 return -EINVAL; 543 544 if (priv->pwm_port_fan_ctrl[index] == fan_ctrl) 545 return count; 546 547 priv->pwm_port_fan_ctrl[index] = fan_ctrl; 548 aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl); 549 550 return count; 551 } 552 553 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, 554 char *buf) 555 { 556 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 557 int index = sensor_attr->index; 558 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 559 560 return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]); 561 } 562 563 static ssize_t show_rpm(struct device *dev, struct device_attribute *attr, 564 char *buf) 565 { 566 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 567 int index = sensor_attr->index; 568 int rpm; 569 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 570 571 rpm = aspeed_get_fan_tach_ch_rpm(priv, index); 572 if (rpm < 0) 573 return rpm; 574 575 return sprintf(buf, "%d\n", rpm); 576 } 577 578 static umode_t pwm_is_visible(struct kobject *kobj, 579 struct attribute *a, int index) 580 { 581 struct device *dev = container_of(kobj, struct device, kobj); 582 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 583 584 if (!priv->pwm_present[index]) 585 return 0; 586 return a->mode; 587 } 588 589 static umode_t fan_dev_is_visible(struct kobject *kobj, 590 struct attribute *a, int index) 591 { 592 struct device *dev = container_of(kobj, struct device, kobj); 593 struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev); 594 595 if (!priv->fan_tach_present[index]) 596 return 0; 597 return a->mode; 598 } 599 600 static SENSOR_DEVICE_ATTR(pwm1, 0644, 601 show_pwm, set_pwm, 0); 602 static SENSOR_DEVICE_ATTR(pwm2, 0644, 603 show_pwm, set_pwm, 1); 604 static SENSOR_DEVICE_ATTR(pwm3, 0644, 605 show_pwm, set_pwm, 2); 606 static SENSOR_DEVICE_ATTR(pwm4, 0644, 607 show_pwm, set_pwm, 3); 608 static SENSOR_DEVICE_ATTR(pwm5, 0644, 609 show_pwm, set_pwm, 4); 610 static SENSOR_DEVICE_ATTR(pwm6, 0644, 611 show_pwm, set_pwm, 5); 612 static SENSOR_DEVICE_ATTR(pwm7, 0644, 613 show_pwm, set_pwm, 6); 614 static SENSOR_DEVICE_ATTR(pwm8, 0644, 615 show_pwm, set_pwm, 7); 616 static struct attribute *pwm_dev_attrs[] = { 617 &sensor_dev_attr_pwm1.dev_attr.attr, 618 &sensor_dev_attr_pwm2.dev_attr.attr, 619 &sensor_dev_attr_pwm3.dev_attr.attr, 620 &sensor_dev_attr_pwm4.dev_attr.attr, 621 &sensor_dev_attr_pwm5.dev_attr.attr, 622 &sensor_dev_attr_pwm6.dev_attr.attr, 623 &sensor_dev_attr_pwm7.dev_attr.attr, 624 &sensor_dev_attr_pwm8.dev_attr.attr, 625 NULL, 626 }; 627 628 static const struct attribute_group pwm_dev_group = { 629 .attrs = pwm_dev_attrs, 630 .is_visible = pwm_is_visible, 631 }; 632 633 static SENSOR_DEVICE_ATTR(fan1_input, 0444, 634 show_rpm, NULL, 0); 635 static SENSOR_DEVICE_ATTR(fan2_input, 0444, 636 show_rpm, NULL, 1); 637 static SENSOR_DEVICE_ATTR(fan3_input, 0444, 638 show_rpm, NULL, 2); 639 static SENSOR_DEVICE_ATTR(fan4_input, 0444, 640 show_rpm, NULL, 3); 641 static SENSOR_DEVICE_ATTR(fan5_input, 0444, 642 show_rpm, NULL, 4); 643 static SENSOR_DEVICE_ATTR(fan6_input, 0444, 644 show_rpm, NULL, 5); 645 static SENSOR_DEVICE_ATTR(fan7_input, 0444, 646 show_rpm, NULL, 6); 647 static SENSOR_DEVICE_ATTR(fan8_input, 0444, 648 show_rpm, NULL, 7); 649 static SENSOR_DEVICE_ATTR(fan9_input, 0444, 650 show_rpm, NULL, 8); 651 static SENSOR_DEVICE_ATTR(fan10_input, 0444, 652 show_rpm, NULL, 9); 653 static SENSOR_DEVICE_ATTR(fan11_input, 0444, 654 show_rpm, NULL, 10); 655 static SENSOR_DEVICE_ATTR(fan12_input, 0444, 656 show_rpm, NULL, 11); 657 static SENSOR_DEVICE_ATTR(fan13_input, 0444, 658 show_rpm, NULL, 12); 659 static SENSOR_DEVICE_ATTR(fan14_input, 0444, 660 show_rpm, NULL, 13); 661 static SENSOR_DEVICE_ATTR(fan15_input, 0444, 662 show_rpm, NULL, 14); 663 static SENSOR_DEVICE_ATTR(fan16_input, 0444, 664 show_rpm, NULL, 15); 665 static struct attribute *fan_dev_attrs[] = { 666 &sensor_dev_attr_fan1_input.dev_attr.attr, 667 &sensor_dev_attr_fan2_input.dev_attr.attr, 668 &sensor_dev_attr_fan3_input.dev_attr.attr, 669 &sensor_dev_attr_fan4_input.dev_attr.attr, 670 &sensor_dev_attr_fan5_input.dev_attr.attr, 671 &sensor_dev_attr_fan6_input.dev_attr.attr, 672 &sensor_dev_attr_fan7_input.dev_attr.attr, 673 &sensor_dev_attr_fan8_input.dev_attr.attr, 674 &sensor_dev_attr_fan9_input.dev_attr.attr, 675 &sensor_dev_attr_fan10_input.dev_attr.attr, 676 &sensor_dev_attr_fan11_input.dev_attr.attr, 677 &sensor_dev_attr_fan12_input.dev_attr.attr, 678 &sensor_dev_attr_fan13_input.dev_attr.attr, 679 &sensor_dev_attr_fan14_input.dev_attr.attr, 680 &sensor_dev_attr_fan15_input.dev_attr.attr, 681 &sensor_dev_attr_fan16_input.dev_attr.attr, 682 NULL 683 }; 684 685 static const struct attribute_group fan_dev_group = { 686 .attrs = fan_dev_attrs, 687 .is_visible = fan_dev_is_visible, 688 }; 689 690 /* 691 * The clock type is type M : 692 * The PWM frequency = 24MHz / (type M clock division L bit * 693 * type M clock division H bit * (type M PWM period bit + 1)) 694 */ 695 static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv) 696 { 697 priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H; 698 priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L; 699 priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD; 700 aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H, 701 M_PWM_DIV_L, M_PWM_PERIOD); 702 aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true); 703 priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV; 704 priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT; 705 aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE, 706 M_TACH_UNIT, M_TACH_CLK_DIV); 707 } 708 709 static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv, 710 u8 pwm_port) 711 { 712 aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true); 713 priv->pwm_present[pwm_port] = true; 714 715 priv->pwm_port_type[pwm_port] = TYPEM; 716 aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM); 717 718 priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL; 719 aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL); 720 } 721 722 static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tacho_data *priv, 723 u8 *fan_tach_ch, 724 int count, 725 u8 pwm_source) 726 { 727 u8 val, index; 728 729 for (val = 0; val < count; val++) { 730 index = fan_tach_ch[val]; 731 aspeed_set_fan_tach_ch_enable(priv->regmap, index, true); 732 priv->fan_tach_present[index] = true; 733 priv->fan_tach_ch_source[index] = pwm_source; 734 aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source); 735 } 736 } 737 738 static int aspeed_create_fan(struct device *dev, 739 struct device_node *child, 740 struct aspeed_pwm_tacho_data *priv) 741 { 742 u8 *fan_tach_ch; 743 u32 pwm_port; 744 int ret, count; 745 746 ret = of_property_read_u32(child, "reg", &pwm_port); 747 if (ret) 748 return ret; 749 aspeed_create_pwm_port(priv, (u8)pwm_port); 750 751 count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch"); 752 if (count < 1) 753 return -EINVAL; 754 fan_tach_ch = devm_kzalloc(dev, sizeof(*fan_tach_ch) * count, 755 GFP_KERNEL); 756 if (!fan_tach_ch) 757 return -ENOMEM; 758 ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch", 759 fan_tach_ch, count); 760 if (ret) 761 return ret; 762 aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, pwm_port); 763 764 return 0; 765 } 766 767 static int aspeed_pwm_tacho_probe(struct platform_device *pdev) 768 { 769 struct device *dev = &pdev->dev; 770 struct device_node *np, *child; 771 struct aspeed_pwm_tacho_data *priv; 772 void __iomem *regs; 773 struct resource *res; 774 struct device *hwmon; 775 struct clk *clk; 776 int ret; 777 778 np = dev->of_node; 779 780 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 781 if (!res) 782 return -ENOENT; 783 regs = devm_ioremap_resource(dev, res); 784 if (IS_ERR(regs)) 785 return PTR_ERR(regs); 786 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 787 if (!priv) 788 return -ENOMEM; 789 priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs, 790 &aspeed_pwm_tacho_regmap_config); 791 if (IS_ERR(priv->regmap)) 792 return PTR_ERR(priv->regmap); 793 regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0); 794 regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0); 795 796 clk = devm_clk_get(dev, NULL); 797 if (IS_ERR(clk)) 798 return -ENODEV; 799 priv->clk_freq = clk_get_rate(clk); 800 aspeed_set_clock_enable(priv->regmap, true); 801 aspeed_set_clock_source(priv->regmap, 0); 802 803 aspeed_create_type(priv); 804 805 for_each_child_of_node(np, child) { 806 ret = aspeed_create_fan(dev, child, priv); 807 of_node_put(child); 808 if (ret) 809 return ret; 810 } 811 812 priv->groups[0] = &pwm_dev_group; 813 priv->groups[1] = &fan_dev_group; 814 priv->groups[2] = NULL; 815 hwmon = devm_hwmon_device_register_with_groups(dev, 816 "aspeed_pwm_tacho", 817 priv, priv->groups); 818 return PTR_ERR_OR_ZERO(hwmon); 819 } 820 821 static const struct of_device_id of_pwm_tacho_match_table[] = { 822 { .compatible = "aspeed,ast2400-pwm-tacho", }, 823 { .compatible = "aspeed,ast2500-pwm-tacho", }, 824 {}, 825 }; 826 MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table); 827 828 static struct platform_driver aspeed_pwm_tacho_driver = { 829 .probe = aspeed_pwm_tacho_probe, 830 .driver = { 831 .name = "aspeed_pwm_tacho", 832 .of_match_table = of_pwm_tacho_match_table, 833 }, 834 }; 835 836 module_platform_driver(aspeed_pwm_tacho_driver); 837 838 MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>"); 839 MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver"); 840 MODULE_LICENSE("GPL"); 841