1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (c) 2016 Google, Inc
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/errno.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/hwmon.h>
11 #include <linux/hwmon-sysfs.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/of_platform.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/reset.h>
20 #include <linux/sysfs.h>
21 #include <linux/thermal.h>
22 
23 /* ASPEED PWM & FAN Tach Register Definition */
24 #define ASPEED_PTCR_CTRL		0x00
25 #define ASPEED_PTCR_CLK_CTRL		0x04
26 #define ASPEED_PTCR_DUTY0_CTRL		0x08
27 #define ASPEED_PTCR_DUTY1_CTRL		0x0c
28 #define ASPEED_PTCR_TYPEM_CTRL		0x10
29 #define ASPEED_PTCR_TYPEM_CTRL1		0x14
30 #define ASPEED_PTCR_TYPEN_CTRL		0x18
31 #define ASPEED_PTCR_TYPEN_CTRL1		0x1c
32 #define ASPEED_PTCR_TACH_SOURCE		0x20
33 #define ASPEED_PTCR_TRIGGER		0x28
34 #define ASPEED_PTCR_RESULT		0x2c
35 #define ASPEED_PTCR_INTR_CTRL		0x30
36 #define ASPEED_PTCR_INTR_STS		0x34
37 #define ASPEED_PTCR_TYPEM_LIMIT		0x38
38 #define ASPEED_PTCR_TYPEN_LIMIT		0x3C
39 #define ASPEED_PTCR_CTRL_EXT		0x40
40 #define ASPEED_PTCR_CLK_CTRL_EXT	0x44
41 #define ASPEED_PTCR_DUTY2_CTRL		0x48
42 #define ASPEED_PTCR_DUTY3_CTRL		0x4c
43 #define ASPEED_PTCR_TYPEO_CTRL		0x50
44 #define ASPEED_PTCR_TYPEO_CTRL1		0x54
45 #define ASPEED_PTCR_TACH_SOURCE_EXT	0x60
46 #define ASPEED_PTCR_TYPEO_LIMIT		0x78
47 
48 /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */
49 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1	15
50 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2	6
51 #define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK	(BIT(7) | BIT(15))
52 
53 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1	14
54 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2	5
55 #define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK	(BIT(6) | BIT(14))
56 
57 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1	13
58 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2	4
59 #define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK	(BIT(5) | BIT(13))
60 
61 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1	12
62 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2	3
63 #define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK	(BIT(4) | BIT(12))
64 
65 #define	ASPEED_PTCR_CTRL_FAN_NUM_EN(x)	BIT(16 + (x))
66 
67 #define	ASPEED_PTCR_CTRL_PWMD_EN	BIT(11)
68 #define	ASPEED_PTCR_CTRL_PWMC_EN	BIT(10)
69 #define	ASPEED_PTCR_CTRL_PWMB_EN	BIT(9)
70 #define	ASPEED_PTCR_CTRL_PWMA_EN	BIT(8)
71 
72 #define	ASPEED_PTCR_CTRL_CLK_SRC	BIT(1)
73 #define	ASPEED_PTCR_CTRL_CLK_EN		BIT(0)
74 
75 /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */
76 /* TYPE N */
77 #define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK		GENMASK(31, 16)
78 #define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT		24
79 #define ASPEED_PTCR_CLK_CTRL_TYPEN_H		20
80 #define ASPEED_PTCR_CLK_CTRL_TYPEN_L		16
81 /* TYPE M */
82 #define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK         GENMASK(15, 0)
83 #define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT		8
84 #define ASPEED_PTCR_CLK_CTRL_TYPEM_H		4
85 #define ASPEED_PTCR_CLK_CTRL_TYPEM_L		0
86 
87 /*
88  * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control
89  * 0/1/2/3 register
90  */
91 #define DUTY_CTRL_PWM2_FALL_POINT	24
92 #define DUTY_CTRL_PWM2_RISE_POINT	16
93 #define DUTY_CTRL_PWM2_RISE_FALL_MASK	GENMASK(31, 16)
94 #define DUTY_CTRL_PWM1_FALL_POINT	8
95 #define DUTY_CTRL_PWM1_RISE_POINT	0
96 #define DUTY_CTRL_PWM1_RISE_FALL_MASK   GENMASK(15, 0)
97 
98 /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */
99 #define TYPE_CTRL_FAN_MASK		(GENMASK(5, 1) | GENMASK(31, 16))
100 #define TYPE_CTRL_FAN1_MASK		GENMASK(31, 0)
101 #define TYPE_CTRL_FAN_PERIOD		16
102 #define TYPE_CTRL_FAN_MODE		4
103 #define TYPE_CTRL_FAN_DIVISION		1
104 #define TYPE_CTRL_FAN_TYPE_EN		1
105 
106 /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */
107 /* bit [0,1] at 0x20, bit [2] at 0x60 */
108 #define TACH_PWM_SOURCE_BIT01(x)	((x) * 2)
109 #define TACH_PWM_SOURCE_BIT2(x)		((x) * 2)
110 #define TACH_PWM_SOURCE_MASK_BIT01(x)	(0x3 << ((x) * 2))
111 #define TACH_PWM_SOURCE_MASK_BIT2(x)	BIT((x) * 2)
112 
113 /* ASPEED_PTCR_RESULT : 0x2c - Result Register */
114 #define RESULT_STATUS_MASK		BIT(31)
115 #define RESULT_VALUE_MASK		0xfffff
116 
117 /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */
118 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1	15
119 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2	6
120 #define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK	(BIT(7) | BIT(15))
121 
122 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1	14
123 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2	5
124 #define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK	(BIT(6) | BIT(14))
125 
126 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1	13
127 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2	4
128 #define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK	(BIT(5) | BIT(13))
129 
130 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1	12
131 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2	3
132 #define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK	(BIT(4) | BIT(12))
133 
134 #define	ASPEED_PTCR_CTRL_PWMH_EN	BIT(11)
135 #define	ASPEED_PTCR_CTRL_PWMG_EN	BIT(10)
136 #define	ASPEED_PTCR_CTRL_PWMF_EN	BIT(9)
137 #define	ASPEED_PTCR_CTRL_PWME_EN	BIT(8)
138 
139 /* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */
140 /* TYPE O */
141 #define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK         GENMASK(15, 0)
142 #define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT		8
143 #define ASPEED_PTCR_CLK_CTRL_TYPEO_H		4
144 #define ASPEED_PTCR_CLK_CTRL_TYPEO_L		0
145 
146 #define PWM_MAX 255
147 
148 #define BOTH_EDGES 0x02 /* 10b */
149 
150 #define M_PWM_DIV_H 0x00
151 #define M_PWM_DIV_L 0x05
152 #define M_PWM_PERIOD 0x5F
153 #define M_TACH_CLK_DIV 0x00
154 /*
155  * 5:4 Type N fan tach mode selection bit:
156  * 00: falling
157  * 01: rising
158  * 10: both
159  * 11: reserved.
160  */
161 #define M_TACH_MODE 0x02 /* 10b */
162 #define M_TACH_UNIT 0x0210
163 #define INIT_FAN_CTRL 0xFF
164 
165 /* How long we sleep in us while waiting for an RPM result. */
166 #define ASPEED_RPM_STATUS_SLEEP_USEC	500
167 
168 #define MAX_CDEV_NAME_LEN 16
169 
170 struct aspeed_cooling_device {
171 	char name[16];
172 	struct aspeed_pwm_tacho_data *priv;
173 	struct thermal_cooling_device *tcdev;
174 	int pwm_port;
175 	u8 *cooling_levels;
176 	u8 max_state;
177 	u8 cur_state;
178 };
179 
180 struct aspeed_pwm_tacho_data {
181 	struct regmap *regmap;
182 	struct reset_control *rst;
183 	unsigned long clk_freq;
184 	bool pwm_present[8];
185 	bool fan_tach_present[16];
186 	u8 type_pwm_clock_unit[3];
187 	u8 type_pwm_clock_division_h[3];
188 	u8 type_pwm_clock_division_l[3];
189 	u8 type_fan_tach_clock_division[3];
190 	u8 type_fan_tach_mode[3];
191 	u16 type_fan_tach_unit[3];
192 	u8 pwm_port_type[8];
193 	u8 pwm_port_fan_ctrl[8];
194 	u8 fan_tach_ch_source[16];
195 	struct aspeed_cooling_device *cdev[8];
196 	const struct attribute_group *groups[3];
197 };
198 
199 enum type { TYPEM, TYPEN, TYPEO };
200 
201 struct type_params {
202 	u32 l_value;
203 	u32 h_value;
204 	u32 unit_value;
205 	u32 clk_ctrl_mask;
206 	u32 clk_ctrl_reg;
207 	u32 ctrl_reg;
208 	u32 ctrl_reg1;
209 };
210 
211 static const struct type_params type_params[] = {
212 	[TYPEM] = {
213 		.l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L,
214 		.h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H,
215 		.unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT,
216 		.clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK,
217 		.clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
218 		.ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
219 		.ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1,
220 	},
221 	[TYPEN] = {
222 		.l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L,
223 		.h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H,
224 		.unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT,
225 		.clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK,
226 		.clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
227 		.ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
228 		.ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1,
229 	},
230 	[TYPEO] = {
231 		.l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L,
232 		.h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H,
233 		.unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT,
234 		.clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK,
235 		.clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT,
236 		.ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
237 		.ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1,
238 	}
239 };
240 
241 enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH };
242 
243 struct pwm_port_params {
244 	u32 pwm_en;
245 	u32 ctrl_reg;
246 	u32 type_part1;
247 	u32 type_part2;
248 	u32 type_mask;
249 	u32 duty_ctrl_rise_point;
250 	u32 duty_ctrl_fall_point;
251 	u32 duty_ctrl_reg;
252 	u32 duty_ctrl_rise_fall_mask;
253 };
254 
255 static const struct pwm_port_params pwm_port_params[] = {
256 	[PWMA] = {
257 		.pwm_en = ASPEED_PTCR_CTRL_PWMA_EN,
258 		.ctrl_reg = ASPEED_PTCR_CTRL,
259 		.type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1,
260 		.type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2,
261 		.type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK,
262 		.duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
263 		.duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
264 		.duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
265 		.duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
266 	},
267 	[PWMB] = {
268 		.pwm_en = ASPEED_PTCR_CTRL_PWMB_EN,
269 		.ctrl_reg = ASPEED_PTCR_CTRL,
270 		.type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1,
271 		.type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2,
272 		.type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK,
273 		.duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
274 		.duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
275 		.duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
276 		.duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
277 	},
278 	[PWMC] = {
279 		.pwm_en = ASPEED_PTCR_CTRL_PWMC_EN,
280 		.ctrl_reg = ASPEED_PTCR_CTRL,
281 		.type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1,
282 		.type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2,
283 		.type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK,
284 		.duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
285 		.duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
286 		.duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
287 		.duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
288 	},
289 	[PWMD] = {
290 		.pwm_en = ASPEED_PTCR_CTRL_PWMD_EN,
291 		.ctrl_reg = ASPEED_PTCR_CTRL,
292 		.type_part1 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1,
293 		.type_part2 = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2,
294 		.type_mask = ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK,
295 		.duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
296 		.duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
297 		.duty_ctrl_reg = ASPEED_PTCR_DUTY1_CTRL,
298 		.duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
299 	},
300 	[PWME] = {
301 		.pwm_en = ASPEED_PTCR_CTRL_PWME_EN,
302 		.ctrl_reg = ASPEED_PTCR_CTRL_EXT,
303 		.type_part1 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1,
304 		.type_part2 = ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2,
305 		.type_mask = ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK,
306 		.duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
307 		.duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
308 		.duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
309 		.duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
310 	},
311 	[PWMF] = {
312 		.pwm_en = ASPEED_PTCR_CTRL_PWMF_EN,
313 		.ctrl_reg = ASPEED_PTCR_CTRL_EXT,
314 		.type_part1 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1,
315 		.type_part2 = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2,
316 		.type_mask = ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK,
317 		.duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
318 		.duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
319 		.duty_ctrl_reg = ASPEED_PTCR_DUTY2_CTRL,
320 		.duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
321 	},
322 	[PWMG] = {
323 		.pwm_en = ASPEED_PTCR_CTRL_PWMG_EN,
324 		.ctrl_reg = ASPEED_PTCR_CTRL_EXT,
325 		.type_part1 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1,
326 		.type_part2 = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2,
327 		.type_mask = ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK,
328 		.duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
329 		.duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
330 		.duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
331 		.duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
332 	},
333 	[PWMH] = {
334 		.pwm_en = ASPEED_PTCR_CTRL_PWMH_EN,
335 		.ctrl_reg = ASPEED_PTCR_CTRL_EXT,
336 		.type_part1 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1,
337 		.type_part2 = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2,
338 		.type_mask = ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK,
339 		.duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
340 		.duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
341 		.duty_ctrl_reg = ASPEED_PTCR_DUTY3_CTRL,
342 		.duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
343 	}
344 };
345 
346 static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg,
347 					     unsigned int val)
348 {
349 	void __iomem *regs = (void __iomem *)context;
350 
351 	writel(val, regs + reg);
352 	return 0;
353 }
354 
355 static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg,
356 					    unsigned int *val)
357 {
358 	void __iomem *regs = (void __iomem *)context;
359 
360 	*val = readl(regs + reg);
361 	return 0;
362 }
363 
364 static const struct regmap_config aspeed_pwm_tacho_regmap_config = {
365 	.reg_bits = 32,
366 	.val_bits = 32,
367 	.reg_stride = 4,
368 	.max_register = ASPEED_PTCR_TYPEO_LIMIT,
369 	.reg_write = regmap_aspeed_pwm_tacho_reg_write,
370 	.reg_read = regmap_aspeed_pwm_tacho_reg_read,
371 	.fast_io = true,
372 };
373 
374 static void aspeed_set_clock_enable(struct regmap *regmap, bool val)
375 {
376 	regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
377 			   ASPEED_PTCR_CTRL_CLK_EN,
378 			   val ? ASPEED_PTCR_CTRL_CLK_EN : 0);
379 }
380 
381 static void aspeed_set_clock_source(struct regmap *regmap, int val)
382 {
383 	regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
384 			   ASPEED_PTCR_CTRL_CLK_SRC,
385 			   val ? ASPEED_PTCR_CTRL_CLK_SRC : 0);
386 }
387 
388 static void aspeed_set_pwm_clock_values(struct regmap *regmap, u8 type,
389 					u8 div_high, u8 div_low, u8 unit)
390 {
391 	u32 reg_value = ((div_high << type_params[type].h_value) |
392 			 (div_low << type_params[type].l_value) |
393 			 (unit << type_params[type].unit_value));
394 
395 	regmap_update_bits(regmap, type_params[type].clk_ctrl_reg,
396 			   type_params[type].clk_ctrl_mask, reg_value);
397 }
398 
399 static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port,
400 				       bool enable)
401 {
402 	regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
403 			   pwm_port_params[pwm_port].pwm_en,
404 			   enable ? pwm_port_params[pwm_port].pwm_en : 0);
405 }
406 
407 static void aspeed_set_pwm_port_type(struct regmap *regmap,
408 				     u8 pwm_port, u8 type)
409 {
410 	u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1;
411 
412 	reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2;
413 
414 	regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
415 			   pwm_port_params[pwm_port].type_mask, reg_value);
416 }
417 
418 static void aspeed_set_pwm_port_duty_rising_falling(struct regmap *regmap,
419 						    u8 pwm_port, u8 rising,
420 						    u8 falling)
421 {
422 	u32 reg_value = (rising <<
423 			 pwm_port_params[pwm_port].duty_ctrl_rise_point);
424 	reg_value |= (falling <<
425 		      pwm_port_params[pwm_port].duty_ctrl_fall_point);
426 
427 	regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg,
428 			   pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask,
429 			   reg_value);
430 }
431 
432 static void aspeed_set_tacho_type_enable(struct regmap *regmap, u8 type,
433 					 bool enable)
434 {
435 	regmap_update_bits(regmap, type_params[type].ctrl_reg,
436 			   TYPE_CTRL_FAN_TYPE_EN,
437 			   enable ? TYPE_CTRL_FAN_TYPE_EN : 0);
438 }
439 
440 static void aspeed_set_tacho_type_values(struct regmap *regmap, u8 type,
441 					 u8 mode, u16 unit, u8 division)
442 {
443 	u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) |
444 			 (unit << TYPE_CTRL_FAN_PERIOD) |
445 			 (division << TYPE_CTRL_FAN_DIVISION));
446 
447 	regmap_update_bits(regmap, type_params[type].ctrl_reg,
448 			   TYPE_CTRL_FAN_MASK, reg_value);
449 	regmap_update_bits(regmap, type_params[type].ctrl_reg1,
450 			   TYPE_CTRL_FAN1_MASK, unit << 16);
451 }
452 
453 static void aspeed_set_fan_tach_ch_enable(struct regmap *regmap, u8 fan_tach_ch,
454 					  bool enable)
455 {
456 	regmap_update_bits(regmap, ASPEED_PTCR_CTRL,
457 			   ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch),
458 			   enable ?
459 			   ASPEED_PTCR_CTRL_FAN_NUM_EN(fan_tach_ch) : 0);
460 }
461 
462 static void aspeed_set_fan_tach_ch_source(struct regmap *regmap, u8 fan_tach_ch,
463 					  u8 fan_tach_ch_source)
464 {
465 	u32 reg_value1 = ((fan_tach_ch_source & 0x3) <<
466 			  TACH_PWM_SOURCE_BIT01(fan_tach_ch));
467 	u32 reg_value2 = (((fan_tach_ch_source & 0x4) >> 2) <<
468 			  TACH_PWM_SOURCE_BIT2(fan_tach_ch));
469 
470 	regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE,
471 			   TACH_PWM_SOURCE_MASK_BIT01(fan_tach_ch),
472 			   reg_value1);
473 
474 	regmap_update_bits(regmap, ASPEED_PTCR_TACH_SOURCE_EXT,
475 			   TACH_PWM_SOURCE_MASK_BIT2(fan_tach_ch),
476 			   reg_value2);
477 }
478 
479 static void aspeed_set_pwm_port_fan_ctrl(struct aspeed_pwm_tacho_data *priv,
480 					 u8 index, u8 fan_ctrl)
481 {
482 	u16 period, dc_time_on;
483 
484 	period = priv->type_pwm_clock_unit[priv->pwm_port_type[index]];
485 	period += 1;
486 	dc_time_on = (fan_ctrl * period) / PWM_MAX;
487 
488 	if (dc_time_on == 0) {
489 		aspeed_set_pwm_port_enable(priv->regmap, index, false);
490 	} else {
491 		if (dc_time_on == period)
492 			dc_time_on = 0;
493 
494 		aspeed_set_pwm_port_duty_rising_falling(priv->regmap, index, 0,
495 							dc_time_on);
496 		aspeed_set_pwm_port_enable(priv->regmap, index, true);
497 	}
498 }
499 
500 static u32 aspeed_get_fan_tach_ch_measure_period(struct aspeed_pwm_tacho_data
501 						 *priv, u8 type)
502 {
503 	u32 clk;
504 	u16 tacho_unit;
505 	u8 clk_unit, div_h, div_l, tacho_div;
506 
507 	clk = priv->clk_freq;
508 	clk_unit = priv->type_pwm_clock_unit[type];
509 	div_h = priv->type_pwm_clock_division_h[type];
510 	div_h = 0x1 << div_h;
511 	div_l = priv->type_pwm_clock_division_l[type];
512 	if (div_l == 0)
513 		div_l = 1;
514 	else
515 		div_l = div_l * 2;
516 
517 	tacho_unit = priv->type_fan_tach_unit[type];
518 	tacho_div = priv->type_fan_tach_clock_division[type];
519 
520 	tacho_div = 0x4 << (tacho_div * 2);
521 	return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit);
522 }
523 
524 static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tacho_data *priv,
525 				      u8 fan_tach_ch)
526 {
527 	u32 raw_data, tach_div, clk_source, msec, usec, val;
528 	u8 fan_tach_ch_source, type, mode, both;
529 	int ret;
530 
531 	regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0);
532 	regmap_write(priv->regmap, ASPEED_PTCR_TRIGGER, 0x1 << fan_tach_ch);
533 
534 	fan_tach_ch_source = priv->fan_tach_ch_source[fan_tach_ch];
535 	type = priv->pwm_port_type[fan_tach_ch_source];
536 
537 	msec = (1000 / aspeed_get_fan_tach_ch_measure_period(priv, type));
538 	usec = msec * 1000;
539 
540 	ret = regmap_read_poll_timeout(
541 		priv->regmap,
542 		ASPEED_PTCR_RESULT,
543 		val,
544 		(val & RESULT_STATUS_MASK),
545 		ASPEED_RPM_STATUS_SLEEP_USEC,
546 		usec);
547 
548 	/* return -ETIMEDOUT if we didn't get an answer. */
549 	if (ret)
550 		return ret;
551 
552 	raw_data = val & RESULT_VALUE_MASK;
553 	tach_div = priv->type_fan_tach_clock_division[type];
554 	/*
555 	 * We need the mode to determine if the raw_data is double (from
556 	 * counting both edges).
557 	 */
558 	mode = priv->type_fan_tach_mode[type];
559 	both = (mode & BOTH_EDGES) ? 1 : 0;
560 
561 	tach_div = (0x4 << both) << (tach_div * 2);
562 	clk_source = priv->clk_freq;
563 
564 	if (raw_data == 0)
565 		return 0;
566 
567 	return (clk_source * 60) / (2 * raw_data * tach_div);
568 }
569 
570 static ssize_t pwm_store(struct device *dev, struct device_attribute *attr,
571 			 const char *buf, size_t count)
572 {
573 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
574 	int index = sensor_attr->index;
575 	int ret;
576 	struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
577 	long fan_ctrl;
578 
579 	ret = kstrtol(buf, 10, &fan_ctrl);
580 	if (ret != 0)
581 		return ret;
582 
583 	if (fan_ctrl < 0 || fan_ctrl > PWM_MAX)
584 		return -EINVAL;
585 
586 	if (priv->pwm_port_fan_ctrl[index] == fan_ctrl)
587 		return count;
588 
589 	priv->pwm_port_fan_ctrl[index] = fan_ctrl;
590 	aspeed_set_pwm_port_fan_ctrl(priv, index, fan_ctrl);
591 
592 	return count;
593 }
594 
595 static ssize_t pwm_show(struct device *dev, struct device_attribute *attr,
596 			char *buf)
597 {
598 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
599 	int index = sensor_attr->index;
600 	struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
601 
602 	return sprintf(buf, "%u\n", priv->pwm_port_fan_ctrl[index]);
603 }
604 
605 static ssize_t rpm_show(struct device *dev, struct device_attribute *attr,
606 			char *buf)
607 {
608 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
609 	int index = sensor_attr->index;
610 	int rpm;
611 	struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
612 
613 	rpm = aspeed_get_fan_tach_ch_rpm(priv, index);
614 	if (rpm < 0)
615 		return rpm;
616 
617 	return sprintf(buf, "%d\n", rpm);
618 }
619 
620 static umode_t pwm_is_visible(struct kobject *kobj,
621 			      struct attribute *a, int index)
622 {
623 	struct device *dev = container_of(kobj, struct device, kobj);
624 	struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
625 
626 	if (!priv->pwm_present[index])
627 		return 0;
628 	return a->mode;
629 }
630 
631 static umode_t fan_dev_is_visible(struct kobject *kobj,
632 				  struct attribute *a, int index)
633 {
634 	struct device *dev = container_of(kobj, struct device, kobj);
635 	struct aspeed_pwm_tacho_data *priv = dev_get_drvdata(dev);
636 
637 	if (!priv->fan_tach_present[index])
638 		return 0;
639 	return a->mode;
640 }
641 
642 static SENSOR_DEVICE_ATTR_RW(pwm1, pwm, 0);
643 static SENSOR_DEVICE_ATTR_RW(pwm2, pwm, 1);
644 static SENSOR_DEVICE_ATTR_RW(pwm3, pwm, 2);
645 static SENSOR_DEVICE_ATTR_RW(pwm4, pwm, 3);
646 static SENSOR_DEVICE_ATTR_RW(pwm5, pwm, 4);
647 static SENSOR_DEVICE_ATTR_RW(pwm6, pwm, 5);
648 static SENSOR_DEVICE_ATTR_RW(pwm7, pwm, 6);
649 static SENSOR_DEVICE_ATTR_RW(pwm8, pwm, 7);
650 static struct attribute *pwm_dev_attrs[] = {
651 	&sensor_dev_attr_pwm1.dev_attr.attr,
652 	&sensor_dev_attr_pwm2.dev_attr.attr,
653 	&sensor_dev_attr_pwm3.dev_attr.attr,
654 	&sensor_dev_attr_pwm4.dev_attr.attr,
655 	&sensor_dev_attr_pwm5.dev_attr.attr,
656 	&sensor_dev_attr_pwm6.dev_attr.attr,
657 	&sensor_dev_attr_pwm7.dev_attr.attr,
658 	&sensor_dev_attr_pwm8.dev_attr.attr,
659 	NULL,
660 };
661 
662 static const struct attribute_group pwm_dev_group = {
663 	.attrs = pwm_dev_attrs,
664 	.is_visible = pwm_is_visible,
665 };
666 
667 static SENSOR_DEVICE_ATTR_RO(fan1_input, rpm, 0);
668 static SENSOR_DEVICE_ATTR_RO(fan2_input, rpm, 1);
669 static SENSOR_DEVICE_ATTR_RO(fan3_input, rpm, 2);
670 static SENSOR_DEVICE_ATTR_RO(fan4_input, rpm, 3);
671 static SENSOR_DEVICE_ATTR_RO(fan5_input, rpm, 4);
672 static SENSOR_DEVICE_ATTR_RO(fan6_input, rpm, 5);
673 static SENSOR_DEVICE_ATTR_RO(fan7_input, rpm, 6);
674 static SENSOR_DEVICE_ATTR_RO(fan8_input, rpm, 7);
675 static SENSOR_DEVICE_ATTR_RO(fan9_input, rpm, 8);
676 static SENSOR_DEVICE_ATTR_RO(fan10_input, rpm, 9);
677 static SENSOR_DEVICE_ATTR_RO(fan11_input, rpm, 10);
678 static SENSOR_DEVICE_ATTR_RO(fan12_input, rpm, 11);
679 static SENSOR_DEVICE_ATTR_RO(fan13_input, rpm, 12);
680 static SENSOR_DEVICE_ATTR_RO(fan14_input, rpm, 13);
681 static SENSOR_DEVICE_ATTR_RO(fan15_input, rpm, 14);
682 static SENSOR_DEVICE_ATTR_RO(fan16_input, rpm, 15);
683 static struct attribute *fan_dev_attrs[] = {
684 	&sensor_dev_attr_fan1_input.dev_attr.attr,
685 	&sensor_dev_attr_fan2_input.dev_attr.attr,
686 	&sensor_dev_attr_fan3_input.dev_attr.attr,
687 	&sensor_dev_attr_fan4_input.dev_attr.attr,
688 	&sensor_dev_attr_fan5_input.dev_attr.attr,
689 	&sensor_dev_attr_fan6_input.dev_attr.attr,
690 	&sensor_dev_attr_fan7_input.dev_attr.attr,
691 	&sensor_dev_attr_fan8_input.dev_attr.attr,
692 	&sensor_dev_attr_fan9_input.dev_attr.attr,
693 	&sensor_dev_attr_fan10_input.dev_attr.attr,
694 	&sensor_dev_attr_fan11_input.dev_attr.attr,
695 	&sensor_dev_attr_fan12_input.dev_attr.attr,
696 	&sensor_dev_attr_fan13_input.dev_attr.attr,
697 	&sensor_dev_attr_fan14_input.dev_attr.attr,
698 	&sensor_dev_attr_fan15_input.dev_attr.attr,
699 	&sensor_dev_attr_fan16_input.dev_attr.attr,
700 	NULL
701 };
702 
703 static const struct attribute_group fan_dev_group = {
704 	.attrs = fan_dev_attrs,
705 	.is_visible = fan_dev_is_visible,
706 };
707 
708 /*
709  * The clock type is type M :
710  * The PWM frequency = 24MHz / (type M clock division L bit *
711  * type M clock division H bit * (type M PWM period bit + 1))
712  */
713 static void aspeed_create_type(struct aspeed_pwm_tacho_data *priv)
714 {
715 	priv->type_pwm_clock_division_h[TYPEM] = M_PWM_DIV_H;
716 	priv->type_pwm_clock_division_l[TYPEM] = M_PWM_DIV_L;
717 	priv->type_pwm_clock_unit[TYPEM] = M_PWM_PERIOD;
718 	aspeed_set_pwm_clock_values(priv->regmap, TYPEM, M_PWM_DIV_H,
719 				    M_PWM_DIV_L, M_PWM_PERIOD);
720 	aspeed_set_tacho_type_enable(priv->regmap, TYPEM, true);
721 	priv->type_fan_tach_clock_division[TYPEM] = M_TACH_CLK_DIV;
722 	priv->type_fan_tach_unit[TYPEM] = M_TACH_UNIT;
723 	priv->type_fan_tach_mode[TYPEM] = M_TACH_MODE;
724 	aspeed_set_tacho_type_values(priv->regmap, TYPEM, M_TACH_MODE,
725 				     M_TACH_UNIT, M_TACH_CLK_DIV);
726 }
727 
728 static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv,
729 				   u8 pwm_port)
730 {
731 	aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true);
732 	priv->pwm_present[pwm_port] = true;
733 
734 	priv->pwm_port_type[pwm_port] = TYPEM;
735 	aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM);
736 
737 	priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL;
738 	aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL);
739 }
740 
741 static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tacho_data *priv,
742 					   u8 *fan_tach_ch,
743 					   int count,
744 					   u8 pwm_source)
745 {
746 	u8 val, index;
747 
748 	for (val = 0; val < count; val++) {
749 		index = fan_tach_ch[val];
750 		aspeed_set_fan_tach_ch_enable(priv->regmap, index, true);
751 		priv->fan_tach_present[index] = true;
752 		priv->fan_tach_ch_source[index] = pwm_source;
753 		aspeed_set_fan_tach_ch_source(priv->regmap, index, pwm_source);
754 	}
755 }
756 
757 static int
758 aspeed_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,
759 			    unsigned long *state)
760 {
761 	struct aspeed_cooling_device *cdev = tcdev->devdata;
762 
763 	*state = cdev->max_state;
764 
765 	return 0;
766 }
767 
768 static int
769 aspeed_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,
770 			    unsigned long *state)
771 {
772 	struct aspeed_cooling_device *cdev = tcdev->devdata;
773 
774 	*state = cdev->cur_state;
775 
776 	return 0;
777 }
778 
779 static int
780 aspeed_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,
781 			    unsigned long state)
782 {
783 	struct aspeed_cooling_device *cdev = tcdev->devdata;
784 
785 	if (state > cdev->max_state)
786 		return -EINVAL;
787 
788 	cdev->cur_state = state;
789 	cdev->priv->pwm_port_fan_ctrl[cdev->pwm_port] =
790 					cdev->cooling_levels[cdev->cur_state];
791 	aspeed_set_pwm_port_fan_ctrl(cdev->priv, cdev->pwm_port,
792 				     cdev->cooling_levels[cdev->cur_state]);
793 
794 	return 0;
795 }
796 
797 static const struct thermal_cooling_device_ops aspeed_pwm_cool_ops = {
798 	.get_max_state = aspeed_pwm_cz_get_max_state,
799 	.get_cur_state = aspeed_pwm_cz_get_cur_state,
800 	.set_cur_state = aspeed_pwm_cz_set_cur_state,
801 };
802 
803 static int aspeed_create_pwm_cooling(struct device *dev,
804 				     struct device_node *child,
805 				     struct aspeed_pwm_tacho_data *priv,
806 				     u32 pwm_port, u8 num_levels)
807 {
808 	int ret;
809 	struct aspeed_cooling_device *cdev;
810 
811 	cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
812 
813 	if (!cdev)
814 		return -ENOMEM;
815 
816 	cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);
817 	if (!cdev->cooling_levels)
818 		return -ENOMEM;
819 
820 	cdev->max_state = num_levels - 1;
821 	ret = of_property_read_u8_array(child, "cooling-levels",
822 					cdev->cooling_levels,
823 					num_levels);
824 	if (ret) {
825 		dev_err(dev, "Property 'cooling-levels' cannot be read.\n");
826 		return ret;
827 	}
828 	snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%pOFn%d", child, pwm_port);
829 
830 	cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child,
831 					cdev->name, cdev, &aspeed_pwm_cool_ops);
832 	if (IS_ERR(cdev->tcdev))
833 		return PTR_ERR(cdev->tcdev);
834 
835 	cdev->priv = priv;
836 	cdev->pwm_port = pwm_port;
837 
838 	priv->cdev[pwm_port] = cdev;
839 
840 	return 0;
841 }
842 
843 static int aspeed_create_fan(struct device *dev,
844 			     struct device_node *child,
845 			     struct aspeed_pwm_tacho_data *priv)
846 {
847 	u8 *fan_tach_ch;
848 	u32 pwm_port;
849 	int ret, count;
850 
851 	ret = of_property_read_u32(child, "reg", &pwm_port);
852 	if (ret)
853 		return ret;
854 	aspeed_create_pwm_port(priv, (u8)pwm_port);
855 
856 	ret = of_property_count_u8_elems(child, "cooling-levels");
857 
858 	if (ret > 0) {
859 		ret = aspeed_create_pwm_cooling(dev, child, priv, pwm_port,
860 						ret);
861 		if (ret)
862 			return ret;
863 	}
864 
865 	count = of_property_count_u8_elems(child, "aspeed,fan-tach-ch");
866 	if (count < 1)
867 		return -EINVAL;
868 	fan_tach_ch = devm_kcalloc(dev, count, sizeof(*fan_tach_ch),
869 				   GFP_KERNEL);
870 	if (!fan_tach_ch)
871 		return -ENOMEM;
872 	ret = of_property_read_u8_array(child, "aspeed,fan-tach-ch",
873 					fan_tach_ch, count);
874 	if (ret)
875 		return ret;
876 	aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, pwm_port);
877 
878 	return 0;
879 }
880 
881 static void aspeed_pwm_tacho_remove(void *data)
882 {
883 	struct aspeed_pwm_tacho_data *priv = data;
884 
885 	reset_control_assert(priv->rst);
886 }
887 
888 static int aspeed_pwm_tacho_probe(struct platform_device *pdev)
889 {
890 	struct device *dev = &pdev->dev;
891 	struct device_node *np, *child;
892 	struct aspeed_pwm_tacho_data *priv;
893 	void __iomem *regs;
894 	struct device *hwmon;
895 	struct clk *clk;
896 	int ret;
897 
898 	np = dev->of_node;
899 	regs = devm_platform_ioremap_resource(pdev, 0);
900 	if (IS_ERR(regs))
901 		return PTR_ERR(regs);
902 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
903 	if (!priv)
904 		return -ENOMEM;
905 	priv->regmap = devm_regmap_init(dev, NULL, (__force void *)regs,
906 			&aspeed_pwm_tacho_regmap_config);
907 	if (IS_ERR(priv->regmap))
908 		return PTR_ERR(priv->regmap);
909 
910 	priv->rst = devm_reset_control_get_exclusive(dev, NULL);
911 	if (IS_ERR(priv->rst)) {
912 		dev_err(dev,
913 			"missing or invalid reset controller device tree entry");
914 		return PTR_ERR(priv->rst);
915 	}
916 	reset_control_deassert(priv->rst);
917 
918 	ret = devm_add_action_or_reset(dev, aspeed_pwm_tacho_remove, priv);
919 	if (ret)
920 		return ret;
921 
922 	regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE, 0);
923 	regmap_write(priv->regmap, ASPEED_PTCR_TACH_SOURCE_EXT, 0);
924 
925 	clk = devm_clk_get(dev, NULL);
926 	if (IS_ERR(clk))
927 		return -ENODEV;
928 	priv->clk_freq = clk_get_rate(clk);
929 	aspeed_set_clock_enable(priv->regmap, true);
930 	aspeed_set_clock_source(priv->regmap, 0);
931 
932 	aspeed_create_type(priv);
933 
934 	for_each_child_of_node(np, child) {
935 		ret = aspeed_create_fan(dev, child, priv);
936 		if (ret) {
937 			of_node_put(child);
938 			return ret;
939 		}
940 	}
941 
942 	priv->groups[0] = &pwm_dev_group;
943 	priv->groups[1] = &fan_dev_group;
944 	priv->groups[2] = NULL;
945 	hwmon = devm_hwmon_device_register_with_groups(dev,
946 						       "aspeed_pwm_tacho",
947 						       priv, priv->groups);
948 	return PTR_ERR_OR_ZERO(hwmon);
949 }
950 
951 static const struct of_device_id of_pwm_tacho_match_table[] = {
952 	{ .compatible = "aspeed,ast2400-pwm-tacho", },
953 	{ .compatible = "aspeed,ast2500-pwm-tacho", },
954 	{},
955 };
956 MODULE_DEVICE_TABLE(of, of_pwm_tacho_match_table);
957 
958 static struct platform_driver aspeed_pwm_tacho_driver = {
959 	.probe		= aspeed_pwm_tacho_probe,
960 	.driver		= {
961 		.name	= "aspeed_pwm_tacho",
962 		.of_match_table = of_pwm_tacho_match_table,
963 	},
964 };
965 
966 module_platform_driver(aspeed_pwm_tacho_driver);
967 
968 MODULE_AUTHOR("Jaghathiswari Rankappagounder Natarajan <jaghu@google.com>");
969 MODULE_DESCRIPTION("ASPEED PWM and Fan Tacho device driver");
970 MODULE_LICENSE("GPL");
971