1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021-2022 NVIDIA Corporation 4 * 5 * Author: Dipen Patel <dipenp@nvidia.com> 6 */ 7 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/slab.h> 12 #include <linux/stat.h> 13 #include <linux/interrupt.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/hte.h> 18 #include <linux/uaccess.h> 19 #include <linux/gpio/driver.h> 20 #include <linux/gpio/consumer.h> 21 22 #define HTE_SUSPEND 0 23 24 /* HTE source clock TSC is 31.25MHz */ 25 #define HTE_TS_CLK_RATE_HZ 31250000ULL 26 #define HTE_CLK_RATE_NS 32 27 #define HTE_TS_NS_SHIFT __builtin_ctz(HTE_CLK_RATE_NS) 28 29 #define NV_AON_SLICE_INVALID -1 30 #define NV_LINES_IN_SLICE 32 31 32 /* AON HTE line map For slice 1 */ 33 #define NV_AON_HTE_SLICE1_IRQ_GPIO_28 12 34 #define NV_AON_HTE_SLICE1_IRQ_GPIO_29 13 35 36 /* AON HTE line map For slice 2 */ 37 #define NV_AON_HTE_SLICE2_IRQ_GPIO_0 0 38 #define NV_AON_HTE_SLICE2_IRQ_GPIO_1 1 39 #define NV_AON_HTE_SLICE2_IRQ_GPIO_2 2 40 #define NV_AON_HTE_SLICE2_IRQ_GPIO_3 3 41 #define NV_AON_HTE_SLICE2_IRQ_GPIO_4 4 42 #define NV_AON_HTE_SLICE2_IRQ_GPIO_5 5 43 #define NV_AON_HTE_SLICE2_IRQ_GPIO_6 6 44 #define NV_AON_HTE_SLICE2_IRQ_GPIO_7 7 45 #define NV_AON_HTE_SLICE2_IRQ_GPIO_8 8 46 #define NV_AON_HTE_SLICE2_IRQ_GPIO_9 9 47 #define NV_AON_HTE_SLICE2_IRQ_GPIO_10 10 48 #define NV_AON_HTE_SLICE2_IRQ_GPIO_11 11 49 #define NV_AON_HTE_SLICE2_IRQ_GPIO_12 12 50 #define NV_AON_HTE_SLICE2_IRQ_GPIO_13 13 51 #define NV_AON_HTE_SLICE2_IRQ_GPIO_14 14 52 #define NV_AON_HTE_SLICE2_IRQ_GPIO_15 15 53 #define NV_AON_HTE_SLICE2_IRQ_GPIO_16 16 54 #define NV_AON_HTE_SLICE2_IRQ_GPIO_17 17 55 #define NV_AON_HTE_SLICE2_IRQ_GPIO_18 18 56 #define NV_AON_HTE_SLICE2_IRQ_GPIO_19 19 57 #define NV_AON_HTE_SLICE2_IRQ_GPIO_20 20 58 #define NV_AON_HTE_SLICE2_IRQ_GPIO_21 21 59 #define NV_AON_HTE_SLICE2_IRQ_GPIO_22 22 60 #define NV_AON_HTE_SLICE2_IRQ_GPIO_23 23 61 #define NV_AON_HTE_SLICE2_IRQ_GPIO_24 24 62 #define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25 63 #define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26 64 #define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27 65 #define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28 66 #define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29 67 #define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30 68 #define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31 69 70 #define HTE_TECTRL 0x0 71 #define HTE_TETSCH 0x4 72 #define HTE_TETSCL 0x8 73 #define HTE_TESRC 0xC 74 #define HTE_TECCV 0x10 75 #define HTE_TEPCV 0x14 76 #define HTE_TECMD 0x1C 77 #define HTE_TESTATUS 0x20 78 #define HTE_SLICE0_TETEN 0x40 79 #define HTE_SLICE1_TETEN 0x60 80 81 #define HTE_SLICE_SIZE (HTE_SLICE1_TETEN - HTE_SLICE0_TETEN) 82 83 #define HTE_TECTRL_ENABLE_ENABLE 0x1 84 85 #define HTE_TECTRL_OCCU_SHIFT 0x8 86 #define HTE_TECTRL_INTR_SHIFT 0x1 87 #define HTE_TECTRL_INTR_ENABLE 0x1 88 89 #define HTE_TESRC_SLICE_SHIFT 16 90 #define HTE_TESRC_SLICE_DEFAULT_MASK 0xFF 91 92 #define HTE_TECMD_CMD_POP 0x1 93 94 #define HTE_TESTATUS_OCCUPANCY_SHIFT 8 95 #define HTE_TESTATUS_OCCUPANCY_MASK 0xFF 96 97 enum tegra_hte_type { 98 HTE_TEGRA_TYPE_GPIO = 1U << 0, 99 HTE_TEGRA_TYPE_LIC = 1U << 1, 100 }; 101 102 struct hte_slices { 103 u32 r_val; 104 unsigned long flags; 105 /* to prevent lines mapped to same slice updating its register */ 106 spinlock_t s_lock; 107 }; 108 109 struct tegra_hte_line_mapped { 110 int slice; 111 u32 bit_index; 112 }; 113 114 struct tegra_hte_line_data { 115 unsigned long flags; 116 void *data; 117 }; 118 119 struct tegra_hte_data { 120 enum tegra_hte_type type; 121 u32 map_sz; 122 u32 sec_map_sz; 123 const struct tegra_hte_line_mapped *map; 124 const struct tegra_hte_line_mapped *sec_map; 125 }; 126 127 struct tegra_hte_soc { 128 int hte_irq; 129 u32 itr_thrshld; 130 u32 conf_rval; 131 struct hte_slices *sl; 132 const struct tegra_hte_data *prov_data; 133 struct tegra_hte_line_data *line_data; 134 struct hte_chip *chip; 135 struct gpio_chip *c; 136 void __iomem *regs; 137 }; 138 139 static const struct tegra_hte_line_mapped tegra194_aon_gpio_map[] = { 140 /* gpio, slice, bit_index */ 141 /* AA port */ 142 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 143 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 144 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 145 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 146 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 147 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 148 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 149 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 150 /* BB port */ 151 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 152 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 153 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 154 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 155 /* CC port */ 156 [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 157 [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 158 [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 159 [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 160 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 161 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 162 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 163 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 164 /* DD port */ 165 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 166 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 167 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 168 /* EE port */ 169 [23] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_29}, 170 [24] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_28}, 171 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 172 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 173 [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 174 [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 175 [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 176 }; 177 178 static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = { 179 /* gpio, slice, bit_index */ 180 /* AA port */ 181 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 182 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 183 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 184 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 185 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 186 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 187 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 188 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 189 /* BB port */ 190 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 191 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 192 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 193 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 194 [12] = {NV_AON_SLICE_INVALID, 0}, 195 [13] = {NV_AON_SLICE_INVALID, 0}, 196 [14] = {NV_AON_SLICE_INVALID, 0}, 197 [15] = {NV_AON_SLICE_INVALID, 0}, 198 /* CC port */ 199 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 200 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 201 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 202 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 203 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 204 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 205 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 206 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 207 /* DD port */ 208 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 209 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 210 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 211 [27] = {NV_AON_SLICE_INVALID, 0}, 212 [28] = {NV_AON_SLICE_INVALID, 0}, 213 [29] = {NV_AON_SLICE_INVALID, 0}, 214 [30] = {NV_AON_SLICE_INVALID, 0}, 215 [31] = {NV_AON_SLICE_INVALID, 0}, 216 /* EE port */ 217 [32] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_29}, 218 [33] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_28}, 219 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 220 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 221 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 222 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 223 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 224 [39] = {NV_AON_SLICE_INVALID, 0}, 225 }; 226 227 static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = { 228 /* gpio, slice, bit_index */ 229 /* AA port */ 230 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 231 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 232 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 233 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 234 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 235 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 236 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 237 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 238 /* BB port */ 239 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 240 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 241 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 242 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 243 /* CC port */ 244 [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 245 [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 246 [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 247 [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 248 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 249 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 250 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 251 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 252 /* DD port */ 253 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 254 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 255 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 256 /* EE port */ 257 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, 258 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, 259 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, 260 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, 261 [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 262 [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 263 [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 264 [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 265 /* GG port */ 266 [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 267 }; 268 269 static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = { 270 /* gpio, slice, bit_index */ 271 /* AA port */ 272 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 273 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 274 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 275 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 276 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 277 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 278 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 279 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 280 /* BB port */ 281 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 282 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 283 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 284 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 285 [12] = {NV_AON_SLICE_INVALID, 0}, 286 [13] = {NV_AON_SLICE_INVALID, 0}, 287 [14] = {NV_AON_SLICE_INVALID, 0}, 288 [15] = {NV_AON_SLICE_INVALID, 0}, 289 /* CC port */ 290 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 291 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 292 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 293 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 294 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 295 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 296 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 297 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 298 /* DD port */ 299 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 300 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 301 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 302 [27] = {NV_AON_SLICE_INVALID, 0}, 303 [28] = {NV_AON_SLICE_INVALID, 0}, 304 [29] = {NV_AON_SLICE_INVALID, 0}, 305 [30] = {NV_AON_SLICE_INVALID, 0}, 306 [31] = {NV_AON_SLICE_INVALID, 0}, 307 /* EE port */ 308 [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, 309 [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, 310 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, 311 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, 312 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 313 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 314 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 315 [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 316 /* GG port */ 317 [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 318 }; 319 320 static const struct tegra_hte_data t194_aon_hte = { 321 .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map), 322 .map = tegra194_aon_gpio_map, 323 .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), 324 .sec_map = tegra194_aon_gpio_sec_map, 325 .type = HTE_TEGRA_TYPE_GPIO, 326 }; 327 328 static const struct tegra_hte_data t234_aon_hte = { 329 .map_sz = ARRAY_SIZE(tegra234_aon_gpio_map), 330 .map = tegra234_aon_gpio_map, 331 .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), 332 .sec_map = tegra234_aon_gpio_sec_map, 333 .type = HTE_TEGRA_TYPE_GPIO, 334 }; 335 336 static const struct tegra_hte_data lic_hte = { 337 .map_sz = 0, 338 .map = NULL, 339 .type = HTE_TEGRA_TYPE_LIC, 340 }; 341 342 static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg) 343 { 344 return readl(hte->regs + reg); 345 } 346 347 static inline void tegra_hte_writel(struct tegra_hte_soc *hte, u32 reg, 348 u32 val) 349 { 350 writel(val, hte->regs + reg); 351 } 352 353 static int tegra_hte_map_to_line_id(u32 eid, 354 const struct tegra_hte_line_mapped *m, 355 u32 map_sz, u32 *mapped) 356 { 357 358 if (m) { 359 if (eid > map_sz) 360 return -EINVAL; 361 if (m[eid].slice == NV_AON_SLICE_INVALID) 362 return -EINVAL; 363 364 *mapped = (m[eid].slice << 5) + m[eid].bit_index; 365 } else { 366 *mapped = eid; 367 } 368 369 return 0; 370 } 371 372 static int tegra_hte_line_xlate(struct hte_chip *gc, 373 const struct of_phandle_args *args, 374 struct hte_ts_desc *desc, u32 *xlated_id) 375 { 376 int ret = 0; 377 u32 line_id; 378 struct tegra_hte_soc *gs; 379 const struct tegra_hte_line_mapped *map = NULL; 380 u32 map_sz = 0; 381 382 if (!gc || !desc || !xlated_id) 383 return -EINVAL; 384 385 if (args) { 386 if (gc->of_hte_n_cells < 1) 387 return -EINVAL; 388 389 if (args->args_count != gc->of_hte_n_cells) 390 return -EINVAL; 391 392 desc->attr.line_id = args->args[0]; 393 } 394 395 gs = gc->data; 396 if (!gs || !gs->prov_data) 397 return -EINVAL; 398 399 /* 400 * 401 * There are two paths GPIO consumers can take as follows: 402 * 1) The consumer (gpiolib-cdev for example) which uses GPIO global 403 * number which gets assigned run time. 404 * 2) The consumer passing GPIO from the DT which is assigned 405 * statically for example by using TEGRA194_AON_GPIO gpio DT binding. 406 * 407 * The code below addresses both the consumer use cases and maps into 408 * HTE/GTE namespace. 409 */ 410 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && !args) { 411 line_id = desc->attr.line_id - gs->c->base; 412 map = gs->prov_data->map; 413 map_sz = gs->prov_data->map_sz; 414 } else if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && args) { 415 line_id = desc->attr.line_id; 416 map = gs->prov_data->sec_map; 417 map_sz = gs->prov_data->sec_map_sz; 418 } else { 419 line_id = desc->attr.line_id; 420 } 421 422 ret = tegra_hte_map_to_line_id(line_id, map, map_sz, xlated_id); 423 if (ret < 0) { 424 dev_err(gc->dev, "line_id:%u mapping failed\n", 425 desc->attr.line_id); 426 return ret; 427 } 428 429 if (*xlated_id > gc->nlines) 430 return -EINVAL; 431 432 dev_dbg(gc->dev, "requested id:%u, xlated id:%u\n", 433 desc->attr.line_id, *xlated_id); 434 435 return 0; 436 } 437 438 static int tegra_hte_line_xlate_plat(struct hte_chip *gc, 439 struct hte_ts_desc *desc, u32 *xlated_id) 440 { 441 return tegra_hte_line_xlate(gc, NULL, desc, xlated_id); 442 } 443 444 static int tegra_hte_en_dis_common(struct hte_chip *chip, u32 line_id, bool en) 445 { 446 u32 slice, sl_bit_shift, line_bit, val, reg; 447 struct tegra_hte_soc *gs; 448 449 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); 450 451 if (!chip) 452 return -EINVAL; 453 454 gs = chip->data; 455 456 if (line_id > chip->nlines) { 457 dev_err(chip->dev, 458 "line id: %u is not supported by this controller\n", 459 line_id); 460 return -EINVAL; 461 } 462 463 slice = line_id >> sl_bit_shift; 464 line_bit = line_id & (HTE_SLICE_SIZE - 1); 465 reg = (slice << sl_bit_shift) + HTE_SLICE0_TETEN; 466 467 spin_lock(&gs->sl[slice].s_lock); 468 469 if (test_bit(HTE_SUSPEND, &gs->sl[slice].flags)) { 470 spin_unlock(&gs->sl[slice].s_lock); 471 dev_dbg(chip->dev, "device suspended"); 472 return -EBUSY; 473 } 474 475 val = tegra_hte_readl(gs, reg); 476 if (en) 477 val = val | (1 << line_bit); 478 else 479 val = val & (~(1 << line_bit)); 480 tegra_hte_writel(gs, reg, val); 481 482 spin_unlock(&gs->sl[slice].s_lock); 483 484 dev_dbg(chip->dev, "line: %u, slice %u, line_bit %u, reg:0x%x\n", 485 line_id, slice, line_bit, reg); 486 487 return 0; 488 } 489 490 static int tegra_hte_enable(struct hte_chip *chip, u32 line_id) 491 { 492 if (!chip) 493 return -EINVAL; 494 495 return tegra_hte_en_dis_common(chip, line_id, true); 496 } 497 498 static int tegra_hte_disable(struct hte_chip *chip, u32 line_id) 499 { 500 if (!chip) 501 return -EINVAL; 502 503 return tegra_hte_en_dis_common(chip, line_id, false); 504 } 505 506 static int tegra_hte_request(struct hte_chip *chip, struct hte_ts_desc *desc, 507 u32 line_id) 508 { 509 int ret; 510 struct tegra_hte_soc *gs; 511 struct hte_line_attr *attr; 512 513 if (!chip || !chip->data || !desc) 514 return -EINVAL; 515 516 gs = chip->data; 517 attr = &desc->attr; 518 519 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 520 if (!attr->line_data) 521 return -EINVAL; 522 523 ret = gpiod_enable_hw_timestamp_ns(attr->line_data, 524 attr->edge_flags); 525 if (ret) 526 return ret; 527 528 gs->line_data[line_id].data = attr->line_data; 529 gs->line_data[line_id].flags = attr->edge_flags; 530 } 531 532 return tegra_hte_en_dis_common(chip, line_id, true); 533 } 534 535 static int tegra_hte_release(struct hte_chip *chip, struct hte_ts_desc *desc, 536 u32 line_id) 537 { 538 struct tegra_hte_soc *gs; 539 struct hte_line_attr *attr; 540 int ret; 541 542 if (!chip || !chip->data || !desc) 543 return -EINVAL; 544 545 gs = chip->data; 546 attr = &desc->attr; 547 548 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 549 ret = gpiod_disable_hw_timestamp_ns(attr->line_data, 550 gs->line_data[line_id].flags); 551 if (ret) 552 return ret; 553 554 gs->line_data[line_id].data = NULL; 555 gs->line_data[line_id].flags = 0; 556 } 557 558 return tegra_hte_en_dis_common(chip, line_id, false); 559 } 560 561 static int tegra_hte_clk_src_info(struct hte_chip *chip, 562 struct hte_clk_info *ci) 563 { 564 (void)chip; 565 566 if (!ci) 567 return -EINVAL; 568 569 ci->hz = HTE_TS_CLK_RATE_HZ; 570 ci->type = CLOCK_MONOTONIC; 571 572 return 0; 573 } 574 575 static int tegra_hte_get_level(struct tegra_hte_soc *gs, u32 line_id) 576 { 577 struct gpio_desc *desc; 578 579 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 580 desc = gs->line_data[line_id].data; 581 if (desc) 582 return gpiod_get_raw_value(desc); 583 } 584 585 return -1; 586 } 587 588 static void tegra_hte_read_fifo(struct tegra_hte_soc *gs) 589 { 590 u32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id; 591 u64 tsc; 592 struct hte_ts_data el; 593 594 while ((tegra_hte_readl(gs, HTE_TESTATUS) >> 595 HTE_TESTATUS_OCCUPANCY_SHIFT) & 596 HTE_TESTATUS_OCCUPANCY_MASK) { 597 tsh = tegra_hte_readl(gs, HTE_TETSCH); 598 tsl = tegra_hte_readl(gs, HTE_TETSCL); 599 tsc = (((u64)tsh << 32) | tsl); 600 601 src = tegra_hte_readl(gs, HTE_TESRC); 602 slice = (src >> HTE_TESRC_SLICE_SHIFT) & 603 HTE_TESRC_SLICE_DEFAULT_MASK; 604 605 pv = tegra_hte_readl(gs, HTE_TEPCV); 606 cv = tegra_hte_readl(gs, HTE_TECCV); 607 acv = pv ^ cv; 608 while (acv) { 609 bit_index = __builtin_ctz(acv); 610 line_id = bit_index + (slice << 5); 611 el.tsc = tsc << HTE_TS_NS_SHIFT; 612 el.raw_level = tegra_hte_get_level(gs, line_id); 613 hte_push_ts_ns(gs->chip, line_id, &el); 614 acv &= ~BIT(bit_index); 615 } 616 tegra_hte_writel(gs, HTE_TECMD, HTE_TECMD_CMD_POP); 617 } 618 } 619 620 static irqreturn_t tegra_hte_isr(int irq, void *dev_id) 621 { 622 struct tegra_hte_soc *gs = dev_id; 623 (void)irq; 624 625 tegra_hte_read_fifo(gs); 626 627 return IRQ_HANDLED; 628 } 629 630 static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, 631 const struct hte_ts_desc *hdesc) 632 { 633 struct tegra_hte_soc *hte_dev = chip->data; 634 635 if (!hte_dev || (hte_dev->prov_data->type != HTE_TEGRA_TYPE_GPIO)) 636 return false; 637 638 return hte_dev->c == gpiod_to_chip(hdesc->attr.line_data); 639 } 640 641 static const struct of_device_id tegra_hte_of_match[] = { 642 { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte}, 643 { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, 644 { .compatible = "nvidia,tegra234-gte-lic", .data = &lic_hte}, 645 { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, 646 { } 647 }; 648 MODULE_DEVICE_TABLE(of, tegra_hte_of_match); 649 650 static const struct hte_ops g_ops = { 651 .request = tegra_hte_request, 652 .release = tegra_hte_release, 653 .enable = tegra_hte_enable, 654 .disable = tegra_hte_disable, 655 .get_clk_src_info = tegra_hte_clk_src_info, 656 }; 657 658 static void tegra_gte_disable(void *data) 659 { 660 struct platform_device *pdev = data; 661 struct tegra_hte_soc *gs = dev_get_drvdata(&pdev->dev); 662 663 tegra_hte_writel(gs, HTE_TECTRL, 0); 664 } 665 666 static int tegra_get_gpiochip_from_name(struct gpio_chip *chip, void *data) 667 { 668 return !strcmp(chip->label, data); 669 } 670 671 static int tegra_hte_probe(struct platform_device *pdev) 672 { 673 int ret; 674 u32 i, slices, val = 0; 675 u32 nlines; 676 struct device *dev; 677 struct tegra_hte_soc *hte_dev; 678 struct hte_chip *gc; 679 680 dev = &pdev->dev; 681 682 ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); 683 if (ret != 0) { 684 dev_err(dev, "Could not read slices\n"); 685 return -EINVAL; 686 } 687 nlines = slices << 5; 688 689 hte_dev = devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL); 690 if (!hte_dev) 691 return -ENOMEM; 692 693 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 694 if (!gc) 695 return -ENOMEM; 696 697 dev_set_drvdata(&pdev->dev, hte_dev); 698 hte_dev->prov_data = of_device_get_match_data(&pdev->dev); 699 700 hte_dev->regs = devm_platform_ioremap_resource(pdev, 0); 701 if (IS_ERR(hte_dev->regs)) 702 return PTR_ERR(hte_dev->regs); 703 704 ret = of_property_read_u32(dev->of_node, "nvidia,int-threshold", 705 &hte_dev->itr_thrshld); 706 if (ret != 0) 707 hte_dev->itr_thrshld = 1; 708 709 hte_dev->sl = devm_kcalloc(dev, slices, sizeof(*hte_dev->sl), 710 GFP_KERNEL); 711 if (!hte_dev->sl) 712 return -ENOMEM; 713 714 ret = platform_get_irq(pdev, 0); 715 if (ret < 0) { 716 dev_err_probe(dev, ret, "failed to get irq\n"); 717 return ret; 718 } 719 hte_dev->hte_irq = ret; 720 ret = devm_request_irq(dev, hte_dev->hte_irq, tegra_hte_isr, 0, 721 dev_name(dev), hte_dev); 722 if (ret < 0) { 723 dev_err(dev, "request irq failed.\n"); 724 return ret; 725 } 726 727 gc->nlines = nlines; 728 gc->ops = &g_ops; 729 gc->dev = dev; 730 gc->data = hte_dev; 731 gc->xlate_of = tegra_hte_line_xlate; 732 gc->xlate_plat = tegra_hte_line_xlate_plat; 733 gc->of_hte_n_cells = 1; 734 735 if (hte_dev->prov_data && 736 hte_dev->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 737 hte_dev->line_data = devm_kcalloc(dev, nlines, 738 sizeof(*hte_dev->line_data), 739 GFP_KERNEL); 740 if (!hte_dev->line_data) 741 return -ENOMEM; 742 743 gc->match_from_linedata = tegra_hte_match_from_linedata; 744 745 if (of_device_is_compatible(dev->of_node, 746 "nvidia,tegra194-gte-aon")) 747 hte_dev->c = gpiochip_find("tegra194-gpio-aon", 748 tegra_get_gpiochip_from_name); 749 else if (of_device_is_compatible(dev->of_node, 750 "nvidia,tegra234-gte-aon")) 751 hte_dev->c = gpiochip_find("tegra234-gpio-aon", 752 tegra_get_gpiochip_from_name); 753 else 754 return -ENODEV; 755 756 if (!hte_dev->c) 757 return dev_err_probe(dev, -EPROBE_DEFER, 758 "wait for gpio controller\n"); 759 } 760 761 hte_dev->chip = gc; 762 763 ret = devm_hte_register_chip(hte_dev->chip); 764 if (ret) { 765 dev_err(gc->dev, "hte chip register failed"); 766 return ret; 767 } 768 769 for (i = 0; i < slices; i++) { 770 hte_dev->sl[i].flags = 0; 771 spin_lock_init(&hte_dev->sl[i].s_lock); 772 } 773 774 val = HTE_TECTRL_ENABLE_ENABLE | 775 (HTE_TECTRL_INTR_ENABLE << HTE_TECTRL_INTR_SHIFT) | 776 (hte_dev->itr_thrshld << HTE_TECTRL_OCCU_SHIFT); 777 tegra_hte_writel(hte_dev, HTE_TECTRL, val); 778 779 ret = devm_add_action_or_reset(&pdev->dev, tegra_gte_disable, pdev); 780 if (ret) 781 return ret; 782 783 dev_dbg(gc->dev, "lines: %d, slices:%d", gc->nlines, slices); 784 785 return 0; 786 } 787 788 static int __maybe_unused tegra_hte_resume_early(struct device *dev) 789 { 790 u32 i; 791 struct tegra_hte_soc *gs = dev_get_drvdata(dev); 792 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; 793 u32 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); 794 795 tegra_hte_writel(gs, HTE_TECTRL, gs->conf_rval); 796 797 for (i = 0; i < slices; i++) { 798 spin_lock(&gs->sl[i].s_lock); 799 tegra_hte_writel(gs, 800 ((i << sl_bit_shift) + HTE_SLICE0_TETEN), 801 gs->sl[i].r_val); 802 clear_bit(HTE_SUSPEND, &gs->sl[i].flags); 803 spin_unlock(&gs->sl[i].s_lock); 804 } 805 806 return 0; 807 } 808 809 static int __maybe_unused tegra_hte_suspend_late(struct device *dev) 810 { 811 u32 i; 812 struct tegra_hte_soc *gs = dev_get_drvdata(dev); 813 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; 814 u32 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); 815 816 gs->conf_rval = tegra_hte_readl(gs, HTE_TECTRL); 817 for (i = 0; i < slices; i++) { 818 spin_lock(&gs->sl[i].s_lock); 819 gs->sl[i].r_val = tegra_hte_readl(gs, 820 ((i << sl_bit_shift) + HTE_SLICE0_TETEN)); 821 set_bit(HTE_SUSPEND, &gs->sl[i].flags); 822 spin_unlock(&gs->sl[i].s_lock); 823 } 824 825 return 0; 826 } 827 828 static const struct dev_pm_ops tegra_hte_pm = { 829 SET_LATE_SYSTEM_SLEEP_PM_OPS(tegra_hte_suspend_late, 830 tegra_hte_resume_early) 831 }; 832 833 static struct platform_driver tegra_hte_driver = { 834 .probe = tegra_hte_probe, 835 .driver = { 836 .name = "tegra_hte", 837 .pm = &tegra_hte_pm, 838 .of_match_table = tegra_hte_of_match, 839 }, 840 }; 841 842 module_platform_driver(tegra_hte_driver); 843 844 MODULE_AUTHOR("Dipen Patel <dipenp@nvidia.com>"); 845 MODULE_DESCRIPTION("NVIDIA Tegra HTE (Hardware Timestamping Engine) driver"); 846 MODULE_LICENSE("GPL"); 847