1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021-2022 NVIDIA Corporation 4 * 5 * Author: Dipen Patel <dipenp@nvidia.com> 6 */ 7 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/slab.h> 12 #include <linux/stat.h> 13 #include <linux/interrupt.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/hte.h> 18 #include <linux/uaccess.h> 19 #include <linux/gpio/driver.h> 20 #include <linux/gpio/consumer.h> 21 22 #define HTE_SUSPEND 0 23 24 /* HTE source clock TSC is 31.25MHz */ 25 #define HTE_TS_CLK_RATE_HZ 31250000ULL 26 #define HTE_CLK_RATE_NS 32 27 #define HTE_TS_NS_SHIFT __builtin_ctz(HTE_CLK_RATE_NS) 28 29 #define NV_AON_SLICE_INVALID -1 30 #define NV_LINES_IN_SLICE 32 31 32 /* AON HTE line map For slice 1 */ 33 #define NV_AON_HTE_SLICE1_IRQ_GPIO_28 12 34 #define NV_AON_HTE_SLICE1_IRQ_GPIO_29 13 35 36 /* AON HTE line map For slice 2 */ 37 #define NV_AON_HTE_SLICE2_IRQ_GPIO_0 0 38 #define NV_AON_HTE_SLICE2_IRQ_GPIO_1 1 39 #define NV_AON_HTE_SLICE2_IRQ_GPIO_2 2 40 #define NV_AON_HTE_SLICE2_IRQ_GPIO_3 3 41 #define NV_AON_HTE_SLICE2_IRQ_GPIO_4 4 42 #define NV_AON_HTE_SLICE2_IRQ_GPIO_5 5 43 #define NV_AON_HTE_SLICE2_IRQ_GPIO_6 6 44 #define NV_AON_HTE_SLICE2_IRQ_GPIO_7 7 45 #define NV_AON_HTE_SLICE2_IRQ_GPIO_8 8 46 #define NV_AON_HTE_SLICE2_IRQ_GPIO_9 9 47 #define NV_AON_HTE_SLICE2_IRQ_GPIO_10 10 48 #define NV_AON_HTE_SLICE2_IRQ_GPIO_11 11 49 #define NV_AON_HTE_SLICE2_IRQ_GPIO_12 12 50 #define NV_AON_HTE_SLICE2_IRQ_GPIO_13 13 51 #define NV_AON_HTE_SLICE2_IRQ_GPIO_14 14 52 #define NV_AON_HTE_SLICE2_IRQ_GPIO_15 15 53 #define NV_AON_HTE_SLICE2_IRQ_GPIO_16 16 54 #define NV_AON_HTE_SLICE2_IRQ_GPIO_17 17 55 #define NV_AON_HTE_SLICE2_IRQ_GPIO_18 18 56 #define NV_AON_HTE_SLICE2_IRQ_GPIO_19 19 57 #define NV_AON_HTE_SLICE2_IRQ_GPIO_20 20 58 #define NV_AON_HTE_SLICE2_IRQ_GPIO_21 21 59 #define NV_AON_HTE_SLICE2_IRQ_GPIO_22 22 60 #define NV_AON_HTE_SLICE2_IRQ_GPIO_23 23 61 #define NV_AON_HTE_SLICE2_IRQ_GPIO_24 24 62 #define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25 63 #define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26 64 #define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27 65 #define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28 66 #define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29 67 #define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30 68 #define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31 69 70 #define HTE_TECTRL 0x0 71 #define HTE_TETSCH 0x4 72 #define HTE_TETSCL 0x8 73 #define HTE_TESRC 0xC 74 #define HTE_TECCV 0x10 75 #define HTE_TEPCV 0x14 76 #define HTE_TECMD 0x1C 77 #define HTE_TESTATUS 0x20 78 #define HTE_SLICE0_TETEN 0x40 79 #define HTE_SLICE1_TETEN 0x60 80 81 #define HTE_SLICE_SIZE (HTE_SLICE1_TETEN - HTE_SLICE0_TETEN) 82 83 #define HTE_TECTRL_ENABLE_ENABLE 0x1 84 85 #define HTE_TECTRL_OCCU_SHIFT 0x8 86 #define HTE_TECTRL_INTR_SHIFT 0x1 87 #define HTE_TECTRL_INTR_ENABLE 0x1 88 89 #define HTE_TESRC_SLICE_SHIFT 16 90 #define HTE_TESRC_SLICE_DEFAULT_MASK 0xFF 91 92 #define HTE_TECMD_CMD_POP 0x1 93 94 #define HTE_TESTATUS_OCCUPANCY_SHIFT 8 95 #define HTE_TESTATUS_OCCUPANCY_MASK 0xFF 96 97 enum tegra_hte_type { 98 HTE_TEGRA_TYPE_GPIO = 1U << 0, 99 HTE_TEGRA_TYPE_LIC = 1U << 1, 100 }; 101 102 struct hte_slices { 103 u32 r_val; 104 unsigned long flags; 105 /* to prevent lines mapped to same slice updating its register */ 106 spinlock_t s_lock; 107 }; 108 109 struct tegra_hte_line_mapped { 110 int slice; 111 u32 bit_index; 112 }; 113 114 struct tegra_hte_line_data { 115 unsigned long flags; 116 void *data; 117 }; 118 119 struct tegra_hte_data { 120 enum tegra_hte_type type; 121 u32 slices; 122 u32 map_sz; 123 u32 sec_map_sz; 124 const struct tegra_hte_line_mapped *map; 125 const struct tegra_hte_line_mapped *sec_map; 126 }; 127 128 struct tegra_hte_soc { 129 int hte_irq; 130 u32 itr_thrshld; 131 u32 conf_rval; 132 struct hte_slices *sl; 133 const struct tegra_hte_data *prov_data; 134 struct tegra_hte_line_data *line_data; 135 struct hte_chip *chip; 136 struct gpio_chip *c; 137 void __iomem *regs; 138 }; 139 140 static const struct tegra_hte_line_mapped tegra194_aon_gpio_map[] = { 141 /* gpio, slice, bit_index */ 142 /* AA port */ 143 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 144 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 145 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 146 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 147 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 148 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 149 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 150 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 151 /* BB port */ 152 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 153 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 154 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 155 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 156 /* CC port */ 157 [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 158 [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 159 [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 160 [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 161 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 162 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 163 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 164 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 165 /* DD port */ 166 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 167 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 168 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 169 /* EE port */ 170 [23] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_29}, 171 [24] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_28}, 172 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 173 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 174 [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 175 [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 176 [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 177 }; 178 179 static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = { 180 /* gpio, slice, bit_index */ 181 /* AA port */ 182 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 183 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 184 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 185 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 186 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 187 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 188 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 189 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 190 /* BB port */ 191 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 192 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 193 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 194 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 195 [12] = {NV_AON_SLICE_INVALID, 0}, 196 [13] = {NV_AON_SLICE_INVALID, 0}, 197 [14] = {NV_AON_SLICE_INVALID, 0}, 198 [15] = {NV_AON_SLICE_INVALID, 0}, 199 /* CC port */ 200 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 201 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 202 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 203 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 204 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 205 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 206 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 207 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 208 /* DD port */ 209 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 210 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 211 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 212 [27] = {NV_AON_SLICE_INVALID, 0}, 213 [28] = {NV_AON_SLICE_INVALID, 0}, 214 [29] = {NV_AON_SLICE_INVALID, 0}, 215 [30] = {NV_AON_SLICE_INVALID, 0}, 216 [31] = {NV_AON_SLICE_INVALID, 0}, 217 /* EE port */ 218 [32] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_29}, 219 [33] = {1, NV_AON_HTE_SLICE1_IRQ_GPIO_28}, 220 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 221 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 222 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 223 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 224 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 225 [39] = {NV_AON_SLICE_INVALID, 0}, 226 }; 227 228 static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = { 229 /* gpio, slice, bit_index */ 230 /* AA port */ 231 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 232 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 233 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 234 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 235 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 236 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 237 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 238 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 239 /* BB port */ 240 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 241 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 242 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 243 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 244 /* CC port */ 245 [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 246 [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 247 [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 248 [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 249 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 250 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 251 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 252 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 253 /* DD port */ 254 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 255 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 256 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 257 /* EE port */ 258 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, 259 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, 260 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, 261 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, 262 [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 263 [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 264 [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 265 [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 266 /* GG port */ 267 [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 268 }; 269 270 static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = { 271 /* gpio, slice, bit_index */ 272 /* AA port */ 273 [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, 274 [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, 275 [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, 276 [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, 277 [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, 278 [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, 279 [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, 280 [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, 281 /* BB port */ 282 [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, 283 [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, 284 [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, 285 [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, 286 [12] = {NV_AON_SLICE_INVALID, 0}, 287 [13] = {NV_AON_SLICE_INVALID, 0}, 288 [14] = {NV_AON_SLICE_INVALID, 0}, 289 [15] = {NV_AON_SLICE_INVALID, 0}, 290 /* CC port */ 291 [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, 292 [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, 293 [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, 294 [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, 295 [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, 296 [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, 297 [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, 298 [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, 299 /* DD port */ 300 [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, 301 [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, 302 [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, 303 [27] = {NV_AON_SLICE_INVALID, 0}, 304 [28] = {NV_AON_SLICE_INVALID, 0}, 305 [29] = {NV_AON_SLICE_INVALID, 0}, 306 [30] = {NV_AON_SLICE_INVALID, 0}, 307 [31] = {NV_AON_SLICE_INVALID, 0}, 308 /* EE port */ 309 [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, 310 [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, 311 [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, 312 [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, 313 [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, 314 [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, 315 [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, 316 [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, 317 /* GG port */ 318 [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, 319 }; 320 321 static const struct tegra_hte_data t194_aon_hte = { 322 .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map), 323 .map = tegra194_aon_gpio_map, 324 .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), 325 .sec_map = tegra194_aon_gpio_sec_map, 326 .type = HTE_TEGRA_TYPE_GPIO, 327 .slices = 3, 328 }; 329 330 static const struct tegra_hte_data t234_aon_hte = { 331 .map_sz = ARRAY_SIZE(tegra234_aon_gpio_map), 332 .map = tegra234_aon_gpio_map, 333 .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), 334 .sec_map = tegra234_aon_gpio_sec_map, 335 .type = HTE_TEGRA_TYPE_GPIO, 336 .slices = 3, 337 }; 338 339 static const struct tegra_hte_data t194_lic_hte = { 340 .map_sz = 0, 341 .map = NULL, 342 .type = HTE_TEGRA_TYPE_LIC, 343 .slices = 11, 344 }; 345 346 static const struct tegra_hte_data t234_lic_hte = { 347 .map_sz = 0, 348 .map = NULL, 349 .type = HTE_TEGRA_TYPE_LIC, 350 .slices = 17, 351 }; 352 353 static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg) 354 { 355 return readl(hte->regs + reg); 356 } 357 358 static inline void tegra_hte_writel(struct tegra_hte_soc *hte, u32 reg, 359 u32 val) 360 { 361 writel(val, hte->regs + reg); 362 } 363 364 static int tegra_hte_map_to_line_id(u32 eid, 365 const struct tegra_hte_line_mapped *m, 366 u32 map_sz, u32 *mapped) 367 { 368 369 if (m) { 370 if (eid >= map_sz) 371 return -EINVAL; 372 if (m[eid].slice == NV_AON_SLICE_INVALID) 373 return -EINVAL; 374 375 *mapped = (m[eid].slice << 5) + m[eid].bit_index; 376 } else { 377 *mapped = eid; 378 } 379 380 return 0; 381 } 382 383 static int tegra_hte_line_xlate(struct hte_chip *gc, 384 const struct of_phandle_args *args, 385 struct hte_ts_desc *desc, u32 *xlated_id) 386 { 387 int ret = 0; 388 u32 line_id; 389 struct tegra_hte_soc *gs; 390 const struct tegra_hte_line_mapped *map = NULL; 391 u32 map_sz = 0; 392 393 if (!gc || !desc || !xlated_id) 394 return -EINVAL; 395 396 if (args) { 397 if (gc->of_hte_n_cells < 1) 398 return -EINVAL; 399 400 if (args->args_count != gc->of_hte_n_cells) 401 return -EINVAL; 402 403 desc->attr.line_id = args->args[0]; 404 } 405 406 gs = gc->data; 407 if (!gs || !gs->prov_data) 408 return -EINVAL; 409 410 /* 411 * 412 * There are two paths GPIO consumers can take as follows: 413 * 1) The consumer (gpiolib-cdev for example) which uses GPIO global 414 * number which gets assigned run time. 415 * 2) The consumer passing GPIO from the DT which is assigned 416 * statically for example by using TEGRA194_AON_GPIO gpio DT binding. 417 * 418 * The code below addresses both the consumer use cases and maps into 419 * HTE/GTE namespace. 420 */ 421 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && !args) { 422 line_id = desc->attr.line_id - gs->c->base; 423 map = gs->prov_data->map; 424 map_sz = gs->prov_data->map_sz; 425 } else if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO && args) { 426 line_id = desc->attr.line_id; 427 map = gs->prov_data->sec_map; 428 map_sz = gs->prov_data->sec_map_sz; 429 } else { 430 line_id = desc->attr.line_id; 431 } 432 433 ret = tegra_hte_map_to_line_id(line_id, map, map_sz, xlated_id); 434 if (ret < 0) { 435 dev_err(gc->dev, "line_id:%u mapping failed\n", 436 desc->attr.line_id); 437 return ret; 438 } 439 440 if (*xlated_id > gc->nlines) 441 return -EINVAL; 442 443 dev_dbg(gc->dev, "requested id:%u, xlated id:%u\n", 444 desc->attr.line_id, *xlated_id); 445 446 return 0; 447 } 448 449 static int tegra_hte_line_xlate_plat(struct hte_chip *gc, 450 struct hte_ts_desc *desc, u32 *xlated_id) 451 { 452 return tegra_hte_line_xlate(gc, NULL, desc, xlated_id); 453 } 454 455 static int tegra_hte_en_dis_common(struct hte_chip *chip, u32 line_id, bool en) 456 { 457 u32 slice, sl_bit_shift, line_bit, val, reg; 458 struct tegra_hte_soc *gs; 459 460 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); 461 462 if (!chip) 463 return -EINVAL; 464 465 gs = chip->data; 466 467 if (line_id > chip->nlines) { 468 dev_err(chip->dev, 469 "line id: %u is not supported by this controller\n", 470 line_id); 471 return -EINVAL; 472 } 473 474 slice = line_id >> sl_bit_shift; 475 line_bit = line_id & (HTE_SLICE_SIZE - 1); 476 reg = (slice << sl_bit_shift) + HTE_SLICE0_TETEN; 477 478 spin_lock(&gs->sl[slice].s_lock); 479 480 if (test_bit(HTE_SUSPEND, &gs->sl[slice].flags)) { 481 spin_unlock(&gs->sl[slice].s_lock); 482 dev_dbg(chip->dev, "device suspended"); 483 return -EBUSY; 484 } 485 486 val = tegra_hte_readl(gs, reg); 487 if (en) 488 val = val | (1 << line_bit); 489 else 490 val = val & (~(1 << line_bit)); 491 tegra_hte_writel(gs, reg, val); 492 493 spin_unlock(&gs->sl[slice].s_lock); 494 495 dev_dbg(chip->dev, "line: %u, slice %u, line_bit %u, reg:0x%x\n", 496 line_id, slice, line_bit, reg); 497 498 return 0; 499 } 500 501 static int tegra_hte_enable(struct hte_chip *chip, u32 line_id) 502 { 503 if (!chip) 504 return -EINVAL; 505 506 return tegra_hte_en_dis_common(chip, line_id, true); 507 } 508 509 static int tegra_hte_disable(struct hte_chip *chip, u32 line_id) 510 { 511 if (!chip) 512 return -EINVAL; 513 514 return tegra_hte_en_dis_common(chip, line_id, false); 515 } 516 517 static int tegra_hte_request(struct hte_chip *chip, struct hte_ts_desc *desc, 518 u32 line_id) 519 { 520 int ret; 521 struct tegra_hte_soc *gs; 522 struct hte_line_attr *attr; 523 524 if (!chip || !chip->data || !desc) 525 return -EINVAL; 526 527 gs = chip->data; 528 attr = &desc->attr; 529 530 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 531 if (!attr->line_data) 532 return -EINVAL; 533 534 ret = gpiod_enable_hw_timestamp_ns(attr->line_data, 535 attr->edge_flags); 536 if (ret) 537 return ret; 538 539 gs->line_data[line_id].data = attr->line_data; 540 gs->line_data[line_id].flags = attr->edge_flags; 541 } 542 543 return tegra_hte_en_dis_common(chip, line_id, true); 544 } 545 546 static int tegra_hte_release(struct hte_chip *chip, struct hte_ts_desc *desc, 547 u32 line_id) 548 { 549 struct tegra_hte_soc *gs; 550 struct hte_line_attr *attr; 551 int ret; 552 553 if (!chip || !chip->data || !desc) 554 return -EINVAL; 555 556 gs = chip->data; 557 attr = &desc->attr; 558 559 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 560 ret = gpiod_disable_hw_timestamp_ns(attr->line_data, 561 gs->line_data[line_id].flags); 562 if (ret) 563 return ret; 564 565 gs->line_data[line_id].data = NULL; 566 gs->line_data[line_id].flags = 0; 567 } 568 569 return tegra_hte_en_dis_common(chip, line_id, false); 570 } 571 572 static int tegra_hte_clk_src_info(struct hte_chip *chip, 573 struct hte_clk_info *ci) 574 { 575 (void)chip; 576 577 if (!ci) 578 return -EINVAL; 579 580 ci->hz = HTE_TS_CLK_RATE_HZ; 581 ci->type = CLOCK_MONOTONIC; 582 583 return 0; 584 } 585 586 static int tegra_hte_get_level(struct tegra_hte_soc *gs, u32 line_id) 587 { 588 struct gpio_desc *desc; 589 590 if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 591 desc = gs->line_data[line_id].data; 592 if (desc) 593 return gpiod_get_raw_value(desc); 594 } 595 596 return -1; 597 } 598 599 static void tegra_hte_read_fifo(struct tegra_hte_soc *gs) 600 { 601 u32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id; 602 u64 tsc; 603 struct hte_ts_data el; 604 605 while ((tegra_hte_readl(gs, HTE_TESTATUS) >> 606 HTE_TESTATUS_OCCUPANCY_SHIFT) & 607 HTE_TESTATUS_OCCUPANCY_MASK) { 608 tsh = tegra_hte_readl(gs, HTE_TETSCH); 609 tsl = tegra_hte_readl(gs, HTE_TETSCL); 610 tsc = (((u64)tsh << 32) | tsl); 611 612 src = tegra_hte_readl(gs, HTE_TESRC); 613 slice = (src >> HTE_TESRC_SLICE_SHIFT) & 614 HTE_TESRC_SLICE_DEFAULT_MASK; 615 616 pv = tegra_hte_readl(gs, HTE_TEPCV); 617 cv = tegra_hte_readl(gs, HTE_TECCV); 618 acv = pv ^ cv; 619 while (acv) { 620 bit_index = __builtin_ctz(acv); 621 line_id = bit_index + (slice << 5); 622 el.tsc = tsc << HTE_TS_NS_SHIFT; 623 el.raw_level = tegra_hte_get_level(gs, line_id); 624 hte_push_ts_ns(gs->chip, line_id, &el); 625 acv &= ~BIT(bit_index); 626 } 627 tegra_hte_writel(gs, HTE_TECMD, HTE_TECMD_CMD_POP); 628 } 629 } 630 631 static irqreturn_t tegra_hte_isr(int irq, void *dev_id) 632 { 633 struct tegra_hte_soc *gs = dev_id; 634 (void)irq; 635 636 tegra_hte_read_fifo(gs); 637 638 return IRQ_HANDLED; 639 } 640 641 static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, 642 const struct hte_ts_desc *hdesc) 643 { 644 struct tegra_hte_soc *hte_dev = chip->data; 645 646 if (!hte_dev || (hte_dev->prov_data->type != HTE_TEGRA_TYPE_GPIO)) 647 return false; 648 649 return hte_dev->c == gpiod_to_chip(hdesc->attr.line_data); 650 } 651 652 static const struct of_device_id tegra_hte_of_match[] = { 653 { .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte}, 654 { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, 655 { .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte}, 656 { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, 657 { } 658 }; 659 MODULE_DEVICE_TABLE(of, tegra_hte_of_match); 660 661 static const struct hte_ops g_ops = { 662 .request = tegra_hte_request, 663 .release = tegra_hte_release, 664 .enable = tegra_hte_enable, 665 .disable = tegra_hte_disable, 666 .get_clk_src_info = tegra_hte_clk_src_info, 667 }; 668 669 static void tegra_gte_disable(void *data) 670 { 671 struct platform_device *pdev = data; 672 struct tegra_hte_soc *gs = dev_get_drvdata(&pdev->dev); 673 674 tegra_hte_writel(gs, HTE_TECTRL, 0); 675 } 676 677 static int tegra_get_gpiochip_from_name(struct gpio_chip *chip, void *data) 678 { 679 return !strcmp(chip->label, data); 680 } 681 682 static int tegra_gpiochip_match(struct gpio_chip *chip, void *data) 683 { 684 return chip->fwnode == of_node_to_fwnode(data); 685 } 686 687 static int tegra_hte_probe(struct platform_device *pdev) 688 { 689 int ret; 690 u32 i, slices, val = 0; 691 u32 nlines; 692 struct device *dev; 693 struct tegra_hte_soc *hte_dev; 694 struct hte_chip *gc; 695 struct device_node *gpio_ctrl; 696 697 dev = &pdev->dev; 698 699 hte_dev = devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL); 700 if (!hte_dev) 701 return -ENOMEM; 702 703 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 704 if (!gc) 705 return -ENOMEM; 706 707 dev_set_drvdata(&pdev->dev, hte_dev); 708 hte_dev->prov_data = of_device_get_match_data(&pdev->dev); 709 710 ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); 711 if (ret != 0) 712 slices = hte_dev->prov_data->slices; 713 714 dev_dbg(dev, "slices:%d\n", slices); 715 nlines = slices << 5; 716 717 hte_dev->regs = devm_platform_ioremap_resource(pdev, 0); 718 if (IS_ERR(hte_dev->regs)) 719 return PTR_ERR(hte_dev->regs); 720 721 ret = of_property_read_u32(dev->of_node, "nvidia,int-threshold", 722 &hte_dev->itr_thrshld); 723 if (ret != 0) 724 hte_dev->itr_thrshld = 1; 725 726 hte_dev->sl = devm_kcalloc(dev, slices, sizeof(*hte_dev->sl), 727 GFP_KERNEL); 728 if (!hte_dev->sl) 729 return -ENOMEM; 730 731 ret = platform_get_irq(pdev, 0); 732 if (ret < 0) { 733 dev_err_probe(dev, ret, "failed to get irq\n"); 734 return ret; 735 } 736 hte_dev->hte_irq = ret; 737 ret = devm_request_irq(dev, hte_dev->hte_irq, tegra_hte_isr, 0, 738 dev_name(dev), hte_dev); 739 if (ret < 0) { 740 dev_err(dev, "request irq failed.\n"); 741 return ret; 742 } 743 744 gc->nlines = nlines; 745 gc->ops = &g_ops; 746 gc->dev = dev; 747 gc->data = hte_dev; 748 gc->xlate_of = tegra_hte_line_xlate; 749 gc->xlate_plat = tegra_hte_line_xlate_plat; 750 gc->of_hte_n_cells = 1; 751 752 if (hte_dev->prov_data && 753 hte_dev->prov_data->type == HTE_TEGRA_TYPE_GPIO) { 754 hte_dev->line_data = devm_kcalloc(dev, nlines, 755 sizeof(*hte_dev->line_data), 756 GFP_KERNEL); 757 if (!hte_dev->line_data) 758 return -ENOMEM; 759 760 gc->match_from_linedata = tegra_hte_match_from_linedata; 761 762 if (of_device_is_compatible(dev->of_node, 763 "nvidia,tegra194-gte-aon")) { 764 hte_dev->c = gpiochip_find("tegra194-gpio-aon", 765 tegra_get_gpiochip_from_name); 766 } else { 767 gpio_ctrl = of_parse_phandle(dev->of_node, 768 "nvidia,gpio-controller", 769 0); 770 if (!gpio_ctrl) { 771 dev_err(dev, 772 "gpio controller node not found\n"); 773 return -ENODEV; 774 } 775 776 hte_dev->c = gpiochip_find(gpio_ctrl, 777 tegra_gpiochip_match); 778 of_node_put(gpio_ctrl); 779 } 780 781 if (!hte_dev->c) 782 return dev_err_probe(dev, -EPROBE_DEFER, 783 "wait for gpio controller\n"); 784 } 785 786 hte_dev->chip = gc; 787 788 ret = devm_hte_register_chip(hte_dev->chip); 789 if (ret) { 790 dev_err(gc->dev, "hte chip register failed"); 791 return ret; 792 } 793 794 for (i = 0; i < slices; i++) { 795 hte_dev->sl[i].flags = 0; 796 spin_lock_init(&hte_dev->sl[i].s_lock); 797 } 798 799 val = HTE_TECTRL_ENABLE_ENABLE | 800 (HTE_TECTRL_INTR_ENABLE << HTE_TECTRL_INTR_SHIFT) | 801 (hte_dev->itr_thrshld << HTE_TECTRL_OCCU_SHIFT); 802 tegra_hte_writel(hte_dev, HTE_TECTRL, val); 803 804 ret = devm_add_action_or_reset(&pdev->dev, tegra_gte_disable, pdev); 805 if (ret) 806 return ret; 807 808 dev_dbg(gc->dev, "lines: %d, slices:%d", gc->nlines, slices); 809 810 return 0; 811 } 812 813 static int __maybe_unused tegra_hte_resume_early(struct device *dev) 814 { 815 u32 i; 816 struct tegra_hte_soc *gs = dev_get_drvdata(dev); 817 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; 818 u32 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); 819 820 tegra_hte_writel(gs, HTE_TECTRL, gs->conf_rval); 821 822 for (i = 0; i < slices; i++) { 823 spin_lock(&gs->sl[i].s_lock); 824 tegra_hte_writel(gs, 825 ((i << sl_bit_shift) + HTE_SLICE0_TETEN), 826 gs->sl[i].r_val); 827 clear_bit(HTE_SUSPEND, &gs->sl[i].flags); 828 spin_unlock(&gs->sl[i].s_lock); 829 } 830 831 return 0; 832 } 833 834 static int __maybe_unused tegra_hte_suspend_late(struct device *dev) 835 { 836 u32 i; 837 struct tegra_hte_soc *gs = dev_get_drvdata(dev); 838 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; 839 u32 sl_bit_shift = __builtin_ctz(HTE_SLICE_SIZE); 840 841 gs->conf_rval = tegra_hte_readl(gs, HTE_TECTRL); 842 for (i = 0; i < slices; i++) { 843 spin_lock(&gs->sl[i].s_lock); 844 gs->sl[i].r_val = tegra_hte_readl(gs, 845 ((i << sl_bit_shift) + HTE_SLICE0_TETEN)); 846 set_bit(HTE_SUSPEND, &gs->sl[i].flags); 847 spin_unlock(&gs->sl[i].s_lock); 848 } 849 850 return 0; 851 } 852 853 static const struct dev_pm_ops tegra_hte_pm = { 854 SET_LATE_SYSTEM_SLEEP_PM_OPS(tegra_hte_suspend_late, 855 tegra_hte_resume_early) 856 }; 857 858 static struct platform_driver tegra_hte_driver = { 859 .probe = tegra_hte_probe, 860 .driver = { 861 .name = "tegra_hte", 862 .pm = &tegra_hte_pm, 863 .of_match_table = tegra_hte_of_match, 864 }, 865 }; 866 867 module_platform_driver(tegra_hte_driver); 868 869 MODULE_AUTHOR("Dipen Patel <dipenp@nvidia.com>"); 870 MODULE_DESCRIPTION("NVIDIA Tegra HTE (Hardware Timestamping Engine) driver"); 871 MODULE_LICENSE("GPL"); 872