1 /* 2 * Most ISHTP provider device and ISHTP logic declarations 3 * 4 * Copyright (c) 2003-2016, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef _ISHTP_DEV_H_ 17 #define _ISHTP_DEV_H_ 18 19 #include <linux/types.h> 20 #include <linux/spinlock.h> 21 #include "bus.h" 22 #include "hbm.h" 23 24 #define IPC_PAYLOAD_SIZE 128 25 #define ISHTP_RD_MSG_BUF_SIZE IPC_PAYLOAD_SIZE 26 #define IPC_FULL_MSG_SIZE 132 27 28 /* Number of messages to be held in ISR->BH FIFO */ 29 #define RD_INT_FIFO_SIZE 64 30 31 /* 32 * Number of IPC messages to be held in Tx FIFO, to be sent by ISR - 33 * Tx complete interrupt or RX_COMPLETE handler 34 */ 35 #define IPC_TX_FIFO_SIZE 512 36 37 /* 38 * Number of Maximum ISHTP Clients 39 */ 40 #define ISHTP_CLIENTS_MAX 256 41 42 /* 43 * Number of File descriptors/handles 44 * that can be opened to the driver. 45 * 46 * Limit to 255: 256 Total Clients 47 * minus internal client for ISHTP Bus Messages 48 */ 49 #define ISHTP_MAX_OPEN_HANDLE_COUNT (ISHTP_CLIENTS_MAX - 1) 50 51 /* Internal Clients Number */ 52 #define ISHTP_HOST_CLIENT_ID_ANY (-1) 53 #define ISHTP_HBM_HOST_CLIENT_ID 0 54 55 #define MAX_DMA_DELAY 20 56 57 /* ISHTP device states */ 58 enum ishtp_dev_state { 59 ISHTP_DEV_INITIALIZING = 0, 60 ISHTP_DEV_INIT_CLIENTS, 61 ISHTP_DEV_ENABLED, 62 ISHTP_DEV_RESETTING, 63 ISHTP_DEV_DISABLED, 64 ISHTP_DEV_POWER_DOWN, 65 ISHTP_DEV_POWER_UP 66 }; 67 const char *ishtp_dev_state_str(int state); 68 69 struct ishtp_cl; 70 71 /** 72 * struct ishtp_fw_client - representation of fw client 73 * 74 * @props - client properties 75 * @client_id - fw client id 76 */ 77 struct ishtp_fw_client { 78 struct ishtp_client_properties props; 79 uint8_t client_id; 80 }; 81 82 /* 83 * Control info for IPC messages ISHTP/IPC sending FIFO - 84 * list with inline data buffer 85 * This structure will be filled with parameters submitted 86 * by the caller glue layer 87 * 'buf' may be pointing to the external buffer or to 'inline_data' 88 * 'offset' will be initialized to 0 by submitting 89 * 90 * 'ipc_send_compl' is intended for use by clients that send fragmented 91 * messages. When a fragment is sent down to IPC msg regs, 92 * it will be called. 93 * If it has more fragments to send, it will do it. With last fragment 94 * it will send appropriate ISHTP "message-complete" flag. 95 * It will remove the outstanding message 96 * (mark outstanding buffer as available). 97 * If counting flow control is in work and there are more flow control 98 * credits, it can put the next client message queued in cl. 99 * structure for IPC processing. 100 * 101 */ 102 struct wr_msg_ctl_info { 103 /* Will be called with 'ipc_send_compl_prm' as parameter */ 104 void (*ipc_send_compl)(void *); 105 106 void *ipc_send_compl_prm; 107 size_t length; 108 struct list_head link; 109 unsigned char inline_data[IPC_FULL_MSG_SIZE]; 110 }; 111 112 /* 113 * The ISHTP layer talks to hardware IPC message using the following 114 * callbacks 115 */ 116 struct ishtp_hw_ops { 117 int (*hw_reset)(struct ishtp_device *dev); 118 int (*ipc_reset)(struct ishtp_device *dev); 119 uint32_t (*ipc_get_header)(struct ishtp_device *dev, int length, 120 int busy); 121 int (*write)(struct ishtp_device *dev, 122 void (*ipc_send_compl)(void *), void *ipc_send_compl_prm, 123 unsigned char *msg, int length); 124 uint32_t (*ishtp_read_hdr)(const struct ishtp_device *dev); 125 int (*ishtp_read)(struct ishtp_device *dev, unsigned char *buffer, 126 unsigned long buffer_length); 127 uint32_t (*get_fw_status)(struct ishtp_device *dev); 128 void (*sync_fw_clock)(struct ishtp_device *dev); 129 }; 130 131 /** 132 * struct ishtp_device - ISHTP private device struct 133 */ 134 struct ishtp_device { 135 struct device *devc; /* pointer to lowest device */ 136 struct pci_dev *pdev; /* PCI device to get device ids */ 137 138 /* waitq for waiting for suspend response */ 139 wait_queue_head_t suspend_wait; 140 bool suspend_flag; /* Suspend is active */ 141 142 /* waitq for waiting for resume response */ 143 wait_queue_head_t resume_wait; 144 bool resume_flag; /*Resume is active */ 145 146 /* 147 * lock for the device, for everything that doesn't have 148 * a dedicated spinlock 149 */ 150 spinlock_t device_lock; 151 152 bool recvd_hw_ready; 153 struct hbm_version version; 154 int transfer_path; /* Choice of transfer path: IPC or DMA */ 155 156 /* ishtp device states */ 157 enum ishtp_dev_state dev_state; 158 enum ishtp_hbm_state hbm_state; 159 160 /* driver read queue */ 161 struct ishtp_cl_rb read_list; 162 spinlock_t read_list_spinlock; 163 164 /* list of ishtp_cl's */ 165 struct list_head cl_list; 166 spinlock_t cl_list_lock; 167 long open_handle_count; 168 169 /* List of bus devices */ 170 struct list_head device_list; 171 spinlock_t device_list_lock; 172 173 /* waiting queues for receive message from FW */ 174 wait_queue_head_t wait_hw_ready; 175 wait_queue_head_t wait_hbm_recvd_msg; 176 177 /* FIFO for input messages for BH processing */ 178 unsigned char rd_msg_fifo[RD_INT_FIFO_SIZE * IPC_PAYLOAD_SIZE]; 179 unsigned int rd_msg_fifo_head, rd_msg_fifo_tail; 180 spinlock_t rd_msg_spinlock; 181 struct work_struct bh_hbm_work; 182 183 /* IPC write queue */ 184 struct list_head wr_processing_list, wr_free_list; 185 /* For both processing list and free list */ 186 spinlock_t wr_processing_spinlock; 187 188 struct ishtp_fw_client *fw_clients; /*Note:memory has to be allocated*/ 189 DECLARE_BITMAP(fw_clients_map, ISHTP_CLIENTS_MAX); 190 DECLARE_BITMAP(host_clients_map, ISHTP_CLIENTS_MAX); 191 uint8_t fw_clients_num; 192 uint8_t fw_client_presentation_num; 193 uint8_t fw_client_index; 194 spinlock_t fw_clients_lock; 195 196 /* TX DMA buffers and slots */ 197 int ishtp_host_dma_enabled; 198 void *ishtp_host_dma_tx_buf; 199 unsigned int ishtp_host_dma_tx_buf_size; 200 uint64_t ishtp_host_dma_tx_buf_phys; 201 int ishtp_dma_num_slots; 202 203 /* map of 4k blocks in Tx dma buf: 0-free, 1-used */ 204 uint8_t *ishtp_dma_tx_map; 205 spinlock_t ishtp_dma_tx_lock; 206 207 /* RX DMA buffers and slots */ 208 void *ishtp_host_dma_rx_buf; 209 unsigned int ishtp_host_dma_rx_buf_size; 210 uint64_t ishtp_host_dma_rx_buf_phys; 211 212 /* Dump to trace buffers if enabled*/ 213 __printf(2, 3) void (*print_log)(struct ishtp_device *dev, 214 const char *format, ...); 215 216 /* Debug stats */ 217 unsigned int ipc_rx_cnt; 218 unsigned long long ipc_rx_bytes_cnt; 219 unsigned int ipc_tx_cnt; 220 unsigned long long ipc_tx_bytes_cnt; 221 222 const struct ishtp_hw_ops *ops; 223 size_t mtu; 224 uint32_t ishtp_msg_hdr; 225 char hw[0] __aligned(sizeof(void *)); 226 }; 227 228 static inline unsigned long ishtp_secs_to_jiffies(unsigned long sec) 229 { 230 return msecs_to_jiffies(sec * MSEC_PER_SEC); 231 } 232 233 /* 234 * Register Access Function 235 */ 236 static inline int ish_ipc_reset(struct ishtp_device *dev) 237 { 238 return dev->ops->ipc_reset(dev); 239 } 240 241 /* Exported function */ 242 void ishtp_device_init(struct ishtp_device *dev); 243 int ishtp_start(struct ishtp_device *dev); 244 245 #endif /*_ISHTP_DEV_H_*/ 246