xref: /openbmc/linux/drivers/gpu/ipu-v3/ipu-prv.h (revision d2999e1b)
1 /*
2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation; either version 2 of the License, or (at your
8  * option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13  * for more details.
14  */
15 #ifndef __IPU_PRV_H__
16 #define __IPU_PRV_H__
17 
18 struct ipu_soc;
19 
20 #include <linux/types.h>
21 #include <linux/device.h>
22 #include <linux/clk.h>
23 #include <linux/platform_device.h>
24 
25 #include <video/imx-ipu-v3.h>
26 
27 #define IPUV3_CHANNEL_CSI0			 0
28 #define IPUV3_CHANNEL_CSI1			 1
29 #define IPUV3_CHANNEL_CSI2			 2
30 #define IPUV3_CHANNEL_CSI3			 3
31 #define IPUV3_CHANNEL_MEM_BG_SYNC		23
32 #define IPUV3_CHANNEL_MEM_FG_SYNC		27
33 #define IPUV3_CHANNEL_MEM_DC_SYNC		28
34 #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA		31
35 #define IPUV3_CHANNEL_MEM_DC_ASYNC		41
36 #define IPUV3_CHANNEL_ROT_ENC_MEM		45
37 #define IPUV3_CHANNEL_ROT_VF_MEM		46
38 #define IPUV3_CHANNEL_ROT_PP_MEM		47
39 #define IPUV3_CHANNEL_ROT_ENC_MEM_OUT		48
40 #define IPUV3_CHANNEL_ROT_VF_MEM_OUT		49
41 #define IPUV3_CHANNEL_ROT_PP_MEM_OUT		50
42 #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA		51
43 
44 #define IPU_MCU_T_DEFAULT	8
45 #define IPU_CM_IDMAC_REG_OFS	0x00008000
46 #define IPU_CM_IC_REG_OFS	0x00020000
47 #define IPU_CM_IRT_REG_OFS	0x00028000
48 #define IPU_CM_CSI0_REG_OFS	0x00030000
49 #define IPU_CM_CSI1_REG_OFS	0x00038000
50 #define IPU_CM_SMFC_REG_OFS	0x00050000
51 #define IPU_CM_DC_REG_OFS	0x00058000
52 #define IPU_CM_DMFC_REG_OFS	0x00060000
53 
54 /* Register addresses */
55 /* IPU Common registers */
56 #define IPU_CM_REG(offset)	(offset)
57 
58 #define IPU_CONF			IPU_CM_REG(0)
59 
60 #define IPU_SRM_PRI1			IPU_CM_REG(0x00a0)
61 #define IPU_SRM_PRI2			IPU_CM_REG(0x00a4)
62 #define IPU_FS_PROC_FLOW1		IPU_CM_REG(0x00a8)
63 #define IPU_FS_PROC_FLOW2		IPU_CM_REG(0x00ac)
64 #define IPU_FS_PROC_FLOW3		IPU_CM_REG(0x00b0)
65 #define IPU_FS_DISP_FLOW1		IPU_CM_REG(0x00b4)
66 #define IPU_FS_DISP_FLOW2		IPU_CM_REG(0x00b8)
67 #define IPU_SKIP			IPU_CM_REG(0x00bc)
68 #define IPU_DISP_ALT_CONF		IPU_CM_REG(0x00c0)
69 #define IPU_DISP_GEN			IPU_CM_REG(0x00c4)
70 #define IPU_DISP_ALT1			IPU_CM_REG(0x00c8)
71 #define IPU_DISP_ALT2			IPU_CM_REG(0x00cc)
72 #define IPU_DISP_ALT3			IPU_CM_REG(0x00d0)
73 #define IPU_DISP_ALT4			IPU_CM_REG(0x00d4)
74 #define IPU_SNOOP			IPU_CM_REG(0x00d8)
75 #define IPU_MEM_RST			IPU_CM_REG(0x00dc)
76 #define IPU_PM				IPU_CM_REG(0x00e0)
77 #define IPU_GPR				IPU_CM_REG(0x00e4)
78 #define IPU_CHA_DB_MODE_SEL(ch)		IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
79 #define IPU_ALT_CHA_DB_MODE_SEL(ch)	IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
80 #define IPU_CHA_CUR_BUF(ch)		IPU_CM_REG(0x023C + 4 * ((ch) / 32))
81 #define IPU_ALT_CUR_BUF0		IPU_CM_REG(0x0244)
82 #define IPU_ALT_CUR_BUF1		IPU_CM_REG(0x0248)
83 #define IPU_SRM_STAT			IPU_CM_REG(0x024C)
84 #define IPU_PROC_TASK_STAT		IPU_CM_REG(0x0250)
85 #define IPU_DISP_TASK_STAT		IPU_CM_REG(0x0254)
86 #define IPU_CHA_BUF0_RDY(ch)		IPU_CM_REG(0x0268 + 4 * ((ch) / 32))
87 #define IPU_CHA_BUF1_RDY(ch)		IPU_CM_REG(0x0270 + 4 * ((ch) / 32))
88 #define IPU_ALT_CHA_BUF0_RDY(ch)	IPU_CM_REG(0x0278 + 4 * ((ch) / 32))
89 #define IPU_ALT_CHA_BUF1_RDY(ch)	IPU_CM_REG(0x0280 + 4 * ((ch) / 32))
90 
91 #define IPU_INT_CTRL(n)		IPU_CM_REG(0x003C + 4 * (n))
92 #define IPU_INT_STAT(n)		IPU_CM_REG(0x0200 + 4 * (n))
93 
94 #define IPU_DI0_COUNTER_RELEASE			(1 << 24)
95 #define IPU_DI1_COUNTER_RELEASE			(1 << 25)
96 
97 #define IPU_IDMAC_REG(offset)	(offset)
98 
99 #define IDMAC_CONF			IPU_IDMAC_REG(0x0000)
100 #define IDMAC_CHA_EN(ch)		IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32))
101 #define IDMAC_SEP_ALPHA			IPU_IDMAC_REG(0x000c)
102 #define IDMAC_ALT_SEP_ALPHA		IPU_IDMAC_REG(0x0010)
103 #define IDMAC_CHA_PRI(ch)		IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32))
104 #define IDMAC_WM_EN(ch)			IPU_IDMAC_REG(0x001c + 4 * ((ch) / 32))
105 #define IDMAC_CH_LOCK_EN_1		IPU_IDMAC_REG(0x0024)
106 #define IDMAC_CH_LOCK_EN_2		IPU_IDMAC_REG(0x0028)
107 #define IDMAC_SUB_ADDR_0		IPU_IDMAC_REG(0x002c)
108 #define IDMAC_SUB_ADDR_1		IPU_IDMAC_REG(0x0030)
109 #define IDMAC_SUB_ADDR_2		IPU_IDMAC_REG(0x0034)
110 #define IDMAC_BAND_EN(ch)		IPU_IDMAC_REG(0x0040 + 4 * ((ch) / 32))
111 #define IDMAC_CHA_BUSY(ch)		IPU_IDMAC_REG(0x0100 + 4 * ((ch) / 32))
112 
113 #define IPU_NUM_IRQS	(32 * 15)
114 
115 enum ipu_modules {
116 	IPU_CONF_CSI0_EN		= (1 << 0),
117 	IPU_CONF_CSI1_EN		= (1 << 1),
118 	IPU_CONF_IC_EN			= (1 << 2),
119 	IPU_CONF_ROT_EN			= (1 << 3),
120 	IPU_CONF_ISP_EN			= (1 << 4),
121 	IPU_CONF_DP_EN			= (1 << 5),
122 	IPU_CONF_DI0_EN			= (1 << 6),
123 	IPU_CONF_DI1_EN			= (1 << 7),
124 	IPU_CONF_SMFC_EN		= (1 << 8),
125 	IPU_CONF_DC_EN			= (1 << 9),
126 	IPU_CONF_DMFC_EN		= (1 << 10),
127 
128 	IPU_CONF_VDI_EN			= (1 << 12),
129 
130 	IPU_CONF_IDMAC_DIS		= (1 << 22),
131 
132 	IPU_CONF_IC_DMFC_SEL		= (1 << 25),
133 	IPU_CONF_IC_DMFC_SYNC		= (1 << 26),
134 	IPU_CONF_VDI_DMFC_SYNC		= (1 << 27),
135 
136 	IPU_CONF_CSI0_DATA_SOURCE	= (1 << 28),
137 	IPU_CONF_CSI1_DATA_SOURCE	= (1 << 29),
138 	IPU_CONF_IC_INPUT		= (1 << 30),
139 	IPU_CONF_CSI_SEL		= (1 << 31),
140 };
141 
142 struct ipuv3_channel {
143 	unsigned int num;
144 
145 	bool enabled;
146 	bool busy;
147 
148 	struct ipu_soc *ipu;
149 };
150 
151 struct ipu_dc_priv;
152 struct ipu_dmfc_priv;
153 struct ipu_di;
154 struct ipu_smfc_priv;
155 
156 struct ipu_devtype;
157 
158 struct ipu_soc {
159 	struct device		*dev;
160 	const struct ipu_devtype	*devtype;
161 	enum ipuv3_type		ipu_type;
162 	spinlock_t		lock;
163 	struct mutex		channel_lock;
164 
165 	void __iomem		*cm_reg;
166 	void __iomem		*idmac_reg;
167 	struct ipu_ch_param __iomem	*cpmem_base;
168 
169 	int			usecount;
170 
171 	struct clk		*clk;
172 
173 	struct ipuv3_channel	channel[64];
174 
175 	int			irq_sync;
176 	int			irq_err;
177 	struct irq_domain	*domain;
178 
179 	struct ipu_dc_priv	*dc_priv;
180 	struct ipu_dp_priv	*dp_priv;
181 	struct ipu_dmfc_priv	*dmfc_priv;
182 	struct ipu_di		*di_priv[2];
183 	struct ipu_smfc_priv	*smfc_priv;
184 };
185 
186 void ipu_srm_dp_sync_update(struct ipu_soc *ipu);
187 
188 int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
189 int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
190 
191 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
192 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms);
193 
194 int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
195 		unsigned long base, u32 module, struct clk *ipu_clk);
196 void ipu_di_exit(struct ipu_soc *ipu, int id);
197 
198 int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
199 		struct clk *ipu_clk);
200 void ipu_dmfc_exit(struct ipu_soc *ipu);
201 
202 int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
203 void ipu_dp_exit(struct ipu_soc *ipu);
204 
205 int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
206 		unsigned long template_base);
207 void ipu_dc_exit(struct ipu_soc *ipu);
208 
209 int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
210 void ipu_cpmem_exit(struct ipu_soc *ipu);
211 
212 int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
213 void ipu_smfc_exit(struct ipu_soc *ipu);
214 
215 #endif				/* __IPU_PRV_H__ */
216