1 /* 2 * Copyright (c) 2017 Lucas Stach, Pengutronix 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 */ 13 14 #include <drm/drm_fourcc.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 #include <linux/genalloc.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <video/imx-ipu-v3.h> 22 23 #include "ipu-prv.h" 24 25 #define IPU_PRE_MAX_WIDTH 2048 26 #define IPU_PRE_NUM_SCANLINES 8 27 28 #define IPU_PRE_CTRL 0x000 29 #define IPU_PRE_CTRL_SET 0x004 30 #define IPU_PRE_CTRL_ENABLE (1 << 0) 31 #define IPU_PRE_CTRL_BLOCK_EN (1 << 1) 32 #define IPU_PRE_CTRL_BLOCK_16 (1 << 2) 33 #define IPU_PRE_CTRL_SDW_UPDATE (1 << 4) 34 #define IPU_PRE_CTRL_VFLIP (1 << 5) 35 #define IPU_PRE_CTRL_SO (1 << 6) 36 #define IPU_PRE_CTRL_INTERLACED_FIELD (1 << 7) 37 #define IPU_PRE_CTRL_HANDSHAKE_EN (1 << 8) 38 #define IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v) ((v & 0x3) << 9) 39 #define IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN (1 << 11) 40 #define IPU_PRE_CTRL_EN_REPEAT (1 << 28) 41 #define IPU_PRE_CTRL_TPR_REST_SEL (1 << 29) 42 #define IPU_PRE_CTRL_CLKGATE (1 << 30) 43 #define IPU_PRE_CTRL_SFTRST (1 << 31) 44 45 #define IPU_PRE_CUR_BUF 0x030 46 47 #define IPU_PRE_NEXT_BUF 0x040 48 49 #define IPU_PRE_TPR_CTRL 0x070 50 #define IPU_PRE_TPR_CTRL_TILE_FORMAT(v) ((v & 0xff) << 0) 51 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK 0xff 52 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT (1 << 0) 53 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SPLIT_BUF (1 << 4) 54 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF (1 << 5) 55 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED (1 << 6) 56 57 #define IPU_PRE_PREFETCH_ENG_CTRL 0x080 58 #define IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN (1 << 0) 59 #define IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v) ((v & 0x7) << 1) 60 #define IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v) ((v & 0x3) << 4) 61 #define IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v) ((v & 0x7) << 8) 62 #define IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS (1 << 11) 63 #define IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE (1 << 12) 64 #define IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP (1 << 14) 65 #define IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN (1 << 15) 66 67 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE 0x0a0 68 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v) ((v & 0xffff) << 0) 69 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v) ((v & 0xffff) << 16) 70 71 #define IPU_PRE_PREFETCH_ENG_PITCH 0x0d0 72 #define IPU_PRE_PREFETCH_ENG_PITCH_Y(v) ((v & 0xffff) << 0) 73 #define IPU_PRE_PREFETCH_ENG_PITCH_UV(v) ((v & 0xffff) << 16) 74 75 #define IPU_PRE_STORE_ENG_CTRL 0x110 76 #define IPU_PRE_STORE_ENG_CTRL_STORE_EN (1 << 0) 77 #define IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v) ((v & 0x7) << 1) 78 #define IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v) ((v & 0x3) << 4) 79 80 #define IPU_PRE_STORE_ENG_STATUS 0x120 81 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK 0xffff 82 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT 0 83 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK 0x3fff 84 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT 16 85 #define IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL (1 << 30) 86 #define IPU_PRE_STORE_ENG_STATUS_STORE_FIELD (1 << 31) 87 88 #define IPU_PRE_STORE_ENG_SIZE 0x130 89 #define IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v) ((v & 0xffff) << 0) 90 #define IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v) ((v & 0xffff) << 16) 91 92 #define IPU_PRE_STORE_ENG_PITCH 0x140 93 #define IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v) ((v & 0xffff) << 0) 94 95 #define IPU_PRE_STORE_ENG_ADDR 0x150 96 97 struct ipu_pre { 98 struct list_head list; 99 struct device *dev; 100 101 void __iomem *regs; 102 struct clk *clk_axi; 103 struct gen_pool *iram; 104 105 dma_addr_t buffer_paddr; 106 void *buffer_virt; 107 bool in_use; 108 unsigned int safe_window_end; 109 }; 110 111 static DEFINE_MUTEX(ipu_pre_list_mutex); 112 static LIST_HEAD(ipu_pre_list); 113 static int available_pres; 114 115 int ipu_pre_get_available_count(void) 116 { 117 return available_pres; 118 } 119 120 struct ipu_pre * 121 ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index) 122 { 123 struct device_node *pre_node = of_parse_phandle(dev->of_node, 124 name, index); 125 struct ipu_pre *pre; 126 127 mutex_lock(&ipu_pre_list_mutex); 128 list_for_each_entry(pre, &ipu_pre_list, list) { 129 if (pre_node == pre->dev->of_node) { 130 mutex_unlock(&ipu_pre_list_mutex); 131 device_link_add(dev, pre->dev, DL_FLAG_AUTOREMOVE); 132 return pre; 133 } 134 } 135 mutex_unlock(&ipu_pre_list_mutex); 136 137 return NULL; 138 } 139 140 int ipu_pre_get(struct ipu_pre *pre) 141 { 142 u32 val; 143 144 if (pre->in_use) 145 return -EBUSY; 146 147 /* first get the engine out of reset and remove clock gating */ 148 writel(0, pre->regs + IPU_PRE_CTRL); 149 150 /* init defaults that should be applied to all streams */ 151 val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN | 152 IPU_PRE_CTRL_HANDSHAKE_EN | 153 IPU_PRE_CTRL_TPR_REST_SEL | 154 IPU_PRE_CTRL_SDW_UPDATE; 155 writel(val, pre->regs + IPU_PRE_CTRL); 156 157 pre->in_use = true; 158 return 0; 159 } 160 161 void ipu_pre_put(struct ipu_pre *pre) 162 { 163 writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL); 164 165 pre->in_use = false; 166 } 167 168 void ipu_pre_configure(struct ipu_pre *pre, unsigned int width, 169 unsigned int height, unsigned int stride, u32 format, 170 uint64_t modifier, unsigned int bufaddr) 171 { 172 const struct drm_format_info *info = drm_format_info(format); 173 u32 active_bpp = info->cpp[0] >> 1; 174 u32 val; 175 176 /* calculate safe window for ctrl register updates */ 177 if (modifier == DRM_FORMAT_MOD_LINEAR) 178 pre->safe_window_end = height - 2; 179 else 180 pre->safe_window_end = DIV_ROUND_UP(height, 4) - 1; 181 182 writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF); 183 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); 184 185 val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) | 186 IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) | 187 IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) | 188 IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS | 189 IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN; 190 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL); 191 192 val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) | 193 IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height); 194 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE); 195 196 val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride); 197 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH); 198 199 val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) | 200 IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) | 201 IPU_PRE_STORE_ENG_CTRL_STORE_EN; 202 writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL); 203 204 val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) | 205 IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height); 206 writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE); 207 208 val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride); 209 writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH); 210 211 writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR); 212 213 val = readl(pre->regs + IPU_PRE_TPR_CTRL); 214 val &= ~IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK; 215 if (modifier != DRM_FORMAT_MOD_LINEAR) { 216 /* only support single buffer formats for now */ 217 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF; 218 if (modifier == DRM_FORMAT_MOD_VIVANTE_SUPER_TILED) 219 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED; 220 if (info->cpp[0] == 2) 221 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT; 222 } 223 writel(val, pre->regs + IPU_PRE_TPR_CTRL); 224 225 val = readl(pre->regs + IPU_PRE_CTRL); 226 val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE | 227 IPU_PRE_CTRL_SDW_UPDATE; 228 if (modifier == DRM_FORMAT_MOD_LINEAR) 229 val &= ~IPU_PRE_CTRL_BLOCK_EN; 230 else 231 val |= IPU_PRE_CTRL_BLOCK_EN; 232 writel(val, pre->regs + IPU_PRE_CTRL); 233 } 234 235 void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr) 236 { 237 unsigned long timeout = jiffies + msecs_to_jiffies(5); 238 unsigned short current_yblock; 239 u32 val; 240 241 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); 242 243 do { 244 if (time_after(jiffies, timeout)) { 245 dev_warn(pre->dev, "timeout waiting for PRE safe window\n"); 246 return; 247 } 248 249 val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS); 250 current_yblock = 251 (val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) & 252 IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK; 253 } while (current_yblock == 0 || current_yblock >= pre->safe_window_end); 254 255 writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET); 256 } 257 258 u32 ipu_pre_get_baddr(struct ipu_pre *pre) 259 { 260 return (u32)pre->buffer_paddr; 261 } 262 263 static int ipu_pre_probe(struct platform_device *pdev) 264 { 265 struct device *dev = &pdev->dev; 266 struct resource *res; 267 struct ipu_pre *pre; 268 269 pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL); 270 if (!pre) 271 return -ENOMEM; 272 273 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 274 pre->regs = devm_ioremap_resource(&pdev->dev, res); 275 if (IS_ERR(pre->regs)) 276 return PTR_ERR(pre->regs); 277 278 pre->clk_axi = devm_clk_get(dev, "axi"); 279 if (IS_ERR(pre->clk_axi)) 280 return PTR_ERR(pre->clk_axi); 281 282 pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0); 283 if (!pre->iram) 284 return -EPROBE_DEFER; 285 286 /* 287 * Allocate IRAM buffer with maximum size. This could be made dynamic, 288 * but as there is no other user of this IRAM region and we can fit all 289 * max sized buffers into it, there is no need yet. 290 */ 291 pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH * 292 IPU_PRE_NUM_SCANLINES * 4, 293 &pre->buffer_paddr); 294 if (!pre->buffer_virt) 295 return -ENOMEM; 296 297 clk_prepare_enable(pre->clk_axi); 298 299 pre->dev = dev; 300 platform_set_drvdata(pdev, pre); 301 mutex_lock(&ipu_pre_list_mutex); 302 list_add(&pre->list, &ipu_pre_list); 303 available_pres++; 304 mutex_unlock(&ipu_pre_list_mutex); 305 306 return 0; 307 } 308 309 static int ipu_pre_remove(struct platform_device *pdev) 310 { 311 struct ipu_pre *pre = platform_get_drvdata(pdev); 312 313 mutex_lock(&ipu_pre_list_mutex); 314 list_del(&pre->list); 315 available_pres--; 316 mutex_unlock(&ipu_pre_list_mutex); 317 318 clk_disable_unprepare(pre->clk_axi); 319 320 if (pre->buffer_virt) 321 gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt, 322 IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4); 323 return 0; 324 } 325 326 static const struct of_device_id ipu_pre_dt_ids[] = { 327 { .compatible = "fsl,imx6qp-pre", }, 328 { /* sentinel */ }, 329 }; 330 331 struct platform_driver ipu_pre_drv = { 332 .probe = ipu_pre_probe, 333 .remove = ipu_pre_remove, 334 .driver = { 335 .name = "imx-ipu-pre", 336 .of_match_table = ipu_pre_dt_ids, 337 }, 338 }; 339