1 /* 2 * Copyright (c) 2017 Lucas Stach, Pengutronix 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 */ 13 14 #include <drm/drm_fourcc.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 #include <linux/genalloc.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <video/imx-ipu-v3.h> 22 23 #include "ipu-prv.h" 24 25 #define IPU_PRE_MAX_WIDTH 2048 26 #define IPU_PRE_NUM_SCANLINES 8 27 28 #define IPU_PRE_CTRL 0x000 29 #define IPU_PRE_CTRL_SET 0x004 30 #define IPU_PRE_CTRL_ENABLE (1 << 0) 31 #define IPU_PRE_CTRL_BLOCK_EN (1 << 1) 32 #define IPU_PRE_CTRL_BLOCK_16 (1 << 2) 33 #define IPU_PRE_CTRL_SDW_UPDATE (1 << 4) 34 #define IPU_PRE_CTRL_VFLIP (1 << 5) 35 #define IPU_PRE_CTRL_SO (1 << 6) 36 #define IPU_PRE_CTRL_INTERLACED_FIELD (1 << 7) 37 #define IPU_PRE_CTRL_HANDSHAKE_EN (1 << 8) 38 #define IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v) ((v & 0x3) << 9) 39 #define IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN (1 << 11) 40 #define IPU_PRE_CTRL_EN_REPEAT (1 << 28) 41 #define IPU_PRE_CTRL_TPR_REST_SEL (1 << 29) 42 #define IPU_PRE_CTRL_CLKGATE (1 << 30) 43 #define IPU_PRE_CTRL_SFTRST (1 << 31) 44 45 #define IPU_PRE_CUR_BUF 0x030 46 47 #define IPU_PRE_NEXT_BUF 0x040 48 49 #define IPU_PRE_TPR_CTRL 0x070 50 #define IPU_PRE_TPR_CTRL_TILE_FORMAT(v) ((v & 0xff) << 0) 51 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK 0xff 52 53 #define IPU_PRE_PREFETCH_ENG_CTRL 0x080 54 #define IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN (1 << 0) 55 #define IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v) ((v & 0x7) << 1) 56 #define IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v) ((v & 0x3) << 4) 57 #define IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v) ((v & 0x7) << 8) 58 #define IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS (1 << 11) 59 #define IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE (1 << 12) 60 #define IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP (1 << 14) 61 #define IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN (1 << 15) 62 63 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE 0x0a0 64 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v) ((v & 0xffff) << 0) 65 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v) ((v & 0xffff) << 16) 66 67 #define IPU_PRE_PREFETCH_ENG_PITCH 0x0d0 68 #define IPU_PRE_PREFETCH_ENG_PITCH_Y(v) ((v & 0xffff) << 0) 69 #define IPU_PRE_PREFETCH_ENG_PITCH_UV(v) ((v & 0xffff) << 16) 70 71 #define IPU_PRE_STORE_ENG_CTRL 0x110 72 #define IPU_PRE_STORE_ENG_CTRL_STORE_EN (1 << 0) 73 #define IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v) ((v & 0x7) << 1) 74 #define IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v) ((v & 0x3) << 4) 75 76 #define IPU_PRE_STORE_ENG_STATUS 0x120 77 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK 0xffff 78 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT 0 79 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK 0x3fff 80 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT 16 81 #define IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL (1 << 30) 82 #define IPU_PRE_STORE_ENG_STATUS_STORE_FIELD (1 << 31) 83 84 #define IPU_PRE_STORE_ENG_SIZE 0x130 85 #define IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v) ((v & 0xffff) << 0) 86 #define IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v) ((v & 0xffff) << 16) 87 88 #define IPU_PRE_STORE_ENG_PITCH 0x140 89 #define IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v) ((v & 0xffff) << 0) 90 91 #define IPU_PRE_STORE_ENG_ADDR 0x150 92 93 struct ipu_pre { 94 struct list_head list; 95 struct device *dev; 96 97 void __iomem *regs; 98 struct clk *clk_axi; 99 struct gen_pool *iram; 100 101 dma_addr_t buffer_paddr; 102 void *buffer_virt; 103 bool in_use; 104 unsigned int safe_window_end; 105 }; 106 107 static DEFINE_MUTEX(ipu_pre_list_mutex); 108 static LIST_HEAD(ipu_pre_list); 109 static int available_pres; 110 111 int ipu_pre_get_available_count(void) 112 { 113 return available_pres; 114 } 115 116 struct ipu_pre * 117 ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index) 118 { 119 struct device_node *pre_node = of_parse_phandle(dev->of_node, 120 name, index); 121 struct ipu_pre *pre; 122 123 mutex_lock(&ipu_pre_list_mutex); 124 list_for_each_entry(pre, &ipu_pre_list, list) { 125 if (pre_node == pre->dev->of_node) { 126 mutex_unlock(&ipu_pre_list_mutex); 127 device_link_add(dev, pre->dev, DL_FLAG_AUTOREMOVE); 128 return pre; 129 } 130 } 131 mutex_unlock(&ipu_pre_list_mutex); 132 133 return NULL; 134 } 135 136 int ipu_pre_get(struct ipu_pre *pre) 137 { 138 u32 val; 139 140 if (pre->in_use) 141 return -EBUSY; 142 143 /* first get the engine out of reset and remove clock gating */ 144 writel(0, pre->regs + IPU_PRE_CTRL); 145 146 /* init defaults that should be applied to all streams */ 147 val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN | 148 IPU_PRE_CTRL_HANDSHAKE_EN | 149 IPU_PRE_CTRL_TPR_REST_SEL | 150 IPU_PRE_CTRL_BLOCK_16 | IPU_PRE_CTRL_SDW_UPDATE; 151 writel(val, pre->regs + IPU_PRE_CTRL); 152 153 pre->in_use = true; 154 return 0; 155 } 156 157 void ipu_pre_put(struct ipu_pre *pre) 158 { 159 writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL); 160 161 pre->in_use = false; 162 } 163 164 void ipu_pre_configure(struct ipu_pre *pre, unsigned int width, 165 unsigned int height, unsigned int stride, u32 format, 166 unsigned int bufaddr) 167 { 168 const struct drm_format_info *info = drm_format_info(format); 169 u32 active_bpp = info->cpp[0] >> 1; 170 u32 val; 171 172 /* calculate safe window for ctrl register updates */ 173 pre->safe_window_end = height - 2; 174 175 writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF); 176 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); 177 178 val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) | 179 IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) | 180 IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) | 181 IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS | 182 IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN; 183 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL); 184 185 val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) | 186 IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height); 187 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE); 188 189 val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride); 190 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH); 191 192 val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) | 193 IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) | 194 IPU_PRE_STORE_ENG_CTRL_STORE_EN; 195 writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL); 196 197 val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) | 198 IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height); 199 writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE); 200 201 val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride); 202 writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH); 203 204 writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR); 205 206 val = readl(pre->regs + IPU_PRE_CTRL); 207 val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE | 208 IPU_PRE_CTRL_SDW_UPDATE; 209 writel(val, pre->regs + IPU_PRE_CTRL); 210 } 211 212 void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr) 213 { 214 unsigned long timeout = jiffies + msecs_to_jiffies(5); 215 unsigned short current_yblock; 216 u32 val; 217 218 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); 219 220 do { 221 if (time_after(jiffies, timeout)) { 222 dev_warn(pre->dev, "timeout waiting for PRE safe window\n"); 223 return; 224 } 225 226 val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS); 227 current_yblock = 228 (val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) & 229 IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK; 230 } while (current_yblock == 0 || current_yblock >= pre->safe_window_end); 231 232 writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET); 233 } 234 235 u32 ipu_pre_get_baddr(struct ipu_pre *pre) 236 { 237 return (u32)pre->buffer_paddr; 238 } 239 240 static int ipu_pre_probe(struct platform_device *pdev) 241 { 242 struct device *dev = &pdev->dev; 243 struct resource *res; 244 struct ipu_pre *pre; 245 246 pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL); 247 if (!pre) 248 return -ENOMEM; 249 250 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 251 pre->regs = devm_ioremap_resource(&pdev->dev, res); 252 if (IS_ERR(pre->regs)) 253 return PTR_ERR(pre->regs); 254 255 pre->clk_axi = devm_clk_get(dev, "axi"); 256 if (IS_ERR(pre->clk_axi)) 257 return PTR_ERR(pre->clk_axi); 258 259 pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0); 260 if (!pre->iram) 261 return -EPROBE_DEFER; 262 263 /* 264 * Allocate IRAM buffer with maximum size. This could be made dynamic, 265 * but as there is no other user of this IRAM region and we can fit all 266 * max sized buffers into it, there is no need yet. 267 */ 268 pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH * 269 IPU_PRE_NUM_SCANLINES * 4, 270 &pre->buffer_paddr); 271 if (!pre->buffer_virt) 272 return -ENOMEM; 273 274 clk_prepare_enable(pre->clk_axi); 275 276 pre->dev = dev; 277 platform_set_drvdata(pdev, pre); 278 mutex_lock(&ipu_pre_list_mutex); 279 list_add(&pre->list, &ipu_pre_list); 280 available_pres++; 281 mutex_unlock(&ipu_pre_list_mutex); 282 283 return 0; 284 } 285 286 static int ipu_pre_remove(struct platform_device *pdev) 287 { 288 struct ipu_pre *pre = platform_get_drvdata(pdev); 289 290 mutex_lock(&ipu_pre_list_mutex); 291 list_del(&pre->list); 292 available_pres--; 293 mutex_unlock(&ipu_pre_list_mutex); 294 295 clk_disable_unprepare(pre->clk_axi); 296 297 if (pre->buffer_virt) 298 gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt, 299 IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4); 300 return 0; 301 } 302 303 static const struct of_device_id ipu_pre_dt_ids[] = { 304 { .compatible = "fsl,imx6qp-pre", }, 305 { /* sentinel */ }, 306 }; 307 308 struct platform_driver ipu_pre_drv = { 309 .probe = ipu_pre_probe, 310 .remove = ipu_pre_remove, 311 .driver = { 312 .name = "imx-ipu-pre", 313 .of_match_table = ipu_pre_dt_ids, 314 }, 315 }; 316