1 /* 2 * Copyright (C) 2012-2016 Mentor Graphics Inc. 3 * 4 * Queued image conversion support, with tiling and rotation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include <linux/interrupt.h> 18 #include <linux/dma-mapping.h> 19 #include <video/imx-ipu-image-convert.h> 20 #include "ipu-prv.h" 21 22 /* 23 * The IC Resizer has a restriction that the output frame from the 24 * resizer must be 1024 or less in both width (pixels) and height 25 * (lines). 26 * 27 * The image converter attempts to split up a conversion when 28 * the desired output (converted) frame resolution exceeds the 29 * IC resizer limit of 1024 in either dimension. 30 * 31 * If either dimension of the output frame exceeds the limit, the 32 * dimension is split into 1, 2, or 4 equal stripes, for a maximum 33 * of 4*4 or 16 tiles. A conversion is then carried out for each 34 * tile (but taking care to pass the full frame stride length to 35 * the DMA channel's parameter memory!). IDMA double-buffering is used 36 * to convert each tile back-to-back when possible (see note below 37 * when double_buffering boolean is set). 38 * 39 * Note that the input frame must be split up into the same number 40 * of tiles as the output frame. 41 * 42 * FIXME: at this point there is no attempt to deal with visible seams 43 * at the tile boundaries when upscaling. The seams are caused by a reset 44 * of the bilinear upscale interpolation when starting a new tile. The 45 * seams are barely visible for small upscale factors, but become 46 * increasingly visible as the upscale factor gets larger, since more 47 * interpolated pixels get thrown out at the tile boundaries. A possilble 48 * fix might be to overlap tiles of different sizes, but this must be done 49 * while also maintaining the IDMAC dma buffer address alignment and 8x8 IRT 50 * alignment restrictions of each tile. 51 */ 52 53 #define MAX_STRIPES_W 4 54 #define MAX_STRIPES_H 4 55 #define MAX_TILES (MAX_STRIPES_W * MAX_STRIPES_H) 56 57 #define MIN_W 16 58 #define MIN_H 8 59 #define MAX_W 4096 60 #define MAX_H 4096 61 62 enum ipu_image_convert_type { 63 IMAGE_CONVERT_IN = 0, 64 IMAGE_CONVERT_OUT, 65 }; 66 67 struct ipu_image_convert_dma_buf { 68 void *virt; 69 dma_addr_t phys; 70 unsigned long len; 71 }; 72 73 struct ipu_image_convert_dma_chan { 74 int in; 75 int out; 76 int rot_in; 77 int rot_out; 78 int vdi_in_p; 79 int vdi_in; 80 int vdi_in_n; 81 }; 82 83 /* dimensions of one tile */ 84 struct ipu_image_tile { 85 u32 width; 86 u32 height; 87 u32 left; 88 u32 top; 89 /* size and strides are in bytes */ 90 u32 size; 91 u32 stride; 92 u32 rot_stride; 93 /* start Y or packed offset of this tile */ 94 u32 offset; 95 /* offset from start to tile in U plane, for planar formats */ 96 u32 u_off; 97 /* offset from start to tile in V plane, for planar formats */ 98 u32 v_off; 99 }; 100 101 struct ipu_image_convert_image { 102 struct ipu_image base; 103 enum ipu_image_convert_type type; 104 105 const struct ipu_image_pixfmt *fmt; 106 unsigned int stride; 107 108 /* # of rows (horizontal stripes) if dest height is > 1024 */ 109 unsigned int num_rows; 110 /* # of columns (vertical stripes) if dest width is > 1024 */ 111 unsigned int num_cols; 112 113 struct ipu_image_tile tile[MAX_TILES]; 114 }; 115 116 struct ipu_image_pixfmt { 117 u32 fourcc; /* V4L2 fourcc */ 118 int bpp; /* total bpp */ 119 int uv_width_dec; /* decimation in width for U/V planes */ 120 int uv_height_dec; /* decimation in height for U/V planes */ 121 bool planar; /* planar format */ 122 bool uv_swapped; /* U and V planes are swapped */ 123 bool uv_packed; /* partial planar (U and V in same plane) */ 124 }; 125 126 struct ipu_image_convert_ctx; 127 struct ipu_image_convert_chan; 128 struct ipu_image_convert_priv; 129 130 struct ipu_image_convert_ctx { 131 struct ipu_image_convert_chan *chan; 132 133 ipu_image_convert_cb_t complete; 134 void *complete_context; 135 136 /* Source/destination image data and rotation mode */ 137 struct ipu_image_convert_image in; 138 struct ipu_image_convert_image out; 139 enum ipu_rotate_mode rot_mode; 140 u32 downsize_coeff_h; 141 u32 downsize_coeff_v; 142 u32 image_resize_coeff_h; 143 u32 image_resize_coeff_v; 144 u32 resize_coeffs_h[MAX_STRIPES_W]; 145 u32 resize_coeffs_v[MAX_STRIPES_H]; 146 147 /* intermediate buffer for rotation */ 148 struct ipu_image_convert_dma_buf rot_intermediate[2]; 149 150 /* current buffer number for double buffering */ 151 int cur_buf_num; 152 153 bool aborting; 154 struct completion aborted; 155 156 /* can we use double-buffering for this conversion operation? */ 157 bool double_buffering; 158 /* num_rows * num_cols */ 159 unsigned int num_tiles; 160 /* next tile to process */ 161 unsigned int next_tile; 162 /* where to place converted tile in dest image */ 163 unsigned int out_tile_map[MAX_TILES]; 164 165 struct list_head list; 166 }; 167 168 struct ipu_image_convert_chan { 169 struct ipu_image_convert_priv *priv; 170 171 enum ipu_ic_task ic_task; 172 const struct ipu_image_convert_dma_chan *dma_ch; 173 174 struct ipu_ic *ic; 175 struct ipuv3_channel *in_chan; 176 struct ipuv3_channel *out_chan; 177 struct ipuv3_channel *rotation_in_chan; 178 struct ipuv3_channel *rotation_out_chan; 179 180 /* the IPU end-of-frame irqs */ 181 int out_eof_irq; 182 int rot_out_eof_irq; 183 184 spinlock_t irqlock; 185 186 /* list of convert contexts */ 187 struct list_head ctx_list; 188 /* queue of conversion runs */ 189 struct list_head pending_q; 190 /* queue of completed runs */ 191 struct list_head done_q; 192 193 /* the current conversion run */ 194 struct ipu_image_convert_run *current_run; 195 }; 196 197 struct ipu_image_convert_priv { 198 struct ipu_image_convert_chan chan[IC_NUM_TASKS]; 199 struct ipu_soc *ipu; 200 }; 201 202 static const struct ipu_image_convert_dma_chan 203 image_convert_dma_chan[IC_NUM_TASKS] = { 204 [IC_TASK_VIEWFINDER] = { 205 .in = IPUV3_CHANNEL_MEM_IC_PRP_VF, 206 .out = IPUV3_CHANNEL_IC_PRP_VF_MEM, 207 .rot_in = IPUV3_CHANNEL_MEM_ROT_VF, 208 .rot_out = IPUV3_CHANNEL_ROT_VF_MEM, 209 .vdi_in_p = IPUV3_CHANNEL_MEM_VDI_PREV, 210 .vdi_in = IPUV3_CHANNEL_MEM_VDI_CUR, 211 .vdi_in_n = IPUV3_CHANNEL_MEM_VDI_NEXT, 212 }, 213 [IC_TASK_POST_PROCESSOR] = { 214 .in = IPUV3_CHANNEL_MEM_IC_PP, 215 .out = IPUV3_CHANNEL_IC_PP_MEM, 216 .rot_in = IPUV3_CHANNEL_MEM_ROT_PP, 217 .rot_out = IPUV3_CHANNEL_ROT_PP_MEM, 218 }, 219 }; 220 221 static const struct ipu_image_pixfmt image_convert_formats[] = { 222 { 223 .fourcc = V4L2_PIX_FMT_RGB565, 224 .bpp = 16, 225 }, { 226 .fourcc = V4L2_PIX_FMT_RGB24, 227 .bpp = 24, 228 }, { 229 .fourcc = V4L2_PIX_FMT_BGR24, 230 .bpp = 24, 231 }, { 232 .fourcc = V4L2_PIX_FMT_RGB32, 233 .bpp = 32, 234 }, { 235 .fourcc = V4L2_PIX_FMT_BGR32, 236 .bpp = 32, 237 }, { 238 .fourcc = V4L2_PIX_FMT_XRGB32, 239 .bpp = 32, 240 }, { 241 .fourcc = V4L2_PIX_FMT_XBGR32, 242 .bpp = 32, 243 }, { 244 .fourcc = V4L2_PIX_FMT_YUYV, 245 .bpp = 16, 246 .uv_width_dec = 2, 247 .uv_height_dec = 1, 248 }, { 249 .fourcc = V4L2_PIX_FMT_UYVY, 250 .bpp = 16, 251 .uv_width_dec = 2, 252 .uv_height_dec = 1, 253 }, { 254 .fourcc = V4L2_PIX_FMT_YUV420, 255 .bpp = 12, 256 .planar = true, 257 .uv_width_dec = 2, 258 .uv_height_dec = 2, 259 }, { 260 .fourcc = V4L2_PIX_FMT_YVU420, 261 .bpp = 12, 262 .planar = true, 263 .uv_width_dec = 2, 264 .uv_height_dec = 2, 265 .uv_swapped = true, 266 }, { 267 .fourcc = V4L2_PIX_FMT_NV12, 268 .bpp = 12, 269 .planar = true, 270 .uv_width_dec = 2, 271 .uv_height_dec = 2, 272 .uv_packed = true, 273 }, { 274 .fourcc = V4L2_PIX_FMT_YUV422P, 275 .bpp = 16, 276 .planar = true, 277 .uv_width_dec = 2, 278 .uv_height_dec = 1, 279 }, { 280 .fourcc = V4L2_PIX_FMT_NV16, 281 .bpp = 16, 282 .planar = true, 283 .uv_width_dec = 2, 284 .uv_height_dec = 1, 285 .uv_packed = true, 286 }, 287 }; 288 289 static const struct ipu_image_pixfmt *get_format(u32 fourcc) 290 { 291 const struct ipu_image_pixfmt *ret = NULL; 292 unsigned int i; 293 294 for (i = 0; i < ARRAY_SIZE(image_convert_formats); i++) { 295 if (image_convert_formats[i].fourcc == fourcc) { 296 ret = &image_convert_formats[i]; 297 break; 298 } 299 } 300 301 return ret; 302 } 303 304 static void dump_format(struct ipu_image_convert_ctx *ctx, 305 struct ipu_image_convert_image *ic_image) 306 { 307 struct ipu_image_convert_chan *chan = ctx->chan; 308 struct ipu_image_convert_priv *priv = chan->priv; 309 310 dev_dbg(priv->ipu->dev, 311 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles), %c%c%c%c\n", 312 chan->ic_task, ctx, 313 ic_image->type == IMAGE_CONVERT_OUT ? "Output" : "Input", 314 ic_image->base.pix.width, ic_image->base.pix.height, 315 ic_image->num_cols, ic_image->num_rows, 316 ic_image->fmt->fourcc & 0xff, 317 (ic_image->fmt->fourcc >> 8) & 0xff, 318 (ic_image->fmt->fourcc >> 16) & 0xff, 319 (ic_image->fmt->fourcc >> 24) & 0xff); 320 } 321 322 int ipu_image_convert_enum_format(int index, u32 *fourcc) 323 { 324 const struct ipu_image_pixfmt *fmt; 325 326 if (index >= (int)ARRAY_SIZE(image_convert_formats)) 327 return -EINVAL; 328 329 /* Format found */ 330 fmt = &image_convert_formats[index]; 331 *fourcc = fmt->fourcc; 332 return 0; 333 } 334 EXPORT_SYMBOL_GPL(ipu_image_convert_enum_format); 335 336 static void free_dma_buf(struct ipu_image_convert_priv *priv, 337 struct ipu_image_convert_dma_buf *buf) 338 { 339 if (buf->virt) 340 dma_free_coherent(priv->ipu->dev, 341 buf->len, buf->virt, buf->phys); 342 buf->virt = NULL; 343 buf->phys = 0; 344 } 345 346 static int alloc_dma_buf(struct ipu_image_convert_priv *priv, 347 struct ipu_image_convert_dma_buf *buf, 348 int size) 349 { 350 buf->len = PAGE_ALIGN(size); 351 buf->virt = dma_alloc_coherent(priv->ipu->dev, buf->len, &buf->phys, 352 GFP_DMA | GFP_KERNEL); 353 if (!buf->virt) { 354 dev_err(priv->ipu->dev, "failed to alloc dma buffer\n"); 355 return -ENOMEM; 356 } 357 358 return 0; 359 } 360 361 static inline int num_stripes(int dim) 362 { 363 if (dim <= 1024) 364 return 1; 365 else if (dim <= 2048) 366 return 2; 367 else 368 return 4; 369 } 370 371 /* 372 * Calculate downsizing coefficients, which are the same for all tiles, 373 * and bilinear resizing coefficients, which are used to find the best 374 * seam positions. 375 */ 376 static int calc_image_resize_coefficients(struct ipu_image_convert_ctx *ctx, 377 struct ipu_image *in, 378 struct ipu_image *out) 379 { 380 u32 downsized_width = in->rect.width; 381 u32 downsized_height = in->rect.height; 382 u32 downsize_coeff_v = 0; 383 u32 downsize_coeff_h = 0; 384 u32 resized_width = out->rect.width; 385 u32 resized_height = out->rect.height; 386 u32 resize_coeff_h; 387 u32 resize_coeff_v; 388 389 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 390 resized_width = out->rect.height; 391 resized_height = out->rect.width; 392 } 393 394 /* Do not let invalid input lead to an endless loop below */ 395 if (WARN_ON(resized_width == 0 || resized_height == 0)) 396 return -EINVAL; 397 398 while (downsized_width >= resized_width * 2) { 399 downsized_width >>= 1; 400 downsize_coeff_h++; 401 } 402 403 while (downsized_height >= resized_height * 2) { 404 downsized_height >>= 1; 405 downsize_coeff_v++; 406 } 407 408 /* 409 * Calculate the bilinear resizing coefficients that could be used if 410 * we were converting with a single tile. The bottom right output pixel 411 * should sample as close as possible to the bottom right input pixel 412 * out of the decimator, but not overshoot it: 413 */ 414 resize_coeff_h = 8192 * (downsized_width - 1) / (resized_width - 1); 415 resize_coeff_v = 8192 * (downsized_height - 1) / (resized_height - 1); 416 417 dev_dbg(ctx->chan->priv->ipu->dev, 418 "%s: hscale: >>%u, *8192/%u vscale: >>%u, *8192/%u, %ux%u tiles\n", 419 __func__, downsize_coeff_h, resize_coeff_h, downsize_coeff_v, 420 resize_coeff_v, ctx->in.num_cols, ctx->in.num_rows); 421 422 if (downsize_coeff_h > 2 || downsize_coeff_v > 2 || 423 resize_coeff_h > 0x3fff || resize_coeff_v > 0x3fff) 424 return -EINVAL; 425 426 ctx->downsize_coeff_h = downsize_coeff_h; 427 ctx->downsize_coeff_v = downsize_coeff_v; 428 ctx->image_resize_coeff_h = resize_coeff_h; 429 ctx->image_resize_coeff_v = resize_coeff_v; 430 431 return 0; 432 } 433 434 #define round_closest(x, y) round_down((x) + (y)/2, (y)) 435 436 /* 437 * Find the best aligned seam position in the inverval [out_start, out_end]. 438 * Rotation and image offsets are out of scope. 439 * 440 * @out_start: start of inverval, must be within 1024 pixels / lines 441 * of out_end 442 * @out_end: end of interval, smaller than or equal to out_edge 443 * @in_edge: input right / bottom edge 444 * @out_edge: output right / bottom edge 445 * @in_align: input alignment, either horizontal 8-byte line start address 446 * alignment, or pixel alignment due to image format 447 * @out_align: output alignment, either horizontal 8-byte line start address 448 * alignment, or pixel alignment due to image format or rotator 449 * block size 450 * @in_burst: horizontal input burst size in case of horizontal flip 451 * @out_burst: horizontal output burst size or rotator block size 452 * @downsize_coeff: downsizing section coefficient 453 * @resize_coeff: main processing section resizing coefficient 454 * @_in_seam: aligned input seam position return value 455 * @_out_seam: aligned output seam position return value 456 */ 457 static void find_best_seam(struct ipu_image_convert_ctx *ctx, 458 unsigned int out_start, 459 unsigned int out_end, 460 unsigned int in_edge, 461 unsigned int out_edge, 462 unsigned int in_align, 463 unsigned int out_align, 464 unsigned int in_burst, 465 unsigned int out_burst, 466 unsigned int downsize_coeff, 467 unsigned int resize_coeff, 468 u32 *_in_seam, 469 u32 *_out_seam) 470 { 471 struct device *dev = ctx->chan->priv->ipu->dev; 472 unsigned int out_pos; 473 /* Input / output seam position candidates */ 474 unsigned int out_seam = 0; 475 unsigned int in_seam = 0; 476 unsigned int min_diff = UINT_MAX; 477 478 /* 479 * Output tiles must start at a multiple of 8 bytes horizontally and 480 * possibly at an even line horizontally depending on the pixel format. 481 * Only consider output aligned positions for the seam. 482 */ 483 out_start = round_up(out_start, out_align); 484 for (out_pos = out_start; out_pos < out_end; out_pos += out_align) { 485 unsigned int in_pos; 486 unsigned int in_pos_aligned; 487 unsigned int abs_diff; 488 489 /* 490 * Tiles in the right row / bottom column may not be allowed to 491 * overshoot horizontally / vertically. out_burst may be the 492 * actual DMA burst size, or the rotator block size. 493 */ 494 if ((out_burst > 1) && (out_edge - out_pos) % out_burst) 495 continue; 496 497 /* 498 * Input sample position, corresponding to out_pos, 19.13 fixed 499 * point. 500 */ 501 in_pos = (out_pos * resize_coeff) << downsize_coeff; 502 /* 503 * The closest input sample position that we could actually 504 * start the input tile at, 19.13 fixed point. 505 */ 506 in_pos_aligned = round_closest(in_pos, 8192U * in_align); 507 508 if ((in_burst > 1) && 509 (in_edge - in_pos_aligned / 8192U) % in_burst) 510 continue; 511 512 if (in_pos < in_pos_aligned) 513 abs_diff = in_pos_aligned - in_pos; 514 else 515 abs_diff = in_pos - in_pos_aligned; 516 517 if (abs_diff < min_diff) { 518 in_seam = in_pos_aligned; 519 out_seam = out_pos; 520 min_diff = abs_diff; 521 } 522 } 523 524 *_out_seam = out_seam; 525 /* Convert 19.13 fixed point to integer seam position */ 526 *_in_seam = DIV_ROUND_CLOSEST(in_seam, 8192U); 527 528 dev_dbg(dev, "%s: out_seam %u(%u) in [%u, %u], in_seam %u(%u) diff %u.%03u\n", 529 __func__, out_seam, out_align, out_start, out_end, 530 *_in_seam, in_align, min_diff / 8192, 531 DIV_ROUND_CLOSEST(min_diff % 8192 * 1000, 8192)); 532 } 533 534 /* 535 * Tile left edges are required to be aligned to multiples of 8 bytes 536 * by the IDMAC. 537 */ 538 static inline u32 tile_left_align(const struct ipu_image_pixfmt *fmt) 539 { 540 if (fmt->planar) 541 return fmt->uv_packed ? 8 : 8 * fmt->uv_width_dec; 542 else 543 return fmt->bpp == 32 ? 2 : fmt->bpp == 16 ? 4 : 8; 544 } 545 546 /* 547 * Tile top edge alignment is only limited by chroma subsampling. 548 */ 549 static inline u32 tile_top_align(const struct ipu_image_pixfmt *fmt) 550 { 551 return fmt->uv_height_dec > 1 ? 2 : 1; 552 } 553 554 static inline u32 tile_width_align(enum ipu_image_convert_type type, 555 const struct ipu_image_pixfmt *fmt, 556 enum ipu_rotate_mode rot_mode) 557 { 558 if (type == IMAGE_CONVERT_IN) { 559 /* 560 * The IC burst reads 8 pixels at a time. Reading beyond the 561 * end of the line is usually acceptable. Those pixels are 562 * ignored, unless the IC has to write the scaled line in 563 * reverse. 564 */ 565 return (!ipu_rot_mode_is_irt(rot_mode) && 566 (rot_mode & IPU_ROT_BIT_HFLIP)) ? 8 : 2; 567 } 568 569 /* 570 * Align to 16x16 pixel blocks for planar 4:2:0 chroma subsampled 571 * formats to guarantee 8-byte aligned line start addresses in the 572 * chroma planes when IRT is used. Align to 8x8 pixel IRT block size 573 * for all other formats. 574 */ 575 return (ipu_rot_mode_is_irt(rot_mode) && 576 fmt->planar && !fmt->uv_packed) ? 577 8 * fmt->uv_width_dec : 8; 578 } 579 580 static inline u32 tile_height_align(enum ipu_image_convert_type type, 581 const struct ipu_image_pixfmt *fmt, 582 enum ipu_rotate_mode rot_mode) 583 { 584 if (type == IMAGE_CONVERT_IN || !ipu_rot_mode_is_irt(rot_mode)) 585 return 2; 586 587 /* 588 * Align to 16x16 pixel blocks for planar 4:2:0 chroma subsampled 589 * formats to guarantee 8-byte aligned line start addresses in the 590 * chroma planes when IRT is used. Align to 8x8 pixel IRT block size 591 * for all other formats. 592 */ 593 return (fmt->planar && !fmt->uv_packed) ? 8 * fmt->uv_width_dec : 8; 594 } 595 596 /* 597 * Fill in left position and width and for all tiles in an input column, and 598 * for all corresponding output tiles. If the 90° rotator is used, the output 599 * tiles are in a row, and output tile top position and height are set. 600 */ 601 static void fill_tile_column(struct ipu_image_convert_ctx *ctx, 602 unsigned int col, 603 struct ipu_image_convert_image *in, 604 unsigned int in_left, unsigned int in_width, 605 struct ipu_image_convert_image *out, 606 unsigned int out_left, unsigned int out_width) 607 { 608 unsigned int row, tile_idx; 609 struct ipu_image_tile *in_tile, *out_tile; 610 611 for (row = 0; row < in->num_rows; row++) { 612 tile_idx = in->num_cols * row + col; 613 in_tile = &in->tile[tile_idx]; 614 out_tile = &out->tile[ctx->out_tile_map[tile_idx]]; 615 616 in_tile->left = in_left; 617 in_tile->width = in_width; 618 619 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 620 out_tile->top = out_left; 621 out_tile->height = out_width; 622 } else { 623 out_tile->left = out_left; 624 out_tile->width = out_width; 625 } 626 } 627 } 628 629 /* 630 * Fill in top position and height and for all tiles in an input row, and 631 * for all corresponding output tiles. If the 90° rotator is used, the output 632 * tiles are in a column, and output tile left position and width are set. 633 */ 634 static void fill_tile_row(struct ipu_image_convert_ctx *ctx, unsigned int row, 635 struct ipu_image_convert_image *in, 636 unsigned int in_top, unsigned int in_height, 637 struct ipu_image_convert_image *out, 638 unsigned int out_top, unsigned int out_height) 639 { 640 unsigned int col, tile_idx; 641 struct ipu_image_tile *in_tile, *out_tile; 642 643 for (col = 0; col < in->num_cols; col++) { 644 tile_idx = in->num_cols * row + col; 645 in_tile = &in->tile[tile_idx]; 646 out_tile = &out->tile[ctx->out_tile_map[tile_idx]]; 647 648 in_tile->top = in_top; 649 in_tile->height = in_height; 650 651 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 652 out_tile->left = out_top; 653 out_tile->width = out_height; 654 } else { 655 out_tile->top = out_top; 656 out_tile->height = out_height; 657 } 658 } 659 } 660 661 /* 662 * Find the best horizontal and vertical seam positions to split into tiles. 663 * Minimize the fractional part of the input sampling position for the 664 * top / left pixels of each tile. 665 */ 666 static void find_seams(struct ipu_image_convert_ctx *ctx, 667 struct ipu_image_convert_image *in, 668 struct ipu_image_convert_image *out) 669 { 670 struct device *dev = ctx->chan->priv->ipu->dev; 671 unsigned int resized_width = out->base.rect.width; 672 unsigned int resized_height = out->base.rect.height; 673 unsigned int col; 674 unsigned int row; 675 unsigned int in_left_align = tile_left_align(in->fmt); 676 unsigned int in_top_align = tile_top_align(in->fmt); 677 unsigned int out_left_align = tile_left_align(out->fmt); 678 unsigned int out_top_align = tile_top_align(out->fmt); 679 unsigned int out_width_align = tile_width_align(out->type, out->fmt, 680 ctx->rot_mode); 681 unsigned int out_height_align = tile_height_align(out->type, out->fmt, 682 ctx->rot_mode); 683 unsigned int in_right = in->base.rect.width; 684 unsigned int in_bottom = in->base.rect.height; 685 unsigned int out_right = out->base.rect.width; 686 unsigned int out_bottom = out->base.rect.height; 687 unsigned int flipped_out_left; 688 unsigned int flipped_out_top; 689 690 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 691 /* Switch width/height and align top left to IRT block size */ 692 resized_width = out->base.rect.height; 693 resized_height = out->base.rect.width; 694 out_left_align = out_height_align; 695 out_top_align = out_width_align; 696 out_width_align = out_left_align; 697 out_height_align = out_top_align; 698 out_right = out->base.rect.height; 699 out_bottom = out->base.rect.width; 700 } 701 702 for (col = in->num_cols - 1; col > 0; col--) { 703 bool allow_in_overshoot = ipu_rot_mode_is_irt(ctx->rot_mode) || 704 !(ctx->rot_mode & IPU_ROT_BIT_HFLIP); 705 bool allow_out_overshoot = (col < in->num_cols - 1) && 706 !(ctx->rot_mode & IPU_ROT_BIT_HFLIP); 707 unsigned int out_start; 708 unsigned int out_end; 709 unsigned int in_left; 710 unsigned int out_left; 711 712 /* 713 * Align input width to burst length if the scaling step flips 714 * horizontally. 715 */ 716 717 /* Start within 1024 pixels of the right edge */ 718 out_start = max_t(int, 0, out_right - 1024); 719 /* End before having to add more columns to the left */ 720 out_end = min_t(unsigned int, out_right, col * 1024); 721 722 find_best_seam(ctx, out_start, out_end, 723 in_right, out_right, 724 in_left_align, out_left_align, 725 allow_in_overshoot ? 1 : 8 /* burst length */, 726 allow_out_overshoot ? 1 : out_width_align, 727 ctx->downsize_coeff_h, ctx->image_resize_coeff_h, 728 &in_left, &out_left); 729 730 if (ctx->rot_mode & IPU_ROT_BIT_HFLIP) 731 flipped_out_left = resized_width - out_right; 732 else 733 flipped_out_left = out_left; 734 735 fill_tile_column(ctx, col, in, in_left, in_right - in_left, 736 out, flipped_out_left, out_right - out_left); 737 738 dev_dbg(dev, "%s: col %u: %u, %u -> %u, %u\n", __func__, col, 739 in_left, in_right - in_left, 740 flipped_out_left, out_right - out_left); 741 742 in_right = in_left; 743 out_right = out_left; 744 } 745 746 flipped_out_left = (ctx->rot_mode & IPU_ROT_BIT_HFLIP) ? 747 resized_width - out_right : 0; 748 749 fill_tile_column(ctx, 0, in, 0, in_right, 750 out, flipped_out_left, out_right); 751 752 dev_dbg(dev, "%s: col 0: 0, %u -> %u, %u\n", __func__, 753 in_right, flipped_out_left, out_right); 754 755 for (row = in->num_rows - 1; row > 0; row--) { 756 bool allow_overshoot = row < in->num_rows - 1; 757 unsigned int out_start; 758 unsigned int out_end; 759 unsigned int in_top; 760 unsigned int out_top; 761 762 /* Start within 1024 lines of the bottom edge */ 763 out_start = max_t(int, 0, out_bottom - 1024); 764 /* End before having to add more rows above */ 765 out_end = min_t(unsigned int, out_bottom, row * 1024); 766 767 find_best_seam(ctx, out_start, out_end, 768 in_bottom, out_bottom, 769 in_top_align, out_top_align, 770 1, allow_overshoot ? 1 : out_height_align, 771 ctx->downsize_coeff_v, ctx->image_resize_coeff_v, 772 &in_top, &out_top); 773 774 if ((ctx->rot_mode & IPU_ROT_BIT_VFLIP) ^ 775 ipu_rot_mode_is_irt(ctx->rot_mode)) 776 flipped_out_top = resized_height - out_bottom; 777 else 778 flipped_out_top = out_top; 779 780 fill_tile_row(ctx, row, in, in_top, in_bottom - in_top, 781 out, flipped_out_top, out_bottom - out_top); 782 783 dev_dbg(dev, "%s: row %u: %u, %u -> %u, %u\n", __func__, row, 784 in_top, in_bottom - in_top, 785 flipped_out_top, out_bottom - out_top); 786 787 in_bottom = in_top; 788 out_bottom = out_top; 789 } 790 791 if ((ctx->rot_mode & IPU_ROT_BIT_VFLIP) ^ 792 ipu_rot_mode_is_irt(ctx->rot_mode)) 793 flipped_out_top = resized_height - out_bottom; 794 else 795 flipped_out_top = 0; 796 797 fill_tile_row(ctx, 0, in, 0, in_bottom, 798 out, flipped_out_top, out_bottom); 799 800 dev_dbg(dev, "%s: row 0: 0, %u -> %u, %u\n", __func__, 801 in_bottom, flipped_out_top, out_bottom); 802 } 803 804 static void calc_tile_dimensions(struct ipu_image_convert_ctx *ctx, 805 struct ipu_image_convert_image *image) 806 { 807 struct ipu_image_convert_chan *chan = ctx->chan; 808 struct ipu_image_convert_priv *priv = chan->priv; 809 unsigned int i; 810 811 for (i = 0; i < ctx->num_tiles; i++) { 812 struct ipu_image_tile *tile; 813 const unsigned int row = i / image->num_cols; 814 const unsigned int col = i % image->num_cols; 815 816 if (image->type == IMAGE_CONVERT_OUT) 817 tile = &image->tile[ctx->out_tile_map[i]]; 818 else 819 tile = &image->tile[i]; 820 821 tile->size = ((tile->height * image->fmt->bpp) >> 3) * 822 tile->width; 823 824 if (image->fmt->planar) { 825 tile->stride = tile->width; 826 tile->rot_stride = tile->height; 827 } else { 828 tile->stride = 829 (image->fmt->bpp * tile->width) >> 3; 830 tile->rot_stride = 831 (image->fmt->bpp * tile->height) >> 3; 832 } 833 834 dev_dbg(priv->ipu->dev, 835 "task %u: ctx %p: %s@[%u,%u]: %ux%u@%u,%u\n", 836 chan->ic_task, ctx, 837 image->type == IMAGE_CONVERT_IN ? "Input" : "Output", 838 row, col, 839 tile->width, tile->height, tile->left, tile->top); 840 } 841 } 842 843 /* 844 * Use the rotation transformation to find the tile coordinates 845 * (row, col) of a tile in the destination frame that corresponds 846 * to the given tile coordinates of a source frame. The destination 847 * coordinate is then converted to a tile index. 848 */ 849 static int transform_tile_index(struct ipu_image_convert_ctx *ctx, 850 int src_row, int src_col) 851 { 852 struct ipu_image_convert_chan *chan = ctx->chan; 853 struct ipu_image_convert_priv *priv = chan->priv; 854 struct ipu_image_convert_image *s_image = &ctx->in; 855 struct ipu_image_convert_image *d_image = &ctx->out; 856 int dst_row, dst_col; 857 858 /* with no rotation it's a 1:1 mapping */ 859 if (ctx->rot_mode == IPU_ROTATE_NONE) 860 return src_row * s_image->num_cols + src_col; 861 862 /* 863 * before doing the transform, first we have to translate 864 * source row,col for an origin in the center of s_image 865 */ 866 src_row = src_row * 2 - (s_image->num_rows - 1); 867 src_col = src_col * 2 - (s_image->num_cols - 1); 868 869 /* do the rotation transform */ 870 if (ctx->rot_mode & IPU_ROT_BIT_90) { 871 dst_col = -src_row; 872 dst_row = src_col; 873 } else { 874 dst_col = src_col; 875 dst_row = src_row; 876 } 877 878 /* apply flip */ 879 if (ctx->rot_mode & IPU_ROT_BIT_HFLIP) 880 dst_col = -dst_col; 881 if (ctx->rot_mode & IPU_ROT_BIT_VFLIP) 882 dst_row = -dst_row; 883 884 dev_dbg(priv->ipu->dev, "task %u: ctx %p: [%d,%d] --> [%d,%d]\n", 885 chan->ic_task, ctx, src_col, src_row, dst_col, dst_row); 886 887 /* 888 * finally translate dest row,col using an origin in upper 889 * left of d_image 890 */ 891 dst_row += d_image->num_rows - 1; 892 dst_col += d_image->num_cols - 1; 893 dst_row /= 2; 894 dst_col /= 2; 895 896 return dst_row * d_image->num_cols + dst_col; 897 } 898 899 /* 900 * Fill the out_tile_map[] with transformed destination tile indeces. 901 */ 902 static void calc_out_tile_map(struct ipu_image_convert_ctx *ctx) 903 { 904 struct ipu_image_convert_image *s_image = &ctx->in; 905 unsigned int row, col, tile = 0; 906 907 for (row = 0; row < s_image->num_rows; row++) { 908 for (col = 0; col < s_image->num_cols; col++) { 909 ctx->out_tile_map[tile] = 910 transform_tile_index(ctx, row, col); 911 tile++; 912 } 913 } 914 } 915 916 static int calc_tile_offsets_planar(struct ipu_image_convert_ctx *ctx, 917 struct ipu_image_convert_image *image) 918 { 919 struct ipu_image_convert_chan *chan = ctx->chan; 920 struct ipu_image_convert_priv *priv = chan->priv; 921 const struct ipu_image_pixfmt *fmt = image->fmt; 922 unsigned int row, col, tile = 0; 923 u32 H, top, y_stride, uv_stride; 924 u32 uv_row_off, uv_col_off, uv_off, u_off, v_off, tmp; 925 u32 y_row_off, y_col_off, y_off; 926 u32 y_size, uv_size; 927 928 /* setup some convenience vars */ 929 H = image->base.pix.height; 930 931 y_stride = image->stride; 932 uv_stride = y_stride / fmt->uv_width_dec; 933 if (fmt->uv_packed) 934 uv_stride *= 2; 935 936 y_size = H * y_stride; 937 uv_size = y_size / (fmt->uv_width_dec * fmt->uv_height_dec); 938 939 for (row = 0; row < image->num_rows; row++) { 940 top = image->tile[tile].top; 941 y_row_off = top * y_stride; 942 uv_row_off = (top * uv_stride) / fmt->uv_height_dec; 943 944 for (col = 0; col < image->num_cols; col++) { 945 y_col_off = image->tile[tile].left; 946 uv_col_off = y_col_off / fmt->uv_width_dec; 947 if (fmt->uv_packed) 948 uv_col_off *= 2; 949 950 y_off = y_row_off + y_col_off; 951 uv_off = uv_row_off + uv_col_off; 952 953 u_off = y_size - y_off + uv_off; 954 v_off = (fmt->uv_packed) ? 0 : u_off + uv_size; 955 if (fmt->uv_swapped) { 956 tmp = u_off; 957 u_off = v_off; 958 v_off = tmp; 959 } 960 961 image->tile[tile].offset = y_off; 962 image->tile[tile].u_off = u_off; 963 image->tile[tile++].v_off = v_off; 964 965 if ((y_off & 0x7) || (u_off & 0x7) || (v_off & 0x7)) { 966 dev_err(priv->ipu->dev, 967 "task %u: ctx %p: %s@[%d,%d]: " 968 "y_off %08x, u_off %08x, v_off %08x\n", 969 chan->ic_task, ctx, 970 image->type == IMAGE_CONVERT_IN ? 971 "Input" : "Output", row, col, 972 y_off, u_off, v_off); 973 return -EINVAL; 974 } 975 } 976 } 977 978 return 0; 979 } 980 981 static int calc_tile_offsets_packed(struct ipu_image_convert_ctx *ctx, 982 struct ipu_image_convert_image *image) 983 { 984 struct ipu_image_convert_chan *chan = ctx->chan; 985 struct ipu_image_convert_priv *priv = chan->priv; 986 const struct ipu_image_pixfmt *fmt = image->fmt; 987 unsigned int row, col, tile = 0; 988 u32 bpp, stride, offset; 989 u32 row_off, col_off; 990 991 /* setup some convenience vars */ 992 stride = image->stride; 993 bpp = fmt->bpp; 994 995 for (row = 0; row < image->num_rows; row++) { 996 row_off = image->tile[tile].top * stride; 997 998 for (col = 0; col < image->num_cols; col++) { 999 col_off = (image->tile[tile].left * bpp) >> 3; 1000 1001 offset = row_off + col_off; 1002 1003 image->tile[tile].offset = offset; 1004 image->tile[tile].u_off = 0; 1005 image->tile[tile++].v_off = 0; 1006 1007 if (offset & 0x7) { 1008 dev_err(priv->ipu->dev, 1009 "task %u: ctx %p: %s@[%d,%d]: " 1010 "phys %08x\n", 1011 chan->ic_task, ctx, 1012 image->type == IMAGE_CONVERT_IN ? 1013 "Input" : "Output", row, col, 1014 row_off + col_off); 1015 return -EINVAL; 1016 } 1017 } 1018 } 1019 1020 return 0; 1021 } 1022 1023 static int calc_tile_offsets(struct ipu_image_convert_ctx *ctx, 1024 struct ipu_image_convert_image *image) 1025 { 1026 if (image->fmt->planar) 1027 return calc_tile_offsets_planar(ctx, image); 1028 1029 return calc_tile_offsets_packed(ctx, image); 1030 } 1031 1032 /* 1033 * Calculate the resizing ratio for the IC main processing section given input 1034 * size, fixed downsizing coefficient, and output size. 1035 * Either round to closest for the next tile's first pixel to minimize seams 1036 * and distortion (for all but right column / bottom row), or round down to 1037 * avoid sampling beyond the edges of the input image for this tile's last 1038 * pixel. 1039 * Returns the resizing coefficient, resizing ratio is 8192.0 / resize_coeff. 1040 */ 1041 static u32 calc_resize_coeff(u32 input_size, u32 downsize_coeff, 1042 u32 output_size, bool allow_overshoot) 1043 { 1044 u32 downsized = input_size >> downsize_coeff; 1045 1046 if (allow_overshoot) 1047 return DIV_ROUND_CLOSEST(8192 * downsized, output_size); 1048 else 1049 return 8192 * (downsized - 1) / (output_size - 1); 1050 } 1051 1052 /* 1053 * Slightly modify resize coefficients per tile to hide the bilinear 1054 * interpolator reset at tile borders, shifting the right / bottom edge 1055 * by up to a half input pixel. This removes noticeable seams between 1056 * tiles at higher upscaling factors. 1057 */ 1058 static void calc_tile_resize_coefficients(struct ipu_image_convert_ctx *ctx) 1059 { 1060 struct ipu_image_convert_chan *chan = ctx->chan; 1061 struct ipu_image_convert_priv *priv = chan->priv; 1062 struct ipu_image_tile *in_tile, *out_tile; 1063 unsigned int col, row, tile_idx; 1064 unsigned int last_output; 1065 1066 for (col = 0; col < ctx->in.num_cols; col++) { 1067 bool closest = (col < ctx->in.num_cols - 1) && 1068 !(ctx->rot_mode & IPU_ROT_BIT_HFLIP); 1069 u32 resized_width; 1070 u32 resize_coeff_h; 1071 1072 tile_idx = col; 1073 in_tile = &ctx->in.tile[tile_idx]; 1074 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 1075 1076 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1077 resized_width = out_tile->height; 1078 else 1079 resized_width = out_tile->width; 1080 1081 resize_coeff_h = calc_resize_coeff(in_tile->width, 1082 ctx->downsize_coeff_h, 1083 resized_width, closest); 1084 1085 dev_dbg(priv->ipu->dev, "%s: column %u hscale: *8192/%u\n", 1086 __func__, col, resize_coeff_h); 1087 1088 1089 for (row = 0; row < ctx->in.num_rows; row++) { 1090 tile_idx = row * ctx->in.num_cols + col; 1091 in_tile = &ctx->in.tile[tile_idx]; 1092 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 1093 1094 /* 1095 * With the horizontal scaling factor known, round up 1096 * resized width (output width or height) to burst size. 1097 */ 1098 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1099 out_tile->height = round_up(resized_width, 8); 1100 else 1101 out_tile->width = round_up(resized_width, 8); 1102 1103 /* 1104 * Calculate input width from the last accessed input 1105 * pixel given resized width and scaling coefficients. 1106 * Round up to burst size. 1107 */ 1108 last_output = round_up(resized_width, 8) - 1; 1109 if (closest) 1110 last_output++; 1111 in_tile->width = round_up( 1112 (DIV_ROUND_UP(last_output * resize_coeff_h, 1113 8192) + 1) 1114 << ctx->downsize_coeff_h, 8); 1115 } 1116 1117 ctx->resize_coeffs_h[col] = resize_coeff_h; 1118 } 1119 1120 for (row = 0; row < ctx->in.num_rows; row++) { 1121 bool closest = (row < ctx->in.num_rows - 1) && 1122 !(ctx->rot_mode & IPU_ROT_BIT_VFLIP); 1123 u32 resized_height; 1124 u32 resize_coeff_v; 1125 1126 tile_idx = row * ctx->in.num_cols; 1127 in_tile = &ctx->in.tile[tile_idx]; 1128 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 1129 1130 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1131 resized_height = out_tile->width; 1132 else 1133 resized_height = out_tile->height; 1134 1135 resize_coeff_v = calc_resize_coeff(in_tile->height, 1136 ctx->downsize_coeff_v, 1137 resized_height, closest); 1138 1139 dev_dbg(priv->ipu->dev, "%s: row %u vscale: *8192/%u\n", 1140 __func__, row, resize_coeff_v); 1141 1142 for (col = 0; col < ctx->in.num_cols; col++) { 1143 tile_idx = row * ctx->in.num_cols + col; 1144 in_tile = &ctx->in.tile[tile_idx]; 1145 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 1146 1147 /* 1148 * With the vertical scaling factor known, round up 1149 * resized height (output width or height) to IDMAC 1150 * limitations. 1151 */ 1152 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1153 out_tile->width = round_up(resized_height, 2); 1154 else 1155 out_tile->height = round_up(resized_height, 2); 1156 1157 /* 1158 * Calculate input width from the last accessed input 1159 * pixel given resized height and scaling coefficients. 1160 * Align to IDMAC restrictions. 1161 */ 1162 last_output = round_up(resized_height, 2) - 1; 1163 if (closest) 1164 last_output++; 1165 in_tile->height = round_up( 1166 (DIV_ROUND_UP(last_output * resize_coeff_v, 1167 8192) + 1) 1168 << ctx->downsize_coeff_v, 2); 1169 } 1170 1171 ctx->resize_coeffs_v[row] = resize_coeff_v; 1172 } 1173 } 1174 1175 /* 1176 * return the number of runs in given queue (pending_q or done_q) 1177 * for this context. hold irqlock when calling. 1178 */ 1179 static int get_run_count(struct ipu_image_convert_ctx *ctx, 1180 struct list_head *q) 1181 { 1182 struct ipu_image_convert_run *run; 1183 int count = 0; 1184 1185 lockdep_assert_held(&ctx->chan->irqlock); 1186 1187 list_for_each_entry(run, q, list) { 1188 if (run->ctx == ctx) 1189 count++; 1190 } 1191 1192 return count; 1193 } 1194 1195 static void convert_stop(struct ipu_image_convert_run *run) 1196 { 1197 struct ipu_image_convert_ctx *ctx = run->ctx; 1198 struct ipu_image_convert_chan *chan = ctx->chan; 1199 struct ipu_image_convert_priv *priv = chan->priv; 1200 1201 dev_dbg(priv->ipu->dev, "%s: task %u: stopping ctx %p run %p\n", 1202 __func__, chan->ic_task, ctx, run); 1203 1204 /* disable IC tasks and the channels */ 1205 ipu_ic_task_disable(chan->ic); 1206 ipu_idmac_disable_channel(chan->in_chan); 1207 ipu_idmac_disable_channel(chan->out_chan); 1208 1209 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1210 ipu_idmac_disable_channel(chan->rotation_in_chan); 1211 ipu_idmac_disable_channel(chan->rotation_out_chan); 1212 ipu_idmac_unlink(chan->out_chan, chan->rotation_in_chan); 1213 } 1214 1215 ipu_ic_disable(chan->ic); 1216 } 1217 1218 static void init_idmac_channel(struct ipu_image_convert_ctx *ctx, 1219 struct ipuv3_channel *channel, 1220 struct ipu_image_convert_image *image, 1221 enum ipu_rotate_mode rot_mode, 1222 bool rot_swap_width_height, 1223 unsigned int tile) 1224 { 1225 struct ipu_image_convert_chan *chan = ctx->chan; 1226 unsigned int burst_size; 1227 u32 width, height, stride; 1228 dma_addr_t addr0, addr1 = 0; 1229 struct ipu_image tile_image; 1230 unsigned int tile_idx[2]; 1231 1232 if (image->type == IMAGE_CONVERT_OUT) { 1233 tile_idx[0] = ctx->out_tile_map[tile]; 1234 tile_idx[1] = ctx->out_tile_map[1]; 1235 } else { 1236 tile_idx[0] = tile; 1237 tile_idx[1] = 1; 1238 } 1239 1240 if (rot_swap_width_height) { 1241 width = image->tile[tile_idx[0]].height; 1242 height = image->tile[tile_idx[0]].width; 1243 stride = image->tile[tile_idx[0]].rot_stride; 1244 addr0 = ctx->rot_intermediate[0].phys; 1245 if (ctx->double_buffering) 1246 addr1 = ctx->rot_intermediate[1].phys; 1247 } else { 1248 width = image->tile[tile_idx[0]].width; 1249 height = image->tile[tile_idx[0]].height; 1250 stride = image->stride; 1251 addr0 = image->base.phys0 + 1252 image->tile[tile_idx[0]].offset; 1253 if (ctx->double_buffering) 1254 addr1 = image->base.phys0 + 1255 image->tile[tile_idx[1]].offset; 1256 } 1257 1258 ipu_cpmem_zero(channel); 1259 1260 memset(&tile_image, 0, sizeof(tile_image)); 1261 tile_image.pix.width = tile_image.rect.width = width; 1262 tile_image.pix.height = tile_image.rect.height = height; 1263 tile_image.pix.bytesperline = stride; 1264 tile_image.pix.pixelformat = image->fmt->fourcc; 1265 tile_image.phys0 = addr0; 1266 tile_image.phys1 = addr1; 1267 if (image->fmt->planar && !rot_swap_width_height) { 1268 tile_image.u_offset = image->tile[tile_idx[0]].u_off; 1269 tile_image.v_offset = image->tile[tile_idx[0]].v_off; 1270 } 1271 1272 ipu_cpmem_set_image(channel, &tile_image); 1273 1274 if (rot_mode) 1275 ipu_cpmem_set_rotation(channel, rot_mode); 1276 1277 if (channel == chan->rotation_in_chan || 1278 channel == chan->rotation_out_chan) { 1279 burst_size = 8; 1280 ipu_cpmem_set_block_mode(channel); 1281 } else 1282 burst_size = (width % 16) ? 8 : 16; 1283 1284 ipu_cpmem_set_burstsize(channel, burst_size); 1285 1286 ipu_ic_task_idma_init(chan->ic, channel, width, height, 1287 burst_size, rot_mode); 1288 1289 /* 1290 * Setting a non-zero AXI ID collides with the PRG AXI snooping, so 1291 * only do this when there is no PRG present. 1292 */ 1293 if (!channel->ipu->prg_priv) 1294 ipu_cpmem_set_axi_id(channel, 1); 1295 1296 ipu_idmac_set_double_buffer(channel, ctx->double_buffering); 1297 } 1298 1299 static int convert_start(struct ipu_image_convert_run *run, unsigned int tile) 1300 { 1301 struct ipu_image_convert_ctx *ctx = run->ctx; 1302 struct ipu_image_convert_chan *chan = ctx->chan; 1303 struct ipu_image_convert_priv *priv = chan->priv; 1304 struct ipu_image_convert_image *s_image = &ctx->in; 1305 struct ipu_image_convert_image *d_image = &ctx->out; 1306 enum ipu_color_space src_cs, dest_cs; 1307 unsigned int dst_tile = ctx->out_tile_map[tile]; 1308 unsigned int dest_width, dest_height; 1309 unsigned int col, row; 1310 u32 rsc; 1311 int ret; 1312 1313 dev_dbg(priv->ipu->dev, "%s: task %u: starting ctx %p run %p tile %u -> %u\n", 1314 __func__, chan->ic_task, ctx, run, tile, dst_tile); 1315 1316 src_cs = ipu_pixelformat_to_colorspace(s_image->fmt->fourcc); 1317 dest_cs = ipu_pixelformat_to_colorspace(d_image->fmt->fourcc); 1318 1319 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1320 /* swap width/height for resizer */ 1321 dest_width = d_image->tile[dst_tile].height; 1322 dest_height = d_image->tile[dst_tile].width; 1323 } else { 1324 dest_width = d_image->tile[dst_tile].width; 1325 dest_height = d_image->tile[dst_tile].height; 1326 } 1327 1328 row = tile / s_image->num_cols; 1329 col = tile % s_image->num_cols; 1330 1331 rsc = (ctx->downsize_coeff_v << 30) | 1332 (ctx->resize_coeffs_v[row] << 16) | 1333 (ctx->downsize_coeff_h << 14) | 1334 (ctx->resize_coeffs_h[col]); 1335 1336 dev_dbg(priv->ipu->dev, "%s: %ux%u -> %ux%u (rsc = 0x%x)\n", 1337 __func__, s_image->tile[tile].width, 1338 s_image->tile[tile].height, dest_width, dest_height, rsc); 1339 1340 /* setup the IC resizer and CSC */ 1341 ret = ipu_ic_task_init_rsc(chan->ic, 1342 s_image->tile[tile].width, 1343 s_image->tile[tile].height, 1344 dest_width, 1345 dest_height, 1346 src_cs, dest_cs, 1347 rsc); 1348 if (ret) { 1349 dev_err(priv->ipu->dev, "ipu_ic_task_init failed, %d\n", ret); 1350 return ret; 1351 } 1352 1353 /* init the source MEM-->IC PP IDMAC channel */ 1354 init_idmac_channel(ctx, chan->in_chan, s_image, 1355 IPU_ROTATE_NONE, false, tile); 1356 1357 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1358 /* init the IC PP-->MEM IDMAC channel */ 1359 init_idmac_channel(ctx, chan->out_chan, d_image, 1360 IPU_ROTATE_NONE, true, tile); 1361 1362 /* init the MEM-->IC PP ROT IDMAC channel */ 1363 init_idmac_channel(ctx, chan->rotation_in_chan, d_image, 1364 ctx->rot_mode, true, tile); 1365 1366 /* init the destination IC PP ROT-->MEM IDMAC channel */ 1367 init_idmac_channel(ctx, chan->rotation_out_chan, d_image, 1368 IPU_ROTATE_NONE, false, tile); 1369 1370 /* now link IC PP-->MEM to MEM-->IC PP ROT */ 1371 ipu_idmac_link(chan->out_chan, chan->rotation_in_chan); 1372 } else { 1373 /* init the destination IC PP-->MEM IDMAC channel */ 1374 init_idmac_channel(ctx, chan->out_chan, d_image, 1375 ctx->rot_mode, false, tile); 1376 } 1377 1378 /* enable the IC */ 1379 ipu_ic_enable(chan->ic); 1380 1381 /* set buffers ready */ 1382 ipu_idmac_select_buffer(chan->in_chan, 0); 1383 ipu_idmac_select_buffer(chan->out_chan, 0); 1384 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1385 ipu_idmac_select_buffer(chan->rotation_out_chan, 0); 1386 if (ctx->double_buffering) { 1387 ipu_idmac_select_buffer(chan->in_chan, 1); 1388 ipu_idmac_select_buffer(chan->out_chan, 1); 1389 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1390 ipu_idmac_select_buffer(chan->rotation_out_chan, 1); 1391 } 1392 1393 /* enable the channels! */ 1394 ipu_idmac_enable_channel(chan->in_chan); 1395 ipu_idmac_enable_channel(chan->out_chan); 1396 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1397 ipu_idmac_enable_channel(chan->rotation_in_chan); 1398 ipu_idmac_enable_channel(chan->rotation_out_chan); 1399 } 1400 1401 ipu_ic_task_enable(chan->ic); 1402 1403 ipu_cpmem_dump(chan->in_chan); 1404 ipu_cpmem_dump(chan->out_chan); 1405 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1406 ipu_cpmem_dump(chan->rotation_in_chan); 1407 ipu_cpmem_dump(chan->rotation_out_chan); 1408 } 1409 1410 ipu_dump(priv->ipu); 1411 1412 return 0; 1413 } 1414 1415 /* hold irqlock when calling */ 1416 static int do_run(struct ipu_image_convert_run *run) 1417 { 1418 struct ipu_image_convert_ctx *ctx = run->ctx; 1419 struct ipu_image_convert_chan *chan = ctx->chan; 1420 1421 lockdep_assert_held(&chan->irqlock); 1422 1423 ctx->in.base.phys0 = run->in_phys; 1424 ctx->out.base.phys0 = run->out_phys; 1425 1426 ctx->cur_buf_num = 0; 1427 ctx->next_tile = 1; 1428 1429 /* remove run from pending_q and set as current */ 1430 list_del(&run->list); 1431 chan->current_run = run; 1432 1433 return convert_start(run, 0); 1434 } 1435 1436 /* hold irqlock when calling */ 1437 static void run_next(struct ipu_image_convert_chan *chan) 1438 { 1439 struct ipu_image_convert_priv *priv = chan->priv; 1440 struct ipu_image_convert_run *run, *tmp; 1441 int ret; 1442 1443 lockdep_assert_held(&chan->irqlock); 1444 1445 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 1446 /* skip contexts that are aborting */ 1447 if (run->ctx->aborting) { 1448 dev_dbg(priv->ipu->dev, 1449 "%s: task %u: skipping aborting ctx %p run %p\n", 1450 __func__, chan->ic_task, run->ctx, run); 1451 continue; 1452 } 1453 1454 ret = do_run(run); 1455 if (!ret) 1456 break; 1457 1458 /* 1459 * something went wrong with start, add the run 1460 * to done q and continue to the next run in the 1461 * pending q. 1462 */ 1463 run->status = ret; 1464 list_add_tail(&run->list, &chan->done_q); 1465 chan->current_run = NULL; 1466 } 1467 } 1468 1469 static void empty_done_q(struct ipu_image_convert_chan *chan) 1470 { 1471 struct ipu_image_convert_priv *priv = chan->priv; 1472 struct ipu_image_convert_run *run; 1473 unsigned long flags; 1474 1475 spin_lock_irqsave(&chan->irqlock, flags); 1476 1477 while (!list_empty(&chan->done_q)) { 1478 run = list_entry(chan->done_q.next, 1479 struct ipu_image_convert_run, 1480 list); 1481 1482 list_del(&run->list); 1483 1484 dev_dbg(priv->ipu->dev, 1485 "%s: task %u: completing ctx %p run %p with %d\n", 1486 __func__, chan->ic_task, run->ctx, run, run->status); 1487 1488 /* call the completion callback and free the run */ 1489 spin_unlock_irqrestore(&chan->irqlock, flags); 1490 run->ctx->complete(run, run->ctx->complete_context); 1491 spin_lock_irqsave(&chan->irqlock, flags); 1492 } 1493 1494 spin_unlock_irqrestore(&chan->irqlock, flags); 1495 } 1496 1497 /* 1498 * the bottom half thread clears out the done_q, calling the 1499 * completion handler for each. 1500 */ 1501 static irqreturn_t do_bh(int irq, void *dev_id) 1502 { 1503 struct ipu_image_convert_chan *chan = dev_id; 1504 struct ipu_image_convert_priv *priv = chan->priv; 1505 struct ipu_image_convert_ctx *ctx; 1506 unsigned long flags; 1507 1508 dev_dbg(priv->ipu->dev, "%s: task %u: enter\n", __func__, 1509 chan->ic_task); 1510 1511 empty_done_q(chan); 1512 1513 spin_lock_irqsave(&chan->irqlock, flags); 1514 1515 /* 1516 * the done_q is cleared out, signal any contexts 1517 * that are aborting that abort can complete. 1518 */ 1519 list_for_each_entry(ctx, &chan->ctx_list, list) { 1520 if (ctx->aborting) { 1521 dev_dbg(priv->ipu->dev, 1522 "%s: task %u: signaling abort for ctx %p\n", 1523 __func__, chan->ic_task, ctx); 1524 complete_all(&ctx->aborted); 1525 } 1526 } 1527 1528 spin_unlock_irqrestore(&chan->irqlock, flags); 1529 1530 dev_dbg(priv->ipu->dev, "%s: task %u: exit\n", __func__, 1531 chan->ic_task); 1532 1533 return IRQ_HANDLED; 1534 } 1535 1536 static bool ic_settings_changed(struct ipu_image_convert_ctx *ctx) 1537 { 1538 unsigned int cur_tile = ctx->next_tile - 1; 1539 unsigned int next_tile = ctx->next_tile; 1540 1541 if (ctx->resize_coeffs_h[cur_tile % ctx->in.num_cols] != 1542 ctx->resize_coeffs_h[next_tile % ctx->in.num_cols] || 1543 ctx->resize_coeffs_v[cur_tile / ctx->in.num_cols] != 1544 ctx->resize_coeffs_v[next_tile / ctx->in.num_cols] || 1545 ctx->in.tile[cur_tile].width != ctx->in.tile[next_tile].width || 1546 ctx->in.tile[cur_tile].height != ctx->in.tile[next_tile].height || 1547 ctx->out.tile[cur_tile].width != ctx->out.tile[next_tile].width || 1548 ctx->out.tile[cur_tile].height != ctx->out.tile[next_tile].height) 1549 return true; 1550 1551 return false; 1552 } 1553 1554 /* hold irqlock when calling */ 1555 static irqreturn_t do_irq(struct ipu_image_convert_run *run) 1556 { 1557 struct ipu_image_convert_ctx *ctx = run->ctx; 1558 struct ipu_image_convert_chan *chan = ctx->chan; 1559 struct ipu_image_tile *src_tile, *dst_tile; 1560 struct ipu_image_convert_image *s_image = &ctx->in; 1561 struct ipu_image_convert_image *d_image = &ctx->out; 1562 struct ipuv3_channel *outch; 1563 unsigned int dst_idx; 1564 1565 lockdep_assert_held(&chan->irqlock); 1566 1567 outch = ipu_rot_mode_is_irt(ctx->rot_mode) ? 1568 chan->rotation_out_chan : chan->out_chan; 1569 1570 /* 1571 * It is difficult to stop the channel DMA before the channels 1572 * enter the paused state. Without double-buffering the channels 1573 * are always in a paused state when the EOF irq occurs, so it 1574 * is safe to stop the channels now. For double-buffering we 1575 * just ignore the abort until the operation completes, when it 1576 * is safe to shut down. 1577 */ 1578 if (ctx->aborting && !ctx->double_buffering) { 1579 convert_stop(run); 1580 run->status = -EIO; 1581 goto done; 1582 } 1583 1584 if (ctx->next_tile == ctx->num_tiles) { 1585 /* 1586 * the conversion is complete 1587 */ 1588 convert_stop(run); 1589 run->status = 0; 1590 goto done; 1591 } 1592 1593 /* 1594 * not done, place the next tile buffers. 1595 */ 1596 if (!ctx->double_buffering) { 1597 if (ic_settings_changed(ctx)) { 1598 convert_stop(run); 1599 convert_start(run, ctx->next_tile); 1600 } else { 1601 src_tile = &s_image->tile[ctx->next_tile]; 1602 dst_idx = ctx->out_tile_map[ctx->next_tile]; 1603 dst_tile = &d_image->tile[dst_idx]; 1604 1605 ipu_cpmem_set_buffer(chan->in_chan, 0, 1606 s_image->base.phys0 + 1607 src_tile->offset); 1608 ipu_cpmem_set_buffer(outch, 0, 1609 d_image->base.phys0 + 1610 dst_tile->offset); 1611 if (s_image->fmt->planar) 1612 ipu_cpmem_set_uv_offset(chan->in_chan, 1613 src_tile->u_off, 1614 src_tile->v_off); 1615 if (d_image->fmt->planar) 1616 ipu_cpmem_set_uv_offset(outch, 1617 dst_tile->u_off, 1618 dst_tile->v_off); 1619 1620 ipu_idmac_select_buffer(chan->in_chan, 0); 1621 ipu_idmac_select_buffer(outch, 0); 1622 } 1623 } else if (ctx->next_tile < ctx->num_tiles - 1) { 1624 1625 src_tile = &s_image->tile[ctx->next_tile + 1]; 1626 dst_idx = ctx->out_tile_map[ctx->next_tile + 1]; 1627 dst_tile = &d_image->tile[dst_idx]; 1628 1629 ipu_cpmem_set_buffer(chan->in_chan, ctx->cur_buf_num, 1630 s_image->base.phys0 + src_tile->offset); 1631 ipu_cpmem_set_buffer(outch, ctx->cur_buf_num, 1632 d_image->base.phys0 + dst_tile->offset); 1633 1634 ipu_idmac_select_buffer(chan->in_chan, ctx->cur_buf_num); 1635 ipu_idmac_select_buffer(outch, ctx->cur_buf_num); 1636 1637 ctx->cur_buf_num ^= 1; 1638 } 1639 1640 ctx->next_tile++; 1641 return IRQ_HANDLED; 1642 done: 1643 list_add_tail(&run->list, &chan->done_q); 1644 chan->current_run = NULL; 1645 run_next(chan); 1646 return IRQ_WAKE_THREAD; 1647 } 1648 1649 static irqreturn_t norotate_irq(int irq, void *data) 1650 { 1651 struct ipu_image_convert_chan *chan = data; 1652 struct ipu_image_convert_ctx *ctx; 1653 struct ipu_image_convert_run *run; 1654 unsigned long flags; 1655 irqreturn_t ret; 1656 1657 spin_lock_irqsave(&chan->irqlock, flags); 1658 1659 /* get current run and its context */ 1660 run = chan->current_run; 1661 if (!run) { 1662 ret = IRQ_NONE; 1663 goto out; 1664 } 1665 1666 ctx = run->ctx; 1667 1668 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1669 /* this is a rotation operation, just ignore */ 1670 spin_unlock_irqrestore(&chan->irqlock, flags); 1671 return IRQ_HANDLED; 1672 } 1673 1674 ret = do_irq(run); 1675 out: 1676 spin_unlock_irqrestore(&chan->irqlock, flags); 1677 return ret; 1678 } 1679 1680 static irqreturn_t rotate_irq(int irq, void *data) 1681 { 1682 struct ipu_image_convert_chan *chan = data; 1683 struct ipu_image_convert_priv *priv = chan->priv; 1684 struct ipu_image_convert_ctx *ctx; 1685 struct ipu_image_convert_run *run; 1686 unsigned long flags; 1687 irqreturn_t ret; 1688 1689 spin_lock_irqsave(&chan->irqlock, flags); 1690 1691 /* get current run and its context */ 1692 run = chan->current_run; 1693 if (!run) { 1694 ret = IRQ_NONE; 1695 goto out; 1696 } 1697 1698 ctx = run->ctx; 1699 1700 if (!ipu_rot_mode_is_irt(ctx->rot_mode)) { 1701 /* this was NOT a rotation operation, shouldn't happen */ 1702 dev_err(priv->ipu->dev, "Unexpected rotation interrupt\n"); 1703 spin_unlock_irqrestore(&chan->irqlock, flags); 1704 return IRQ_HANDLED; 1705 } 1706 1707 ret = do_irq(run); 1708 out: 1709 spin_unlock_irqrestore(&chan->irqlock, flags); 1710 return ret; 1711 } 1712 1713 /* 1714 * try to force the completion of runs for this ctx. Called when 1715 * abort wait times out in ipu_image_convert_abort(). 1716 */ 1717 static void force_abort(struct ipu_image_convert_ctx *ctx) 1718 { 1719 struct ipu_image_convert_chan *chan = ctx->chan; 1720 struct ipu_image_convert_run *run; 1721 unsigned long flags; 1722 1723 spin_lock_irqsave(&chan->irqlock, flags); 1724 1725 run = chan->current_run; 1726 if (run && run->ctx == ctx) { 1727 convert_stop(run); 1728 run->status = -EIO; 1729 list_add_tail(&run->list, &chan->done_q); 1730 chan->current_run = NULL; 1731 run_next(chan); 1732 } 1733 1734 spin_unlock_irqrestore(&chan->irqlock, flags); 1735 1736 empty_done_q(chan); 1737 } 1738 1739 static void release_ipu_resources(struct ipu_image_convert_chan *chan) 1740 { 1741 if (chan->out_eof_irq >= 0) 1742 free_irq(chan->out_eof_irq, chan); 1743 if (chan->rot_out_eof_irq >= 0) 1744 free_irq(chan->rot_out_eof_irq, chan); 1745 1746 if (!IS_ERR_OR_NULL(chan->in_chan)) 1747 ipu_idmac_put(chan->in_chan); 1748 if (!IS_ERR_OR_NULL(chan->out_chan)) 1749 ipu_idmac_put(chan->out_chan); 1750 if (!IS_ERR_OR_NULL(chan->rotation_in_chan)) 1751 ipu_idmac_put(chan->rotation_in_chan); 1752 if (!IS_ERR_OR_NULL(chan->rotation_out_chan)) 1753 ipu_idmac_put(chan->rotation_out_chan); 1754 if (!IS_ERR_OR_NULL(chan->ic)) 1755 ipu_ic_put(chan->ic); 1756 1757 chan->in_chan = chan->out_chan = chan->rotation_in_chan = 1758 chan->rotation_out_chan = NULL; 1759 chan->out_eof_irq = chan->rot_out_eof_irq = -1; 1760 } 1761 1762 static int get_ipu_resources(struct ipu_image_convert_chan *chan) 1763 { 1764 const struct ipu_image_convert_dma_chan *dma = chan->dma_ch; 1765 struct ipu_image_convert_priv *priv = chan->priv; 1766 int ret; 1767 1768 /* get IC */ 1769 chan->ic = ipu_ic_get(priv->ipu, chan->ic_task); 1770 if (IS_ERR(chan->ic)) { 1771 dev_err(priv->ipu->dev, "could not acquire IC\n"); 1772 ret = PTR_ERR(chan->ic); 1773 goto err; 1774 } 1775 1776 /* get IDMAC channels */ 1777 chan->in_chan = ipu_idmac_get(priv->ipu, dma->in); 1778 chan->out_chan = ipu_idmac_get(priv->ipu, dma->out); 1779 if (IS_ERR(chan->in_chan) || IS_ERR(chan->out_chan)) { 1780 dev_err(priv->ipu->dev, "could not acquire idmac channels\n"); 1781 ret = -EBUSY; 1782 goto err; 1783 } 1784 1785 chan->rotation_in_chan = ipu_idmac_get(priv->ipu, dma->rot_in); 1786 chan->rotation_out_chan = ipu_idmac_get(priv->ipu, dma->rot_out); 1787 if (IS_ERR(chan->rotation_in_chan) || IS_ERR(chan->rotation_out_chan)) { 1788 dev_err(priv->ipu->dev, 1789 "could not acquire idmac rotation channels\n"); 1790 ret = -EBUSY; 1791 goto err; 1792 } 1793 1794 /* acquire the EOF interrupts */ 1795 chan->out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1796 chan->out_chan, 1797 IPU_IRQ_EOF); 1798 1799 ret = request_threaded_irq(chan->out_eof_irq, norotate_irq, do_bh, 1800 0, "ipu-ic", chan); 1801 if (ret < 0) { 1802 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1803 chan->out_eof_irq); 1804 chan->out_eof_irq = -1; 1805 goto err; 1806 } 1807 1808 chan->rot_out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1809 chan->rotation_out_chan, 1810 IPU_IRQ_EOF); 1811 1812 ret = request_threaded_irq(chan->rot_out_eof_irq, rotate_irq, do_bh, 1813 0, "ipu-ic", chan); 1814 if (ret < 0) { 1815 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1816 chan->rot_out_eof_irq); 1817 chan->rot_out_eof_irq = -1; 1818 goto err; 1819 } 1820 1821 return 0; 1822 err: 1823 release_ipu_resources(chan); 1824 return ret; 1825 } 1826 1827 static int fill_image(struct ipu_image_convert_ctx *ctx, 1828 struct ipu_image_convert_image *ic_image, 1829 struct ipu_image *image, 1830 enum ipu_image_convert_type type) 1831 { 1832 struct ipu_image_convert_priv *priv = ctx->chan->priv; 1833 1834 ic_image->base = *image; 1835 ic_image->type = type; 1836 1837 ic_image->fmt = get_format(image->pix.pixelformat); 1838 if (!ic_image->fmt) { 1839 dev_err(priv->ipu->dev, "pixelformat not supported for %s\n", 1840 type == IMAGE_CONVERT_OUT ? "Output" : "Input"); 1841 return -EINVAL; 1842 } 1843 1844 if (ic_image->fmt->planar) 1845 ic_image->stride = ic_image->base.pix.width; 1846 else 1847 ic_image->stride = ic_image->base.pix.bytesperline; 1848 1849 return 0; 1850 } 1851 1852 /* borrowed from drivers/media/v4l2-core/v4l2-common.c */ 1853 static unsigned int clamp_align(unsigned int x, unsigned int min, 1854 unsigned int max, unsigned int align) 1855 { 1856 /* Bits that must be zero to be aligned */ 1857 unsigned int mask = ~((1 << align) - 1); 1858 1859 /* Clamp to aligned min and max */ 1860 x = clamp(x, (min + ~mask) & mask, max & mask); 1861 1862 /* Round to nearest aligned value */ 1863 if (align) 1864 x = (x + (1 << (align - 1))) & mask; 1865 1866 return x; 1867 } 1868 1869 /* Adjusts input/output images to IPU restrictions */ 1870 void ipu_image_convert_adjust(struct ipu_image *in, struct ipu_image *out, 1871 enum ipu_rotate_mode rot_mode) 1872 { 1873 const struct ipu_image_pixfmt *infmt, *outfmt; 1874 u32 w_align, h_align; 1875 1876 infmt = get_format(in->pix.pixelformat); 1877 outfmt = get_format(out->pix.pixelformat); 1878 1879 /* set some default pixel formats if needed */ 1880 if (!infmt) { 1881 in->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1882 infmt = get_format(V4L2_PIX_FMT_RGB24); 1883 } 1884 if (!outfmt) { 1885 out->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1886 outfmt = get_format(V4L2_PIX_FMT_RGB24); 1887 } 1888 1889 /* image converter does not handle fields */ 1890 in->pix.field = out->pix.field = V4L2_FIELD_NONE; 1891 1892 /* resizer cannot downsize more than 4:1 */ 1893 if (ipu_rot_mode_is_irt(rot_mode)) { 1894 out->pix.height = max_t(__u32, out->pix.height, 1895 in->pix.width / 4); 1896 out->pix.width = max_t(__u32, out->pix.width, 1897 in->pix.height / 4); 1898 } else { 1899 out->pix.width = max_t(__u32, out->pix.width, 1900 in->pix.width / 4); 1901 out->pix.height = max_t(__u32, out->pix.height, 1902 in->pix.height / 4); 1903 } 1904 1905 /* align input width/height */ 1906 w_align = ilog2(tile_width_align(IMAGE_CONVERT_IN, infmt, rot_mode)); 1907 h_align = ilog2(tile_height_align(IMAGE_CONVERT_IN, infmt, rot_mode)); 1908 in->pix.width = clamp_align(in->pix.width, MIN_W, MAX_W, w_align); 1909 in->pix.height = clamp_align(in->pix.height, MIN_H, MAX_H, h_align); 1910 1911 /* align output width/height */ 1912 w_align = ilog2(tile_width_align(IMAGE_CONVERT_OUT, outfmt, rot_mode)); 1913 h_align = ilog2(tile_height_align(IMAGE_CONVERT_OUT, outfmt, rot_mode)); 1914 out->pix.width = clamp_align(out->pix.width, MIN_W, MAX_W, w_align); 1915 out->pix.height = clamp_align(out->pix.height, MIN_H, MAX_H, h_align); 1916 1917 /* set input/output strides and image sizes */ 1918 in->pix.bytesperline = (in->pix.width * infmt->bpp) >> 3; 1919 in->pix.sizeimage = in->pix.height * in->pix.bytesperline; 1920 out->pix.bytesperline = (out->pix.width * outfmt->bpp) >> 3; 1921 out->pix.sizeimage = out->pix.height * out->pix.bytesperline; 1922 } 1923 EXPORT_SYMBOL_GPL(ipu_image_convert_adjust); 1924 1925 /* 1926 * this is used by ipu_image_convert_prepare() to verify set input and 1927 * output images are valid before starting the conversion. Clients can 1928 * also call it before calling ipu_image_convert_prepare(). 1929 */ 1930 int ipu_image_convert_verify(struct ipu_image *in, struct ipu_image *out, 1931 enum ipu_rotate_mode rot_mode) 1932 { 1933 struct ipu_image testin, testout; 1934 1935 testin = *in; 1936 testout = *out; 1937 1938 ipu_image_convert_adjust(&testin, &testout, rot_mode); 1939 1940 if (testin.pix.width != in->pix.width || 1941 testin.pix.height != in->pix.height || 1942 testout.pix.width != out->pix.width || 1943 testout.pix.height != out->pix.height) 1944 return -EINVAL; 1945 1946 return 0; 1947 } 1948 EXPORT_SYMBOL_GPL(ipu_image_convert_verify); 1949 1950 /* 1951 * Call ipu_image_convert_prepare() to prepare for the conversion of 1952 * given images and rotation mode. Returns a new conversion context. 1953 */ 1954 struct ipu_image_convert_ctx * 1955 ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1956 struct ipu_image *in, struct ipu_image *out, 1957 enum ipu_rotate_mode rot_mode, 1958 ipu_image_convert_cb_t complete, 1959 void *complete_context) 1960 { 1961 struct ipu_image_convert_priv *priv = ipu->image_convert_priv; 1962 struct ipu_image_convert_image *s_image, *d_image; 1963 struct ipu_image_convert_chan *chan; 1964 struct ipu_image_convert_ctx *ctx; 1965 unsigned long flags; 1966 bool get_res; 1967 int ret; 1968 1969 if (!in || !out || !complete || 1970 (ic_task != IC_TASK_VIEWFINDER && 1971 ic_task != IC_TASK_POST_PROCESSOR)) 1972 return ERR_PTR(-EINVAL); 1973 1974 /* verify the in/out images before continuing */ 1975 ret = ipu_image_convert_verify(in, out, rot_mode); 1976 if (ret) { 1977 dev_err(priv->ipu->dev, "%s: in/out formats invalid\n", 1978 __func__); 1979 return ERR_PTR(ret); 1980 } 1981 1982 chan = &priv->chan[ic_task]; 1983 1984 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 1985 if (!ctx) 1986 return ERR_PTR(-ENOMEM); 1987 1988 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p\n", __func__, 1989 chan->ic_task, ctx); 1990 1991 ctx->chan = chan; 1992 init_completion(&ctx->aborted); 1993 1994 s_image = &ctx->in; 1995 d_image = &ctx->out; 1996 1997 /* set tiling and rotation */ 1998 d_image->num_rows = num_stripes(out->pix.height); 1999 d_image->num_cols = num_stripes(out->pix.width); 2000 if (ipu_rot_mode_is_irt(rot_mode)) { 2001 s_image->num_rows = d_image->num_cols; 2002 s_image->num_cols = d_image->num_rows; 2003 } else { 2004 s_image->num_rows = d_image->num_rows; 2005 s_image->num_cols = d_image->num_cols; 2006 } 2007 2008 ctx->num_tiles = d_image->num_cols * d_image->num_rows; 2009 ctx->rot_mode = rot_mode; 2010 2011 ret = fill_image(ctx, s_image, in, IMAGE_CONVERT_IN); 2012 if (ret) 2013 goto out_free; 2014 ret = fill_image(ctx, d_image, out, IMAGE_CONVERT_OUT); 2015 if (ret) 2016 goto out_free; 2017 2018 ret = calc_image_resize_coefficients(ctx, in, out); 2019 if (ret) 2020 goto out_free; 2021 2022 calc_out_tile_map(ctx); 2023 2024 find_seams(ctx, s_image, d_image); 2025 2026 calc_tile_dimensions(ctx, s_image); 2027 ret = calc_tile_offsets(ctx, s_image); 2028 if (ret) 2029 goto out_free; 2030 2031 calc_tile_dimensions(ctx, d_image); 2032 ret = calc_tile_offsets(ctx, d_image); 2033 if (ret) 2034 goto out_free; 2035 2036 calc_tile_resize_coefficients(ctx); 2037 2038 dump_format(ctx, s_image); 2039 dump_format(ctx, d_image); 2040 2041 ctx->complete = complete; 2042 ctx->complete_context = complete_context; 2043 2044 /* 2045 * Can we use double-buffering for this operation? If there is 2046 * only one tile (the whole image can be converted in a single 2047 * operation) there's no point in using double-buffering. Also, 2048 * the IPU's IDMAC channels allow only a single U and V plane 2049 * offset shared between both buffers, but these offsets change 2050 * for every tile, and therefore would have to be updated for 2051 * each buffer which is not possible. So double-buffering is 2052 * impossible when either the source or destination images are 2053 * a planar format (YUV420, YUV422P, etc.). 2054 */ 2055 ctx->double_buffering = (ctx->num_tiles > 1 && 2056 !s_image->fmt->planar && 2057 !d_image->fmt->planar); 2058 2059 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 2060 unsigned long intermediate_size = d_image->tile[0].size; 2061 unsigned int i; 2062 2063 for (i = 1; i < ctx->num_tiles; i++) { 2064 if (d_image->tile[i].size > intermediate_size) 2065 intermediate_size = d_image->tile[i].size; 2066 } 2067 2068 ret = alloc_dma_buf(priv, &ctx->rot_intermediate[0], 2069 intermediate_size); 2070 if (ret) 2071 goto out_free; 2072 if (ctx->double_buffering) { 2073 ret = alloc_dma_buf(priv, 2074 &ctx->rot_intermediate[1], 2075 intermediate_size); 2076 if (ret) 2077 goto out_free_dmabuf0; 2078 } 2079 } 2080 2081 spin_lock_irqsave(&chan->irqlock, flags); 2082 2083 get_res = list_empty(&chan->ctx_list); 2084 2085 list_add_tail(&ctx->list, &chan->ctx_list); 2086 2087 spin_unlock_irqrestore(&chan->irqlock, flags); 2088 2089 if (get_res) { 2090 ret = get_ipu_resources(chan); 2091 if (ret) 2092 goto out_free_dmabuf1; 2093 } 2094 2095 return ctx; 2096 2097 out_free_dmabuf1: 2098 free_dma_buf(priv, &ctx->rot_intermediate[1]); 2099 spin_lock_irqsave(&chan->irqlock, flags); 2100 list_del(&ctx->list); 2101 spin_unlock_irqrestore(&chan->irqlock, flags); 2102 out_free_dmabuf0: 2103 free_dma_buf(priv, &ctx->rot_intermediate[0]); 2104 out_free: 2105 kfree(ctx); 2106 return ERR_PTR(ret); 2107 } 2108 EXPORT_SYMBOL_GPL(ipu_image_convert_prepare); 2109 2110 /* 2111 * Carry out a single image conversion run. Only the physaddr's of the input 2112 * and output image buffers are needed. The conversion context must have 2113 * been created previously with ipu_image_convert_prepare(). 2114 */ 2115 int ipu_image_convert_queue(struct ipu_image_convert_run *run) 2116 { 2117 struct ipu_image_convert_chan *chan; 2118 struct ipu_image_convert_priv *priv; 2119 struct ipu_image_convert_ctx *ctx; 2120 unsigned long flags; 2121 int ret = 0; 2122 2123 if (!run || !run->ctx || !run->in_phys || !run->out_phys) 2124 return -EINVAL; 2125 2126 ctx = run->ctx; 2127 chan = ctx->chan; 2128 priv = chan->priv; 2129 2130 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p run %p\n", __func__, 2131 chan->ic_task, ctx, run); 2132 2133 INIT_LIST_HEAD(&run->list); 2134 2135 spin_lock_irqsave(&chan->irqlock, flags); 2136 2137 if (ctx->aborting) { 2138 ret = -EIO; 2139 goto unlock; 2140 } 2141 2142 list_add_tail(&run->list, &chan->pending_q); 2143 2144 if (!chan->current_run) { 2145 ret = do_run(run); 2146 if (ret) 2147 chan->current_run = NULL; 2148 } 2149 unlock: 2150 spin_unlock_irqrestore(&chan->irqlock, flags); 2151 return ret; 2152 } 2153 EXPORT_SYMBOL_GPL(ipu_image_convert_queue); 2154 2155 /* Abort any active or pending conversions for this context */ 2156 static void __ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 2157 { 2158 struct ipu_image_convert_chan *chan = ctx->chan; 2159 struct ipu_image_convert_priv *priv = chan->priv; 2160 struct ipu_image_convert_run *run, *active_run, *tmp; 2161 unsigned long flags; 2162 int run_count, ret; 2163 2164 spin_lock_irqsave(&chan->irqlock, flags); 2165 2166 /* move all remaining pending runs in this context to done_q */ 2167 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 2168 if (run->ctx != ctx) 2169 continue; 2170 run->status = -EIO; 2171 list_move_tail(&run->list, &chan->done_q); 2172 } 2173 2174 run_count = get_run_count(ctx, &chan->done_q); 2175 active_run = (chan->current_run && chan->current_run->ctx == ctx) ? 2176 chan->current_run : NULL; 2177 2178 if (active_run) 2179 reinit_completion(&ctx->aborted); 2180 2181 ctx->aborting = true; 2182 2183 spin_unlock_irqrestore(&chan->irqlock, flags); 2184 2185 if (!run_count && !active_run) { 2186 dev_dbg(priv->ipu->dev, 2187 "%s: task %u: no abort needed for ctx %p\n", 2188 __func__, chan->ic_task, ctx); 2189 return; 2190 } 2191 2192 if (!active_run) { 2193 empty_done_q(chan); 2194 return; 2195 } 2196 2197 dev_dbg(priv->ipu->dev, 2198 "%s: task %u: wait for completion: %d runs\n", 2199 __func__, chan->ic_task, run_count); 2200 2201 ret = wait_for_completion_timeout(&ctx->aborted, 2202 msecs_to_jiffies(10000)); 2203 if (ret == 0) { 2204 dev_warn(priv->ipu->dev, "%s: timeout\n", __func__); 2205 force_abort(ctx); 2206 } 2207 } 2208 2209 void ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 2210 { 2211 __ipu_image_convert_abort(ctx); 2212 ctx->aborting = false; 2213 } 2214 EXPORT_SYMBOL_GPL(ipu_image_convert_abort); 2215 2216 /* Unprepare image conversion context */ 2217 void ipu_image_convert_unprepare(struct ipu_image_convert_ctx *ctx) 2218 { 2219 struct ipu_image_convert_chan *chan = ctx->chan; 2220 struct ipu_image_convert_priv *priv = chan->priv; 2221 unsigned long flags; 2222 bool put_res; 2223 2224 /* make sure no runs are hanging around */ 2225 __ipu_image_convert_abort(ctx); 2226 2227 dev_dbg(priv->ipu->dev, "%s: task %u: removing ctx %p\n", __func__, 2228 chan->ic_task, ctx); 2229 2230 spin_lock_irqsave(&chan->irqlock, flags); 2231 2232 list_del(&ctx->list); 2233 2234 put_res = list_empty(&chan->ctx_list); 2235 2236 spin_unlock_irqrestore(&chan->irqlock, flags); 2237 2238 if (put_res) 2239 release_ipu_resources(chan); 2240 2241 free_dma_buf(priv, &ctx->rot_intermediate[1]); 2242 free_dma_buf(priv, &ctx->rot_intermediate[0]); 2243 2244 kfree(ctx); 2245 } 2246 EXPORT_SYMBOL_GPL(ipu_image_convert_unprepare); 2247 2248 /* 2249 * "Canned" asynchronous single image conversion. Allocates and returns 2250 * a new conversion run. On successful return the caller must free the 2251 * run and call ipu_image_convert_unprepare() after conversion completes. 2252 */ 2253 struct ipu_image_convert_run * 2254 ipu_image_convert(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 2255 struct ipu_image *in, struct ipu_image *out, 2256 enum ipu_rotate_mode rot_mode, 2257 ipu_image_convert_cb_t complete, 2258 void *complete_context) 2259 { 2260 struct ipu_image_convert_ctx *ctx; 2261 struct ipu_image_convert_run *run; 2262 int ret; 2263 2264 ctx = ipu_image_convert_prepare(ipu, ic_task, in, out, rot_mode, 2265 complete, complete_context); 2266 if (IS_ERR(ctx)) 2267 return ERR_CAST(ctx); 2268 2269 run = kzalloc(sizeof(*run), GFP_KERNEL); 2270 if (!run) { 2271 ipu_image_convert_unprepare(ctx); 2272 return ERR_PTR(-ENOMEM); 2273 } 2274 2275 run->ctx = ctx; 2276 run->in_phys = in->phys0; 2277 run->out_phys = out->phys0; 2278 2279 ret = ipu_image_convert_queue(run); 2280 if (ret) { 2281 ipu_image_convert_unprepare(ctx); 2282 kfree(run); 2283 return ERR_PTR(ret); 2284 } 2285 2286 return run; 2287 } 2288 EXPORT_SYMBOL_GPL(ipu_image_convert); 2289 2290 /* "Canned" synchronous single image conversion */ 2291 static void image_convert_sync_complete(struct ipu_image_convert_run *run, 2292 void *data) 2293 { 2294 struct completion *comp = data; 2295 2296 complete(comp); 2297 } 2298 2299 int ipu_image_convert_sync(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 2300 struct ipu_image *in, struct ipu_image *out, 2301 enum ipu_rotate_mode rot_mode) 2302 { 2303 struct ipu_image_convert_run *run; 2304 struct completion comp; 2305 int ret; 2306 2307 init_completion(&comp); 2308 2309 run = ipu_image_convert(ipu, ic_task, in, out, rot_mode, 2310 image_convert_sync_complete, &comp); 2311 if (IS_ERR(run)) 2312 return PTR_ERR(run); 2313 2314 ret = wait_for_completion_timeout(&comp, msecs_to_jiffies(10000)); 2315 ret = (ret == 0) ? -ETIMEDOUT : 0; 2316 2317 ipu_image_convert_unprepare(run->ctx); 2318 kfree(run); 2319 2320 return ret; 2321 } 2322 EXPORT_SYMBOL_GPL(ipu_image_convert_sync); 2323 2324 int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev) 2325 { 2326 struct ipu_image_convert_priv *priv; 2327 int i; 2328 2329 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 2330 if (!priv) 2331 return -ENOMEM; 2332 2333 ipu->image_convert_priv = priv; 2334 priv->ipu = ipu; 2335 2336 for (i = 0; i < IC_NUM_TASKS; i++) { 2337 struct ipu_image_convert_chan *chan = &priv->chan[i]; 2338 2339 chan->ic_task = i; 2340 chan->priv = priv; 2341 chan->dma_ch = &image_convert_dma_chan[i]; 2342 chan->out_eof_irq = -1; 2343 chan->rot_out_eof_irq = -1; 2344 2345 spin_lock_init(&chan->irqlock); 2346 INIT_LIST_HEAD(&chan->ctx_list); 2347 INIT_LIST_HEAD(&chan->pending_q); 2348 INIT_LIST_HEAD(&chan->done_q); 2349 } 2350 2351 return 0; 2352 } 2353 2354 void ipu_image_convert_exit(struct ipu_soc *ipu) 2355 { 2356 } 2357