1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2012-2016 Mentor Graphics Inc. 4 * 5 * Queued image conversion support, with tiling and rotation. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/dma-mapping.h> 10 #include <video/imx-ipu-image-convert.h> 11 #include "ipu-prv.h" 12 13 /* 14 * The IC Resizer has a restriction that the output frame from the 15 * resizer must be 1024 or less in both width (pixels) and height 16 * (lines). 17 * 18 * The image converter attempts to split up a conversion when 19 * the desired output (converted) frame resolution exceeds the 20 * IC resizer limit of 1024 in either dimension. 21 * 22 * If either dimension of the output frame exceeds the limit, the 23 * dimension is split into 1, 2, or 4 equal stripes, for a maximum 24 * of 4*4 or 16 tiles. A conversion is then carried out for each 25 * tile (but taking care to pass the full frame stride length to 26 * the DMA channel's parameter memory!). IDMA double-buffering is used 27 * to convert each tile back-to-back when possible (see note below 28 * when double_buffering boolean is set). 29 * 30 * Note that the input frame must be split up into the same number 31 * of tiles as the output frame: 32 * 33 * +---------+-----+ 34 * +-----+---+ | A | B | 35 * | A | B | | | | 36 * +-----+---+ --> +---------+-----+ 37 * | C | D | | C | D | 38 * +-----+---+ | | | 39 * +---------+-----+ 40 * 41 * Clockwise 90° rotations are handled by first rescaling into a 42 * reusable temporary tile buffer and then rotating with the 8x8 43 * block rotator, writing to the correct destination: 44 * 45 * +-----+-----+ 46 * | | | 47 * +-----+---+ +---------+ | C | A | 48 * | A | B | | A,B, | | | | | 49 * +-----+---+ --> | C,D | | --> | | | 50 * | C | D | +---------+ +-----+-----+ 51 * +-----+---+ | D | B | 52 * | | | 53 * +-----+-----+ 54 * 55 * If the 8x8 block rotator is used, horizontal or vertical flipping 56 * is done during the rotation step, otherwise flipping is done 57 * during the scaling step. 58 * With rotation or flipping, tile order changes between input and 59 * output image. Tiles are numbered row major from top left to bottom 60 * right for both input and output image. 61 */ 62 63 #define MAX_STRIPES_W 4 64 #define MAX_STRIPES_H 4 65 #define MAX_TILES (MAX_STRIPES_W * MAX_STRIPES_H) 66 67 #define MIN_W 16 68 #define MIN_H 8 69 #define MAX_W 4096 70 #define MAX_H 4096 71 72 enum ipu_image_convert_type { 73 IMAGE_CONVERT_IN = 0, 74 IMAGE_CONVERT_OUT, 75 }; 76 77 struct ipu_image_convert_dma_buf { 78 void *virt; 79 dma_addr_t phys; 80 unsigned long len; 81 }; 82 83 struct ipu_image_convert_dma_chan { 84 int in; 85 int out; 86 int rot_in; 87 int rot_out; 88 int vdi_in_p; 89 int vdi_in; 90 int vdi_in_n; 91 }; 92 93 /* dimensions of one tile */ 94 struct ipu_image_tile { 95 u32 width; 96 u32 height; 97 u32 left; 98 u32 top; 99 /* size and strides are in bytes */ 100 u32 size; 101 u32 stride; 102 u32 rot_stride; 103 /* start Y or packed offset of this tile */ 104 u32 offset; 105 /* offset from start to tile in U plane, for planar formats */ 106 u32 u_off; 107 /* offset from start to tile in V plane, for planar formats */ 108 u32 v_off; 109 }; 110 111 struct ipu_image_convert_image { 112 struct ipu_image base; 113 enum ipu_image_convert_type type; 114 115 const struct ipu_image_pixfmt *fmt; 116 unsigned int stride; 117 118 /* # of rows (horizontal stripes) if dest height is > 1024 */ 119 unsigned int num_rows; 120 /* # of columns (vertical stripes) if dest width is > 1024 */ 121 unsigned int num_cols; 122 123 struct ipu_image_tile tile[MAX_TILES]; 124 }; 125 126 struct ipu_image_pixfmt { 127 u32 fourcc; /* V4L2 fourcc */ 128 int bpp; /* total bpp */ 129 int uv_width_dec; /* decimation in width for U/V planes */ 130 int uv_height_dec; /* decimation in height for U/V planes */ 131 bool planar; /* planar format */ 132 bool uv_swapped; /* U and V planes are swapped */ 133 bool uv_packed; /* partial planar (U and V in same plane) */ 134 }; 135 136 struct ipu_image_convert_ctx; 137 struct ipu_image_convert_chan; 138 struct ipu_image_convert_priv; 139 140 struct ipu_image_convert_ctx { 141 struct ipu_image_convert_chan *chan; 142 143 ipu_image_convert_cb_t complete; 144 void *complete_context; 145 146 /* Source/destination image data and rotation mode */ 147 struct ipu_image_convert_image in; 148 struct ipu_image_convert_image out; 149 struct ipu_ic_csc csc; 150 enum ipu_rotate_mode rot_mode; 151 u32 downsize_coeff_h; 152 u32 downsize_coeff_v; 153 u32 image_resize_coeff_h; 154 u32 image_resize_coeff_v; 155 u32 resize_coeffs_h[MAX_STRIPES_W]; 156 u32 resize_coeffs_v[MAX_STRIPES_H]; 157 158 /* intermediate buffer for rotation */ 159 struct ipu_image_convert_dma_buf rot_intermediate[2]; 160 161 /* current buffer number for double buffering */ 162 int cur_buf_num; 163 164 bool aborting; 165 struct completion aborted; 166 167 /* can we use double-buffering for this conversion operation? */ 168 bool double_buffering; 169 /* num_rows * num_cols */ 170 unsigned int num_tiles; 171 /* next tile to process */ 172 unsigned int next_tile; 173 /* where to place converted tile in dest image */ 174 unsigned int out_tile_map[MAX_TILES]; 175 176 struct list_head list; 177 }; 178 179 struct ipu_image_convert_chan { 180 struct ipu_image_convert_priv *priv; 181 182 enum ipu_ic_task ic_task; 183 const struct ipu_image_convert_dma_chan *dma_ch; 184 185 struct ipu_ic *ic; 186 struct ipuv3_channel *in_chan; 187 struct ipuv3_channel *out_chan; 188 struct ipuv3_channel *rotation_in_chan; 189 struct ipuv3_channel *rotation_out_chan; 190 191 /* the IPU end-of-frame irqs */ 192 int out_eof_irq; 193 int rot_out_eof_irq; 194 195 spinlock_t irqlock; 196 197 /* list of convert contexts */ 198 struct list_head ctx_list; 199 /* queue of conversion runs */ 200 struct list_head pending_q; 201 /* queue of completed runs */ 202 struct list_head done_q; 203 204 /* the current conversion run */ 205 struct ipu_image_convert_run *current_run; 206 }; 207 208 struct ipu_image_convert_priv { 209 struct ipu_image_convert_chan chan[IC_NUM_TASKS]; 210 struct ipu_soc *ipu; 211 }; 212 213 static const struct ipu_image_convert_dma_chan 214 image_convert_dma_chan[IC_NUM_TASKS] = { 215 [IC_TASK_VIEWFINDER] = { 216 .in = IPUV3_CHANNEL_MEM_IC_PRP_VF, 217 .out = IPUV3_CHANNEL_IC_PRP_VF_MEM, 218 .rot_in = IPUV3_CHANNEL_MEM_ROT_VF, 219 .rot_out = IPUV3_CHANNEL_ROT_VF_MEM, 220 .vdi_in_p = IPUV3_CHANNEL_MEM_VDI_PREV, 221 .vdi_in = IPUV3_CHANNEL_MEM_VDI_CUR, 222 .vdi_in_n = IPUV3_CHANNEL_MEM_VDI_NEXT, 223 }, 224 [IC_TASK_POST_PROCESSOR] = { 225 .in = IPUV3_CHANNEL_MEM_IC_PP, 226 .out = IPUV3_CHANNEL_IC_PP_MEM, 227 .rot_in = IPUV3_CHANNEL_MEM_ROT_PP, 228 .rot_out = IPUV3_CHANNEL_ROT_PP_MEM, 229 }, 230 }; 231 232 static const struct ipu_image_pixfmt image_convert_formats[] = { 233 { 234 .fourcc = V4L2_PIX_FMT_RGB565, 235 .bpp = 16, 236 }, { 237 .fourcc = V4L2_PIX_FMT_RGB24, 238 .bpp = 24, 239 }, { 240 .fourcc = V4L2_PIX_FMT_BGR24, 241 .bpp = 24, 242 }, { 243 .fourcc = V4L2_PIX_FMT_RGB32, 244 .bpp = 32, 245 }, { 246 .fourcc = V4L2_PIX_FMT_BGR32, 247 .bpp = 32, 248 }, { 249 .fourcc = V4L2_PIX_FMT_XRGB32, 250 .bpp = 32, 251 }, { 252 .fourcc = V4L2_PIX_FMT_XBGR32, 253 .bpp = 32, 254 }, { 255 .fourcc = V4L2_PIX_FMT_BGRX32, 256 .bpp = 32, 257 }, { 258 .fourcc = V4L2_PIX_FMT_RGBX32, 259 .bpp = 32, 260 }, { 261 .fourcc = V4L2_PIX_FMT_YUYV, 262 .bpp = 16, 263 .uv_width_dec = 2, 264 .uv_height_dec = 1, 265 }, { 266 .fourcc = V4L2_PIX_FMT_UYVY, 267 .bpp = 16, 268 .uv_width_dec = 2, 269 .uv_height_dec = 1, 270 }, { 271 .fourcc = V4L2_PIX_FMT_YUV420, 272 .bpp = 12, 273 .planar = true, 274 .uv_width_dec = 2, 275 .uv_height_dec = 2, 276 }, { 277 .fourcc = V4L2_PIX_FMT_YVU420, 278 .bpp = 12, 279 .planar = true, 280 .uv_width_dec = 2, 281 .uv_height_dec = 2, 282 .uv_swapped = true, 283 }, { 284 .fourcc = V4L2_PIX_FMT_NV12, 285 .bpp = 12, 286 .planar = true, 287 .uv_width_dec = 2, 288 .uv_height_dec = 2, 289 .uv_packed = true, 290 }, { 291 .fourcc = V4L2_PIX_FMT_YUV422P, 292 .bpp = 16, 293 .planar = true, 294 .uv_width_dec = 2, 295 .uv_height_dec = 1, 296 }, { 297 .fourcc = V4L2_PIX_FMT_NV16, 298 .bpp = 16, 299 .planar = true, 300 .uv_width_dec = 2, 301 .uv_height_dec = 1, 302 .uv_packed = true, 303 }, 304 }; 305 306 static const struct ipu_image_pixfmt *get_format(u32 fourcc) 307 { 308 const struct ipu_image_pixfmt *ret = NULL; 309 unsigned int i; 310 311 for (i = 0; i < ARRAY_SIZE(image_convert_formats); i++) { 312 if (image_convert_formats[i].fourcc == fourcc) { 313 ret = &image_convert_formats[i]; 314 break; 315 } 316 } 317 318 return ret; 319 } 320 321 static void dump_format(struct ipu_image_convert_ctx *ctx, 322 struct ipu_image_convert_image *ic_image) 323 { 324 struct ipu_image_convert_chan *chan = ctx->chan; 325 struct ipu_image_convert_priv *priv = chan->priv; 326 327 dev_dbg(priv->ipu->dev, 328 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles), %c%c%c%c\n", 329 chan->ic_task, ctx, 330 ic_image->type == IMAGE_CONVERT_OUT ? "Output" : "Input", 331 ic_image->base.pix.width, ic_image->base.pix.height, 332 ic_image->num_cols, ic_image->num_rows, 333 ic_image->fmt->fourcc & 0xff, 334 (ic_image->fmt->fourcc >> 8) & 0xff, 335 (ic_image->fmt->fourcc >> 16) & 0xff, 336 (ic_image->fmt->fourcc >> 24) & 0xff); 337 } 338 339 int ipu_image_convert_enum_format(int index, u32 *fourcc) 340 { 341 const struct ipu_image_pixfmt *fmt; 342 343 if (index >= (int)ARRAY_SIZE(image_convert_formats)) 344 return -EINVAL; 345 346 /* Format found */ 347 fmt = &image_convert_formats[index]; 348 *fourcc = fmt->fourcc; 349 return 0; 350 } 351 EXPORT_SYMBOL_GPL(ipu_image_convert_enum_format); 352 353 static void free_dma_buf(struct ipu_image_convert_priv *priv, 354 struct ipu_image_convert_dma_buf *buf) 355 { 356 if (buf->virt) 357 dma_free_coherent(priv->ipu->dev, 358 buf->len, buf->virt, buf->phys); 359 buf->virt = NULL; 360 buf->phys = 0; 361 } 362 363 static int alloc_dma_buf(struct ipu_image_convert_priv *priv, 364 struct ipu_image_convert_dma_buf *buf, 365 int size) 366 { 367 buf->len = PAGE_ALIGN(size); 368 buf->virt = dma_alloc_coherent(priv->ipu->dev, buf->len, &buf->phys, 369 GFP_DMA | GFP_KERNEL); 370 if (!buf->virt) { 371 dev_err(priv->ipu->dev, "failed to alloc dma buffer\n"); 372 return -ENOMEM; 373 } 374 375 return 0; 376 } 377 378 static inline int num_stripes(int dim) 379 { 380 return (dim - 1) / 1024 + 1; 381 } 382 383 /* 384 * Calculate downsizing coefficients, which are the same for all tiles, 385 * and initial bilinear resizing coefficients, which are used to find the 386 * best seam positions. 387 * Also determine the number of tiles necessary to guarantee that no tile 388 * is larger than 1024 pixels in either dimension at the output and between 389 * IC downsizing and main processing sections. 390 */ 391 static int calc_image_resize_coefficients(struct ipu_image_convert_ctx *ctx, 392 struct ipu_image *in, 393 struct ipu_image *out) 394 { 395 u32 downsized_width = in->rect.width; 396 u32 downsized_height = in->rect.height; 397 u32 downsize_coeff_v = 0; 398 u32 downsize_coeff_h = 0; 399 u32 resized_width = out->rect.width; 400 u32 resized_height = out->rect.height; 401 u32 resize_coeff_h; 402 u32 resize_coeff_v; 403 u32 cols; 404 u32 rows; 405 406 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 407 resized_width = out->rect.height; 408 resized_height = out->rect.width; 409 } 410 411 /* Do not let invalid input lead to an endless loop below */ 412 if (WARN_ON(resized_width == 0 || resized_height == 0)) 413 return -EINVAL; 414 415 while (downsized_width >= resized_width * 2) { 416 downsized_width >>= 1; 417 downsize_coeff_h++; 418 } 419 420 while (downsized_height >= resized_height * 2) { 421 downsized_height >>= 1; 422 downsize_coeff_v++; 423 } 424 425 /* 426 * Calculate the bilinear resizing coefficients that could be used if 427 * we were converting with a single tile. The bottom right output pixel 428 * should sample as close as possible to the bottom right input pixel 429 * out of the decimator, but not overshoot it: 430 */ 431 resize_coeff_h = 8192 * (downsized_width - 1) / (resized_width - 1); 432 resize_coeff_v = 8192 * (downsized_height - 1) / (resized_height - 1); 433 434 /* 435 * Both the output of the IC downsizing section before being passed to 436 * the IC main processing section and the final output of the IC main 437 * processing section must be <= 1024 pixels in both dimensions. 438 */ 439 cols = num_stripes(max_t(u32, downsized_width, resized_width)); 440 rows = num_stripes(max_t(u32, downsized_height, resized_height)); 441 442 dev_dbg(ctx->chan->priv->ipu->dev, 443 "%s: hscale: >>%u, *8192/%u vscale: >>%u, *8192/%u, %ux%u tiles\n", 444 __func__, downsize_coeff_h, resize_coeff_h, downsize_coeff_v, 445 resize_coeff_v, cols, rows); 446 447 if (downsize_coeff_h > 2 || downsize_coeff_v > 2 || 448 resize_coeff_h > 0x3fff || resize_coeff_v > 0x3fff) 449 return -EINVAL; 450 451 ctx->downsize_coeff_h = downsize_coeff_h; 452 ctx->downsize_coeff_v = downsize_coeff_v; 453 ctx->image_resize_coeff_h = resize_coeff_h; 454 ctx->image_resize_coeff_v = resize_coeff_v; 455 ctx->in.num_cols = cols; 456 ctx->in.num_rows = rows; 457 458 return 0; 459 } 460 461 #define round_closest(x, y) round_down((x) + (y)/2, (y)) 462 463 /* 464 * Find the best aligned seam position for the given column / row index. 465 * Rotation and image offsets are out of scope. 466 * 467 * @index: column / row index, used to calculate valid interval 468 * @in_edge: input right / bottom edge 469 * @out_edge: output right / bottom edge 470 * @in_align: input alignment, either horizontal 8-byte line start address 471 * alignment, or pixel alignment due to image format 472 * @out_align: output alignment, either horizontal 8-byte line start address 473 * alignment, or pixel alignment due to image format or rotator 474 * block size 475 * @in_burst: horizontal input burst size in case of horizontal flip 476 * @out_burst: horizontal output burst size or rotator block size 477 * @downsize_coeff: downsizing section coefficient 478 * @resize_coeff: main processing section resizing coefficient 479 * @_in_seam: aligned input seam position return value 480 * @_out_seam: aligned output seam position return value 481 */ 482 static void find_best_seam(struct ipu_image_convert_ctx *ctx, 483 unsigned int index, 484 unsigned int in_edge, 485 unsigned int out_edge, 486 unsigned int in_align, 487 unsigned int out_align, 488 unsigned int in_burst, 489 unsigned int out_burst, 490 unsigned int downsize_coeff, 491 unsigned int resize_coeff, 492 u32 *_in_seam, 493 u32 *_out_seam) 494 { 495 struct device *dev = ctx->chan->priv->ipu->dev; 496 unsigned int out_pos; 497 /* Input / output seam position candidates */ 498 unsigned int out_seam = 0; 499 unsigned int in_seam = 0; 500 unsigned int min_diff = UINT_MAX; 501 unsigned int out_start; 502 unsigned int out_end; 503 unsigned int in_start; 504 unsigned int in_end; 505 506 /* Start within 1024 pixels of the right / bottom edge */ 507 out_start = max_t(int, index * out_align, out_edge - 1024); 508 /* End before having to add more columns to the left / rows above */ 509 out_end = min_t(unsigned int, out_edge, index * 1024 + 1); 510 511 /* 512 * Limit input seam position to make sure that the downsized input tile 513 * to the right or bottom does not exceed 1024 pixels. 514 */ 515 in_start = max_t(int, index * in_align, 516 in_edge - (1024 << downsize_coeff)); 517 in_end = min_t(unsigned int, in_edge, 518 index * (1024 << downsize_coeff) + 1); 519 520 /* 521 * Output tiles must start at a multiple of 8 bytes horizontally and 522 * possibly at an even line horizontally depending on the pixel format. 523 * Only consider output aligned positions for the seam. 524 */ 525 out_start = round_up(out_start, out_align); 526 for (out_pos = out_start; out_pos < out_end; out_pos += out_align) { 527 unsigned int in_pos; 528 unsigned int in_pos_aligned; 529 unsigned int in_pos_rounded; 530 unsigned int abs_diff; 531 532 /* 533 * Tiles in the right row / bottom column may not be allowed to 534 * overshoot horizontally / vertically. out_burst may be the 535 * actual DMA burst size, or the rotator block size. 536 */ 537 if ((out_burst > 1) && (out_edge - out_pos) % out_burst) 538 continue; 539 540 /* 541 * Input sample position, corresponding to out_pos, 19.13 fixed 542 * point. 543 */ 544 in_pos = (out_pos * resize_coeff) << downsize_coeff; 545 /* 546 * The closest input sample position that we could actually 547 * start the input tile at, 19.13 fixed point. 548 */ 549 in_pos_aligned = round_closest(in_pos, 8192U * in_align); 550 /* Convert 19.13 fixed point to integer */ 551 in_pos_rounded = in_pos_aligned / 8192U; 552 553 if (in_pos_rounded < in_start) 554 continue; 555 if (in_pos_rounded >= in_end) 556 break; 557 558 if ((in_burst > 1) && 559 (in_edge - in_pos_rounded) % in_burst) 560 continue; 561 562 if (in_pos < in_pos_aligned) 563 abs_diff = in_pos_aligned - in_pos; 564 else 565 abs_diff = in_pos - in_pos_aligned; 566 567 if (abs_diff < min_diff) { 568 in_seam = in_pos_rounded; 569 out_seam = out_pos; 570 min_diff = abs_diff; 571 } 572 } 573 574 *_out_seam = out_seam; 575 *_in_seam = in_seam; 576 577 dev_dbg(dev, "%s: out_seam %u(%u) in [%u, %u], in_seam %u(%u) in [%u, %u] diff %u.%03u\n", 578 __func__, out_seam, out_align, out_start, out_end, 579 in_seam, in_align, in_start, in_end, min_diff / 8192, 580 DIV_ROUND_CLOSEST(min_diff % 8192 * 1000, 8192)); 581 } 582 583 /* 584 * Tile left edges are required to be aligned to multiples of 8 bytes 585 * by the IDMAC. 586 */ 587 static inline u32 tile_left_align(const struct ipu_image_pixfmt *fmt) 588 { 589 if (fmt->planar) 590 return fmt->uv_packed ? 8 : 8 * fmt->uv_width_dec; 591 else 592 return fmt->bpp == 32 ? 2 : fmt->bpp == 16 ? 4 : 8; 593 } 594 595 /* 596 * Tile top edge alignment is only limited by chroma subsampling. 597 */ 598 static inline u32 tile_top_align(const struct ipu_image_pixfmt *fmt) 599 { 600 return fmt->uv_height_dec > 1 ? 2 : 1; 601 } 602 603 static inline u32 tile_width_align(enum ipu_image_convert_type type, 604 const struct ipu_image_pixfmt *fmt, 605 enum ipu_rotate_mode rot_mode) 606 { 607 if (type == IMAGE_CONVERT_IN) { 608 /* 609 * The IC burst reads 8 pixels at a time. Reading beyond the 610 * end of the line is usually acceptable. Those pixels are 611 * ignored, unless the IC has to write the scaled line in 612 * reverse. 613 */ 614 return (!ipu_rot_mode_is_irt(rot_mode) && 615 (rot_mode & IPU_ROT_BIT_HFLIP)) ? 8 : 2; 616 } 617 618 /* 619 * Align to 16x16 pixel blocks for planar 4:2:0 chroma subsampled 620 * formats to guarantee 8-byte aligned line start addresses in the 621 * chroma planes when IRT is used. Align to 8x8 pixel IRT block size 622 * for all other formats. 623 */ 624 return (ipu_rot_mode_is_irt(rot_mode) && 625 fmt->planar && !fmt->uv_packed) ? 626 8 * fmt->uv_width_dec : 8; 627 } 628 629 static inline u32 tile_height_align(enum ipu_image_convert_type type, 630 const struct ipu_image_pixfmt *fmt, 631 enum ipu_rotate_mode rot_mode) 632 { 633 if (type == IMAGE_CONVERT_IN || !ipu_rot_mode_is_irt(rot_mode)) 634 return 2; 635 636 /* 637 * Align to 16x16 pixel blocks for planar 4:2:0 chroma subsampled 638 * formats to guarantee 8-byte aligned line start addresses in the 639 * chroma planes when IRT is used. Align to 8x8 pixel IRT block size 640 * for all other formats. 641 */ 642 return (fmt->planar && !fmt->uv_packed) ? 8 * fmt->uv_width_dec : 8; 643 } 644 645 /* 646 * Fill in left position and width and for all tiles in an input column, and 647 * for all corresponding output tiles. If the 90° rotator is used, the output 648 * tiles are in a row, and output tile top position and height are set. 649 */ 650 static void fill_tile_column(struct ipu_image_convert_ctx *ctx, 651 unsigned int col, 652 struct ipu_image_convert_image *in, 653 unsigned int in_left, unsigned int in_width, 654 struct ipu_image_convert_image *out, 655 unsigned int out_left, unsigned int out_width) 656 { 657 unsigned int row, tile_idx; 658 struct ipu_image_tile *in_tile, *out_tile; 659 660 for (row = 0; row < in->num_rows; row++) { 661 tile_idx = in->num_cols * row + col; 662 in_tile = &in->tile[tile_idx]; 663 out_tile = &out->tile[ctx->out_tile_map[tile_idx]]; 664 665 in_tile->left = in_left; 666 in_tile->width = in_width; 667 668 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 669 out_tile->top = out_left; 670 out_tile->height = out_width; 671 } else { 672 out_tile->left = out_left; 673 out_tile->width = out_width; 674 } 675 } 676 } 677 678 /* 679 * Fill in top position and height and for all tiles in an input row, and 680 * for all corresponding output tiles. If the 90° rotator is used, the output 681 * tiles are in a column, and output tile left position and width are set. 682 */ 683 static void fill_tile_row(struct ipu_image_convert_ctx *ctx, unsigned int row, 684 struct ipu_image_convert_image *in, 685 unsigned int in_top, unsigned int in_height, 686 struct ipu_image_convert_image *out, 687 unsigned int out_top, unsigned int out_height) 688 { 689 unsigned int col, tile_idx; 690 struct ipu_image_tile *in_tile, *out_tile; 691 692 for (col = 0; col < in->num_cols; col++) { 693 tile_idx = in->num_cols * row + col; 694 in_tile = &in->tile[tile_idx]; 695 out_tile = &out->tile[ctx->out_tile_map[tile_idx]]; 696 697 in_tile->top = in_top; 698 in_tile->height = in_height; 699 700 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 701 out_tile->left = out_top; 702 out_tile->width = out_height; 703 } else { 704 out_tile->top = out_top; 705 out_tile->height = out_height; 706 } 707 } 708 } 709 710 /* 711 * Find the best horizontal and vertical seam positions to split into tiles. 712 * Minimize the fractional part of the input sampling position for the 713 * top / left pixels of each tile. 714 */ 715 static void find_seams(struct ipu_image_convert_ctx *ctx, 716 struct ipu_image_convert_image *in, 717 struct ipu_image_convert_image *out) 718 { 719 struct device *dev = ctx->chan->priv->ipu->dev; 720 unsigned int resized_width = out->base.rect.width; 721 unsigned int resized_height = out->base.rect.height; 722 unsigned int col; 723 unsigned int row; 724 unsigned int in_left_align = tile_left_align(in->fmt); 725 unsigned int in_top_align = tile_top_align(in->fmt); 726 unsigned int out_left_align = tile_left_align(out->fmt); 727 unsigned int out_top_align = tile_top_align(out->fmt); 728 unsigned int out_width_align = tile_width_align(out->type, out->fmt, 729 ctx->rot_mode); 730 unsigned int out_height_align = tile_height_align(out->type, out->fmt, 731 ctx->rot_mode); 732 unsigned int in_right = in->base.rect.width; 733 unsigned int in_bottom = in->base.rect.height; 734 unsigned int out_right = out->base.rect.width; 735 unsigned int out_bottom = out->base.rect.height; 736 unsigned int flipped_out_left; 737 unsigned int flipped_out_top; 738 739 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 740 /* Switch width/height and align top left to IRT block size */ 741 resized_width = out->base.rect.height; 742 resized_height = out->base.rect.width; 743 out_left_align = out_height_align; 744 out_top_align = out_width_align; 745 out_width_align = out_left_align; 746 out_height_align = out_top_align; 747 out_right = out->base.rect.height; 748 out_bottom = out->base.rect.width; 749 } 750 751 for (col = in->num_cols - 1; col > 0; col--) { 752 bool allow_in_overshoot = ipu_rot_mode_is_irt(ctx->rot_mode) || 753 !(ctx->rot_mode & IPU_ROT_BIT_HFLIP); 754 bool allow_out_overshoot = (col < in->num_cols - 1) && 755 !(ctx->rot_mode & IPU_ROT_BIT_HFLIP); 756 unsigned int in_left; 757 unsigned int out_left; 758 759 /* 760 * Align input width to burst length if the scaling step flips 761 * horizontally. 762 */ 763 764 find_best_seam(ctx, col, 765 in_right, out_right, 766 in_left_align, out_left_align, 767 allow_in_overshoot ? 1 : 8 /* burst length */, 768 allow_out_overshoot ? 1 : out_width_align, 769 ctx->downsize_coeff_h, ctx->image_resize_coeff_h, 770 &in_left, &out_left); 771 772 if (ctx->rot_mode & IPU_ROT_BIT_HFLIP) 773 flipped_out_left = resized_width - out_right; 774 else 775 flipped_out_left = out_left; 776 777 fill_tile_column(ctx, col, in, in_left, in_right - in_left, 778 out, flipped_out_left, out_right - out_left); 779 780 dev_dbg(dev, "%s: col %u: %u, %u -> %u, %u\n", __func__, col, 781 in_left, in_right - in_left, 782 flipped_out_left, out_right - out_left); 783 784 in_right = in_left; 785 out_right = out_left; 786 } 787 788 flipped_out_left = (ctx->rot_mode & IPU_ROT_BIT_HFLIP) ? 789 resized_width - out_right : 0; 790 791 fill_tile_column(ctx, 0, in, 0, in_right, 792 out, flipped_out_left, out_right); 793 794 dev_dbg(dev, "%s: col 0: 0, %u -> %u, %u\n", __func__, 795 in_right, flipped_out_left, out_right); 796 797 for (row = in->num_rows - 1; row > 0; row--) { 798 bool allow_overshoot = row < in->num_rows - 1; 799 unsigned int in_top; 800 unsigned int out_top; 801 802 find_best_seam(ctx, row, 803 in_bottom, out_bottom, 804 in_top_align, out_top_align, 805 1, allow_overshoot ? 1 : out_height_align, 806 ctx->downsize_coeff_v, ctx->image_resize_coeff_v, 807 &in_top, &out_top); 808 809 if ((ctx->rot_mode & IPU_ROT_BIT_VFLIP) ^ 810 ipu_rot_mode_is_irt(ctx->rot_mode)) 811 flipped_out_top = resized_height - out_bottom; 812 else 813 flipped_out_top = out_top; 814 815 fill_tile_row(ctx, row, in, in_top, in_bottom - in_top, 816 out, flipped_out_top, out_bottom - out_top); 817 818 dev_dbg(dev, "%s: row %u: %u, %u -> %u, %u\n", __func__, row, 819 in_top, in_bottom - in_top, 820 flipped_out_top, out_bottom - out_top); 821 822 in_bottom = in_top; 823 out_bottom = out_top; 824 } 825 826 if ((ctx->rot_mode & IPU_ROT_BIT_VFLIP) ^ 827 ipu_rot_mode_is_irt(ctx->rot_mode)) 828 flipped_out_top = resized_height - out_bottom; 829 else 830 flipped_out_top = 0; 831 832 fill_tile_row(ctx, 0, in, 0, in_bottom, 833 out, flipped_out_top, out_bottom); 834 835 dev_dbg(dev, "%s: row 0: 0, %u -> %u, %u\n", __func__, 836 in_bottom, flipped_out_top, out_bottom); 837 } 838 839 static void calc_tile_dimensions(struct ipu_image_convert_ctx *ctx, 840 struct ipu_image_convert_image *image) 841 { 842 struct ipu_image_convert_chan *chan = ctx->chan; 843 struct ipu_image_convert_priv *priv = chan->priv; 844 unsigned int i; 845 846 for (i = 0; i < ctx->num_tiles; i++) { 847 struct ipu_image_tile *tile; 848 const unsigned int row = i / image->num_cols; 849 const unsigned int col = i % image->num_cols; 850 851 if (image->type == IMAGE_CONVERT_OUT) 852 tile = &image->tile[ctx->out_tile_map[i]]; 853 else 854 tile = &image->tile[i]; 855 856 tile->size = ((tile->height * image->fmt->bpp) >> 3) * 857 tile->width; 858 859 if (image->fmt->planar) { 860 tile->stride = tile->width; 861 tile->rot_stride = tile->height; 862 } else { 863 tile->stride = 864 (image->fmt->bpp * tile->width) >> 3; 865 tile->rot_stride = 866 (image->fmt->bpp * tile->height) >> 3; 867 } 868 869 dev_dbg(priv->ipu->dev, 870 "task %u: ctx %p: %s@[%u,%u]: %ux%u@%u,%u\n", 871 chan->ic_task, ctx, 872 image->type == IMAGE_CONVERT_IN ? "Input" : "Output", 873 row, col, 874 tile->width, tile->height, tile->left, tile->top); 875 } 876 } 877 878 /* 879 * Use the rotation transformation to find the tile coordinates 880 * (row, col) of a tile in the destination frame that corresponds 881 * to the given tile coordinates of a source frame. The destination 882 * coordinate is then converted to a tile index. 883 */ 884 static int transform_tile_index(struct ipu_image_convert_ctx *ctx, 885 int src_row, int src_col) 886 { 887 struct ipu_image_convert_chan *chan = ctx->chan; 888 struct ipu_image_convert_priv *priv = chan->priv; 889 struct ipu_image_convert_image *s_image = &ctx->in; 890 struct ipu_image_convert_image *d_image = &ctx->out; 891 int dst_row, dst_col; 892 893 /* with no rotation it's a 1:1 mapping */ 894 if (ctx->rot_mode == IPU_ROTATE_NONE) 895 return src_row * s_image->num_cols + src_col; 896 897 /* 898 * before doing the transform, first we have to translate 899 * source row,col for an origin in the center of s_image 900 */ 901 src_row = src_row * 2 - (s_image->num_rows - 1); 902 src_col = src_col * 2 - (s_image->num_cols - 1); 903 904 /* do the rotation transform */ 905 if (ctx->rot_mode & IPU_ROT_BIT_90) { 906 dst_col = -src_row; 907 dst_row = src_col; 908 } else { 909 dst_col = src_col; 910 dst_row = src_row; 911 } 912 913 /* apply flip */ 914 if (ctx->rot_mode & IPU_ROT_BIT_HFLIP) 915 dst_col = -dst_col; 916 if (ctx->rot_mode & IPU_ROT_BIT_VFLIP) 917 dst_row = -dst_row; 918 919 dev_dbg(priv->ipu->dev, "task %u: ctx %p: [%d,%d] --> [%d,%d]\n", 920 chan->ic_task, ctx, src_col, src_row, dst_col, dst_row); 921 922 /* 923 * finally translate dest row,col using an origin in upper 924 * left of d_image 925 */ 926 dst_row += d_image->num_rows - 1; 927 dst_col += d_image->num_cols - 1; 928 dst_row /= 2; 929 dst_col /= 2; 930 931 return dst_row * d_image->num_cols + dst_col; 932 } 933 934 /* 935 * Fill the out_tile_map[] with transformed destination tile indeces. 936 */ 937 static void calc_out_tile_map(struct ipu_image_convert_ctx *ctx) 938 { 939 struct ipu_image_convert_image *s_image = &ctx->in; 940 unsigned int row, col, tile = 0; 941 942 for (row = 0; row < s_image->num_rows; row++) { 943 for (col = 0; col < s_image->num_cols; col++) { 944 ctx->out_tile_map[tile] = 945 transform_tile_index(ctx, row, col); 946 tile++; 947 } 948 } 949 } 950 951 static int calc_tile_offsets_planar(struct ipu_image_convert_ctx *ctx, 952 struct ipu_image_convert_image *image) 953 { 954 struct ipu_image_convert_chan *chan = ctx->chan; 955 struct ipu_image_convert_priv *priv = chan->priv; 956 const struct ipu_image_pixfmt *fmt = image->fmt; 957 unsigned int row, col, tile = 0; 958 u32 H, top, y_stride, uv_stride; 959 u32 uv_row_off, uv_col_off, uv_off, u_off, v_off, tmp; 960 u32 y_row_off, y_col_off, y_off; 961 u32 y_size, uv_size; 962 963 /* setup some convenience vars */ 964 H = image->base.pix.height; 965 966 y_stride = image->stride; 967 uv_stride = y_stride / fmt->uv_width_dec; 968 if (fmt->uv_packed) 969 uv_stride *= 2; 970 971 y_size = H * y_stride; 972 uv_size = y_size / (fmt->uv_width_dec * fmt->uv_height_dec); 973 974 for (row = 0; row < image->num_rows; row++) { 975 top = image->tile[tile].top; 976 y_row_off = top * y_stride; 977 uv_row_off = (top * uv_stride) / fmt->uv_height_dec; 978 979 for (col = 0; col < image->num_cols; col++) { 980 y_col_off = image->tile[tile].left; 981 uv_col_off = y_col_off / fmt->uv_width_dec; 982 if (fmt->uv_packed) 983 uv_col_off *= 2; 984 985 y_off = y_row_off + y_col_off; 986 uv_off = uv_row_off + uv_col_off; 987 988 u_off = y_size - y_off + uv_off; 989 v_off = (fmt->uv_packed) ? 0 : u_off + uv_size; 990 if (fmt->uv_swapped) { 991 tmp = u_off; 992 u_off = v_off; 993 v_off = tmp; 994 } 995 996 image->tile[tile].offset = y_off; 997 image->tile[tile].u_off = u_off; 998 image->tile[tile++].v_off = v_off; 999 1000 if ((y_off & 0x7) || (u_off & 0x7) || (v_off & 0x7)) { 1001 dev_err(priv->ipu->dev, 1002 "task %u: ctx %p: %s@[%d,%d]: " 1003 "y_off %08x, u_off %08x, v_off %08x\n", 1004 chan->ic_task, ctx, 1005 image->type == IMAGE_CONVERT_IN ? 1006 "Input" : "Output", row, col, 1007 y_off, u_off, v_off); 1008 return -EINVAL; 1009 } 1010 } 1011 } 1012 1013 return 0; 1014 } 1015 1016 static int calc_tile_offsets_packed(struct ipu_image_convert_ctx *ctx, 1017 struct ipu_image_convert_image *image) 1018 { 1019 struct ipu_image_convert_chan *chan = ctx->chan; 1020 struct ipu_image_convert_priv *priv = chan->priv; 1021 const struct ipu_image_pixfmt *fmt = image->fmt; 1022 unsigned int row, col, tile = 0; 1023 u32 bpp, stride, offset; 1024 u32 row_off, col_off; 1025 1026 /* setup some convenience vars */ 1027 stride = image->stride; 1028 bpp = fmt->bpp; 1029 1030 for (row = 0; row < image->num_rows; row++) { 1031 row_off = image->tile[tile].top * stride; 1032 1033 for (col = 0; col < image->num_cols; col++) { 1034 col_off = (image->tile[tile].left * bpp) >> 3; 1035 1036 offset = row_off + col_off; 1037 1038 image->tile[tile].offset = offset; 1039 image->tile[tile].u_off = 0; 1040 image->tile[tile++].v_off = 0; 1041 1042 if (offset & 0x7) { 1043 dev_err(priv->ipu->dev, 1044 "task %u: ctx %p: %s@[%d,%d]: " 1045 "phys %08x\n", 1046 chan->ic_task, ctx, 1047 image->type == IMAGE_CONVERT_IN ? 1048 "Input" : "Output", row, col, 1049 row_off + col_off); 1050 return -EINVAL; 1051 } 1052 } 1053 } 1054 1055 return 0; 1056 } 1057 1058 static int calc_tile_offsets(struct ipu_image_convert_ctx *ctx, 1059 struct ipu_image_convert_image *image) 1060 { 1061 if (image->fmt->planar) 1062 return calc_tile_offsets_planar(ctx, image); 1063 1064 return calc_tile_offsets_packed(ctx, image); 1065 } 1066 1067 /* 1068 * Calculate the resizing ratio for the IC main processing section given input 1069 * size, fixed downsizing coefficient, and output size. 1070 * Either round to closest for the next tile's first pixel to minimize seams 1071 * and distortion (for all but right column / bottom row), or round down to 1072 * avoid sampling beyond the edges of the input image for this tile's last 1073 * pixel. 1074 * Returns the resizing coefficient, resizing ratio is 8192.0 / resize_coeff. 1075 */ 1076 static u32 calc_resize_coeff(u32 input_size, u32 downsize_coeff, 1077 u32 output_size, bool allow_overshoot) 1078 { 1079 u32 downsized = input_size >> downsize_coeff; 1080 1081 if (allow_overshoot) 1082 return DIV_ROUND_CLOSEST(8192 * downsized, output_size); 1083 else 1084 return 8192 * (downsized - 1) / (output_size - 1); 1085 } 1086 1087 /* 1088 * Slightly modify resize coefficients per tile to hide the bilinear 1089 * interpolator reset at tile borders, shifting the right / bottom edge 1090 * by up to a half input pixel. This removes noticeable seams between 1091 * tiles at higher upscaling factors. 1092 */ 1093 static void calc_tile_resize_coefficients(struct ipu_image_convert_ctx *ctx) 1094 { 1095 struct ipu_image_convert_chan *chan = ctx->chan; 1096 struct ipu_image_convert_priv *priv = chan->priv; 1097 struct ipu_image_tile *in_tile, *out_tile; 1098 unsigned int col, row, tile_idx; 1099 unsigned int last_output; 1100 1101 for (col = 0; col < ctx->in.num_cols; col++) { 1102 bool closest = (col < ctx->in.num_cols - 1) && 1103 !(ctx->rot_mode & IPU_ROT_BIT_HFLIP); 1104 u32 resized_width; 1105 u32 resize_coeff_h; 1106 1107 tile_idx = col; 1108 in_tile = &ctx->in.tile[tile_idx]; 1109 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 1110 1111 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1112 resized_width = out_tile->height; 1113 else 1114 resized_width = out_tile->width; 1115 1116 resize_coeff_h = calc_resize_coeff(in_tile->width, 1117 ctx->downsize_coeff_h, 1118 resized_width, closest); 1119 1120 dev_dbg(priv->ipu->dev, "%s: column %u hscale: *8192/%u\n", 1121 __func__, col, resize_coeff_h); 1122 1123 1124 for (row = 0; row < ctx->in.num_rows; row++) { 1125 tile_idx = row * ctx->in.num_cols + col; 1126 in_tile = &ctx->in.tile[tile_idx]; 1127 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 1128 1129 /* 1130 * With the horizontal scaling factor known, round up 1131 * resized width (output width or height) to burst size. 1132 */ 1133 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1134 out_tile->height = round_up(resized_width, 8); 1135 else 1136 out_tile->width = round_up(resized_width, 8); 1137 1138 /* 1139 * Calculate input width from the last accessed input 1140 * pixel given resized width and scaling coefficients. 1141 * Round up to burst size. 1142 */ 1143 last_output = round_up(resized_width, 8) - 1; 1144 if (closest) 1145 last_output++; 1146 in_tile->width = round_up( 1147 (DIV_ROUND_UP(last_output * resize_coeff_h, 1148 8192) + 1) 1149 << ctx->downsize_coeff_h, 8); 1150 } 1151 1152 ctx->resize_coeffs_h[col] = resize_coeff_h; 1153 } 1154 1155 for (row = 0; row < ctx->in.num_rows; row++) { 1156 bool closest = (row < ctx->in.num_rows - 1) && 1157 !(ctx->rot_mode & IPU_ROT_BIT_VFLIP); 1158 u32 resized_height; 1159 u32 resize_coeff_v; 1160 1161 tile_idx = row * ctx->in.num_cols; 1162 in_tile = &ctx->in.tile[tile_idx]; 1163 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 1164 1165 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1166 resized_height = out_tile->width; 1167 else 1168 resized_height = out_tile->height; 1169 1170 resize_coeff_v = calc_resize_coeff(in_tile->height, 1171 ctx->downsize_coeff_v, 1172 resized_height, closest); 1173 1174 dev_dbg(priv->ipu->dev, "%s: row %u vscale: *8192/%u\n", 1175 __func__, row, resize_coeff_v); 1176 1177 for (col = 0; col < ctx->in.num_cols; col++) { 1178 tile_idx = row * ctx->in.num_cols + col; 1179 in_tile = &ctx->in.tile[tile_idx]; 1180 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 1181 1182 /* 1183 * With the vertical scaling factor known, round up 1184 * resized height (output width or height) to IDMAC 1185 * limitations. 1186 */ 1187 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1188 out_tile->width = round_up(resized_height, 2); 1189 else 1190 out_tile->height = round_up(resized_height, 2); 1191 1192 /* 1193 * Calculate input width from the last accessed input 1194 * pixel given resized height and scaling coefficients. 1195 * Align to IDMAC restrictions. 1196 */ 1197 last_output = round_up(resized_height, 2) - 1; 1198 if (closest) 1199 last_output++; 1200 in_tile->height = round_up( 1201 (DIV_ROUND_UP(last_output * resize_coeff_v, 1202 8192) + 1) 1203 << ctx->downsize_coeff_v, 2); 1204 } 1205 1206 ctx->resize_coeffs_v[row] = resize_coeff_v; 1207 } 1208 } 1209 1210 /* 1211 * return the number of runs in given queue (pending_q or done_q) 1212 * for this context. hold irqlock when calling. 1213 */ 1214 static int get_run_count(struct ipu_image_convert_ctx *ctx, 1215 struct list_head *q) 1216 { 1217 struct ipu_image_convert_run *run; 1218 int count = 0; 1219 1220 lockdep_assert_held(&ctx->chan->irqlock); 1221 1222 list_for_each_entry(run, q, list) { 1223 if (run->ctx == ctx) 1224 count++; 1225 } 1226 1227 return count; 1228 } 1229 1230 static void convert_stop(struct ipu_image_convert_run *run) 1231 { 1232 struct ipu_image_convert_ctx *ctx = run->ctx; 1233 struct ipu_image_convert_chan *chan = ctx->chan; 1234 struct ipu_image_convert_priv *priv = chan->priv; 1235 1236 dev_dbg(priv->ipu->dev, "%s: task %u: stopping ctx %p run %p\n", 1237 __func__, chan->ic_task, ctx, run); 1238 1239 /* disable IC tasks and the channels */ 1240 ipu_ic_task_disable(chan->ic); 1241 ipu_idmac_disable_channel(chan->in_chan); 1242 ipu_idmac_disable_channel(chan->out_chan); 1243 1244 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1245 ipu_idmac_disable_channel(chan->rotation_in_chan); 1246 ipu_idmac_disable_channel(chan->rotation_out_chan); 1247 ipu_idmac_unlink(chan->out_chan, chan->rotation_in_chan); 1248 } 1249 1250 ipu_ic_disable(chan->ic); 1251 } 1252 1253 static void init_idmac_channel(struct ipu_image_convert_ctx *ctx, 1254 struct ipuv3_channel *channel, 1255 struct ipu_image_convert_image *image, 1256 enum ipu_rotate_mode rot_mode, 1257 bool rot_swap_width_height, 1258 unsigned int tile) 1259 { 1260 struct ipu_image_convert_chan *chan = ctx->chan; 1261 unsigned int burst_size; 1262 u32 width, height, stride; 1263 dma_addr_t addr0, addr1 = 0; 1264 struct ipu_image tile_image; 1265 unsigned int tile_idx[2]; 1266 1267 if (image->type == IMAGE_CONVERT_OUT) { 1268 tile_idx[0] = ctx->out_tile_map[tile]; 1269 tile_idx[1] = ctx->out_tile_map[1]; 1270 } else { 1271 tile_idx[0] = tile; 1272 tile_idx[1] = 1; 1273 } 1274 1275 if (rot_swap_width_height) { 1276 width = image->tile[tile_idx[0]].height; 1277 height = image->tile[tile_idx[0]].width; 1278 stride = image->tile[tile_idx[0]].rot_stride; 1279 addr0 = ctx->rot_intermediate[0].phys; 1280 if (ctx->double_buffering) 1281 addr1 = ctx->rot_intermediate[1].phys; 1282 } else { 1283 width = image->tile[tile_idx[0]].width; 1284 height = image->tile[tile_idx[0]].height; 1285 stride = image->stride; 1286 addr0 = image->base.phys0 + 1287 image->tile[tile_idx[0]].offset; 1288 if (ctx->double_buffering) 1289 addr1 = image->base.phys0 + 1290 image->tile[tile_idx[1]].offset; 1291 } 1292 1293 ipu_cpmem_zero(channel); 1294 1295 memset(&tile_image, 0, sizeof(tile_image)); 1296 tile_image.pix.width = tile_image.rect.width = width; 1297 tile_image.pix.height = tile_image.rect.height = height; 1298 tile_image.pix.bytesperline = stride; 1299 tile_image.pix.pixelformat = image->fmt->fourcc; 1300 tile_image.phys0 = addr0; 1301 tile_image.phys1 = addr1; 1302 if (image->fmt->planar && !rot_swap_width_height) { 1303 tile_image.u_offset = image->tile[tile_idx[0]].u_off; 1304 tile_image.v_offset = image->tile[tile_idx[0]].v_off; 1305 } 1306 1307 ipu_cpmem_set_image(channel, &tile_image); 1308 1309 if (rot_mode) 1310 ipu_cpmem_set_rotation(channel, rot_mode); 1311 1312 /* 1313 * Skip writing U and V components to odd rows in the output 1314 * channels for planar 4:2:0. 1315 */ 1316 if ((channel == chan->out_chan || 1317 channel == chan->rotation_out_chan) && 1318 image->fmt->planar && image->fmt->uv_height_dec == 2) 1319 ipu_cpmem_skip_odd_chroma_rows(channel); 1320 1321 if (channel == chan->rotation_in_chan || 1322 channel == chan->rotation_out_chan) { 1323 burst_size = 8; 1324 ipu_cpmem_set_block_mode(channel); 1325 } else 1326 burst_size = (width % 16) ? 8 : 16; 1327 1328 ipu_cpmem_set_burstsize(channel, burst_size); 1329 1330 ipu_ic_task_idma_init(chan->ic, channel, width, height, 1331 burst_size, rot_mode); 1332 1333 /* 1334 * Setting a non-zero AXI ID collides with the PRG AXI snooping, so 1335 * only do this when there is no PRG present. 1336 */ 1337 if (!channel->ipu->prg_priv) 1338 ipu_cpmem_set_axi_id(channel, 1); 1339 1340 ipu_idmac_set_double_buffer(channel, ctx->double_buffering); 1341 } 1342 1343 static int convert_start(struct ipu_image_convert_run *run, unsigned int tile) 1344 { 1345 struct ipu_image_convert_ctx *ctx = run->ctx; 1346 struct ipu_image_convert_chan *chan = ctx->chan; 1347 struct ipu_image_convert_priv *priv = chan->priv; 1348 struct ipu_image_convert_image *s_image = &ctx->in; 1349 struct ipu_image_convert_image *d_image = &ctx->out; 1350 unsigned int dst_tile = ctx->out_tile_map[tile]; 1351 unsigned int dest_width, dest_height; 1352 unsigned int col, row; 1353 u32 rsc; 1354 int ret; 1355 1356 dev_dbg(priv->ipu->dev, "%s: task %u: starting ctx %p run %p tile %u -> %u\n", 1357 __func__, chan->ic_task, ctx, run, tile, dst_tile); 1358 1359 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1360 /* swap width/height for resizer */ 1361 dest_width = d_image->tile[dst_tile].height; 1362 dest_height = d_image->tile[dst_tile].width; 1363 } else { 1364 dest_width = d_image->tile[dst_tile].width; 1365 dest_height = d_image->tile[dst_tile].height; 1366 } 1367 1368 row = tile / s_image->num_cols; 1369 col = tile % s_image->num_cols; 1370 1371 rsc = (ctx->downsize_coeff_v << 30) | 1372 (ctx->resize_coeffs_v[row] << 16) | 1373 (ctx->downsize_coeff_h << 14) | 1374 (ctx->resize_coeffs_h[col]); 1375 1376 dev_dbg(priv->ipu->dev, "%s: %ux%u -> %ux%u (rsc = 0x%x)\n", 1377 __func__, s_image->tile[tile].width, 1378 s_image->tile[tile].height, dest_width, dest_height, rsc); 1379 1380 /* setup the IC resizer and CSC */ 1381 ret = ipu_ic_task_init_rsc(chan->ic, &ctx->csc, 1382 s_image->tile[tile].width, 1383 s_image->tile[tile].height, 1384 dest_width, 1385 dest_height, 1386 rsc); 1387 if (ret) { 1388 dev_err(priv->ipu->dev, "ipu_ic_task_init failed, %d\n", ret); 1389 return ret; 1390 } 1391 1392 /* init the source MEM-->IC PP IDMAC channel */ 1393 init_idmac_channel(ctx, chan->in_chan, s_image, 1394 IPU_ROTATE_NONE, false, tile); 1395 1396 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1397 /* init the IC PP-->MEM IDMAC channel */ 1398 init_idmac_channel(ctx, chan->out_chan, d_image, 1399 IPU_ROTATE_NONE, true, tile); 1400 1401 /* init the MEM-->IC PP ROT IDMAC channel */ 1402 init_idmac_channel(ctx, chan->rotation_in_chan, d_image, 1403 ctx->rot_mode, true, tile); 1404 1405 /* init the destination IC PP ROT-->MEM IDMAC channel */ 1406 init_idmac_channel(ctx, chan->rotation_out_chan, d_image, 1407 IPU_ROTATE_NONE, false, tile); 1408 1409 /* now link IC PP-->MEM to MEM-->IC PP ROT */ 1410 ipu_idmac_link(chan->out_chan, chan->rotation_in_chan); 1411 } else { 1412 /* init the destination IC PP-->MEM IDMAC channel */ 1413 init_idmac_channel(ctx, chan->out_chan, d_image, 1414 ctx->rot_mode, false, tile); 1415 } 1416 1417 /* enable the IC */ 1418 ipu_ic_enable(chan->ic); 1419 1420 /* set buffers ready */ 1421 ipu_idmac_select_buffer(chan->in_chan, 0); 1422 ipu_idmac_select_buffer(chan->out_chan, 0); 1423 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1424 ipu_idmac_select_buffer(chan->rotation_out_chan, 0); 1425 if (ctx->double_buffering) { 1426 ipu_idmac_select_buffer(chan->in_chan, 1); 1427 ipu_idmac_select_buffer(chan->out_chan, 1); 1428 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1429 ipu_idmac_select_buffer(chan->rotation_out_chan, 1); 1430 } 1431 1432 /* enable the channels! */ 1433 ipu_idmac_enable_channel(chan->in_chan); 1434 ipu_idmac_enable_channel(chan->out_chan); 1435 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1436 ipu_idmac_enable_channel(chan->rotation_in_chan); 1437 ipu_idmac_enable_channel(chan->rotation_out_chan); 1438 } 1439 1440 ipu_ic_task_enable(chan->ic); 1441 1442 ipu_cpmem_dump(chan->in_chan); 1443 ipu_cpmem_dump(chan->out_chan); 1444 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1445 ipu_cpmem_dump(chan->rotation_in_chan); 1446 ipu_cpmem_dump(chan->rotation_out_chan); 1447 } 1448 1449 ipu_dump(priv->ipu); 1450 1451 return 0; 1452 } 1453 1454 /* hold irqlock when calling */ 1455 static int do_run(struct ipu_image_convert_run *run) 1456 { 1457 struct ipu_image_convert_ctx *ctx = run->ctx; 1458 struct ipu_image_convert_chan *chan = ctx->chan; 1459 1460 lockdep_assert_held(&chan->irqlock); 1461 1462 ctx->in.base.phys0 = run->in_phys; 1463 ctx->out.base.phys0 = run->out_phys; 1464 1465 ctx->cur_buf_num = 0; 1466 ctx->next_tile = 1; 1467 1468 /* remove run from pending_q and set as current */ 1469 list_del(&run->list); 1470 chan->current_run = run; 1471 1472 return convert_start(run, 0); 1473 } 1474 1475 /* hold irqlock when calling */ 1476 static void run_next(struct ipu_image_convert_chan *chan) 1477 { 1478 struct ipu_image_convert_priv *priv = chan->priv; 1479 struct ipu_image_convert_run *run, *tmp; 1480 int ret; 1481 1482 lockdep_assert_held(&chan->irqlock); 1483 1484 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 1485 /* skip contexts that are aborting */ 1486 if (run->ctx->aborting) { 1487 dev_dbg(priv->ipu->dev, 1488 "%s: task %u: skipping aborting ctx %p run %p\n", 1489 __func__, chan->ic_task, run->ctx, run); 1490 continue; 1491 } 1492 1493 ret = do_run(run); 1494 if (!ret) 1495 break; 1496 1497 /* 1498 * something went wrong with start, add the run 1499 * to done q and continue to the next run in the 1500 * pending q. 1501 */ 1502 run->status = ret; 1503 list_add_tail(&run->list, &chan->done_q); 1504 chan->current_run = NULL; 1505 } 1506 } 1507 1508 static void empty_done_q(struct ipu_image_convert_chan *chan) 1509 { 1510 struct ipu_image_convert_priv *priv = chan->priv; 1511 struct ipu_image_convert_run *run; 1512 unsigned long flags; 1513 1514 spin_lock_irqsave(&chan->irqlock, flags); 1515 1516 while (!list_empty(&chan->done_q)) { 1517 run = list_entry(chan->done_q.next, 1518 struct ipu_image_convert_run, 1519 list); 1520 1521 list_del(&run->list); 1522 1523 dev_dbg(priv->ipu->dev, 1524 "%s: task %u: completing ctx %p run %p with %d\n", 1525 __func__, chan->ic_task, run->ctx, run, run->status); 1526 1527 /* call the completion callback and free the run */ 1528 spin_unlock_irqrestore(&chan->irqlock, flags); 1529 run->ctx->complete(run, run->ctx->complete_context); 1530 spin_lock_irqsave(&chan->irqlock, flags); 1531 } 1532 1533 spin_unlock_irqrestore(&chan->irqlock, flags); 1534 } 1535 1536 /* 1537 * the bottom half thread clears out the done_q, calling the 1538 * completion handler for each. 1539 */ 1540 static irqreturn_t do_bh(int irq, void *dev_id) 1541 { 1542 struct ipu_image_convert_chan *chan = dev_id; 1543 struct ipu_image_convert_priv *priv = chan->priv; 1544 struct ipu_image_convert_ctx *ctx; 1545 unsigned long flags; 1546 1547 dev_dbg(priv->ipu->dev, "%s: task %u: enter\n", __func__, 1548 chan->ic_task); 1549 1550 empty_done_q(chan); 1551 1552 spin_lock_irqsave(&chan->irqlock, flags); 1553 1554 /* 1555 * the done_q is cleared out, signal any contexts 1556 * that are aborting that abort can complete. 1557 */ 1558 list_for_each_entry(ctx, &chan->ctx_list, list) { 1559 if (ctx->aborting) { 1560 dev_dbg(priv->ipu->dev, 1561 "%s: task %u: signaling abort for ctx %p\n", 1562 __func__, chan->ic_task, ctx); 1563 complete_all(&ctx->aborted); 1564 } 1565 } 1566 1567 spin_unlock_irqrestore(&chan->irqlock, flags); 1568 1569 dev_dbg(priv->ipu->dev, "%s: task %u: exit\n", __func__, 1570 chan->ic_task); 1571 1572 return IRQ_HANDLED; 1573 } 1574 1575 static bool ic_settings_changed(struct ipu_image_convert_ctx *ctx) 1576 { 1577 unsigned int cur_tile = ctx->next_tile - 1; 1578 unsigned int next_tile = ctx->next_tile; 1579 1580 if (ctx->resize_coeffs_h[cur_tile % ctx->in.num_cols] != 1581 ctx->resize_coeffs_h[next_tile % ctx->in.num_cols] || 1582 ctx->resize_coeffs_v[cur_tile / ctx->in.num_cols] != 1583 ctx->resize_coeffs_v[next_tile / ctx->in.num_cols] || 1584 ctx->in.tile[cur_tile].width != ctx->in.tile[next_tile].width || 1585 ctx->in.tile[cur_tile].height != ctx->in.tile[next_tile].height || 1586 ctx->out.tile[cur_tile].width != ctx->out.tile[next_tile].width || 1587 ctx->out.tile[cur_tile].height != ctx->out.tile[next_tile].height) 1588 return true; 1589 1590 return false; 1591 } 1592 1593 /* hold irqlock when calling */ 1594 static irqreturn_t do_irq(struct ipu_image_convert_run *run) 1595 { 1596 struct ipu_image_convert_ctx *ctx = run->ctx; 1597 struct ipu_image_convert_chan *chan = ctx->chan; 1598 struct ipu_image_tile *src_tile, *dst_tile; 1599 struct ipu_image_convert_image *s_image = &ctx->in; 1600 struct ipu_image_convert_image *d_image = &ctx->out; 1601 struct ipuv3_channel *outch; 1602 unsigned int dst_idx; 1603 1604 lockdep_assert_held(&chan->irqlock); 1605 1606 outch = ipu_rot_mode_is_irt(ctx->rot_mode) ? 1607 chan->rotation_out_chan : chan->out_chan; 1608 1609 /* 1610 * It is difficult to stop the channel DMA before the channels 1611 * enter the paused state. Without double-buffering the channels 1612 * are always in a paused state when the EOF irq occurs, so it 1613 * is safe to stop the channels now. For double-buffering we 1614 * just ignore the abort until the operation completes, when it 1615 * is safe to shut down. 1616 */ 1617 if (ctx->aborting && !ctx->double_buffering) { 1618 convert_stop(run); 1619 run->status = -EIO; 1620 goto done; 1621 } 1622 1623 if (ctx->next_tile == ctx->num_tiles) { 1624 /* 1625 * the conversion is complete 1626 */ 1627 convert_stop(run); 1628 run->status = 0; 1629 goto done; 1630 } 1631 1632 /* 1633 * not done, place the next tile buffers. 1634 */ 1635 if (!ctx->double_buffering) { 1636 if (ic_settings_changed(ctx)) { 1637 convert_stop(run); 1638 convert_start(run, ctx->next_tile); 1639 } else { 1640 src_tile = &s_image->tile[ctx->next_tile]; 1641 dst_idx = ctx->out_tile_map[ctx->next_tile]; 1642 dst_tile = &d_image->tile[dst_idx]; 1643 1644 ipu_cpmem_set_buffer(chan->in_chan, 0, 1645 s_image->base.phys0 + 1646 src_tile->offset); 1647 ipu_cpmem_set_buffer(outch, 0, 1648 d_image->base.phys0 + 1649 dst_tile->offset); 1650 if (s_image->fmt->planar) 1651 ipu_cpmem_set_uv_offset(chan->in_chan, 1652 src_tile->u_off, 1653 src_tile->v_off); 1654 if (d_image->fmt->planar) 1655 ipu_cpmem_set_uv_offset(outch, 1656 dst_tile->u_off, 1657 dst_tile->v_off); 1658 1659 ipu_idmac_select_buffer(chan->in_chan, 0); 1660 ipu_idmac_select_buffer(outch, 0); 1661 } 1662 } else if (ctx->next_tile < ctx->num_tiles - 1) { 1663 1664 src_tile = &s_image->tile[ctx->next_tile + 1]; 1665 dst_idx = ctx->out_tile_map[ctx->next_tile + 1]; 1666 dst_tile = &d_image->tile[dst_idx]; 1667 1668 ipu_cpmem_set_buffer(chan->in_chan, ctx->cur_buf_num, 1669 s_image->base.phys0 + src_tile->offset); 1670 ipu_cpmem_set_buffer(outch, ctx->cur_buf_num, 1671 d_image->base.phys0 + dst_tile->offset); 1672 1673 ipu_idmac_select_buffer(chan->in_chan, ctx->cur_buf_num); 1674 ipu_idmac_select_buffer(outch, ctx->cur_buf_num); 1675 1676 ctx->cur_buf_num ^= 1; 1677 } 1678 1679 ctx->next_tile++; 1680 return IRQ_HANDLED; 1681 done: 1682 list_add_tail(&run->list, &chan->done_q); 1683 chan->current_run = NULL; 1684 run_next(chan); 1685 return IRQ_WAKE_THREAD; 1686 } 1687 1688 static irqreturn_t norotate_irq(int irq, void *data) 1689 { 1690 struct ipu_image_convert_chan *chan = data; 1691 struct ipu_image_convert_ctx *ctx; 1692 struct ipu_image_convert_run *run; 1693 unsigned long flags; 1694 irqreturn_t ret; 1695 1696 spin_lock_irqsave(&chan->irqlock, flags); 1697 1698 /* get current run and its context */ 1699 run = chan->current_run; 1700 if (!run) { 1701 ret = IRQ_NONE; 1702 goto out; 1703 } 1704 1705 ctx = run->ctx; 1706 1707 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1708 /* this is a rotation operation, just ignore */ 1709 spin_unlock_irqrestore(&chan->irqlock, flags); 1710 return IRQ_HANDLED; 1711 } 1712 1713 ret = do_irq(run); 1714 out: 1715 spin_unlock_irqrestore(&chan->irqlock, flags); 1716 return ret; 1717 } 1718 1719 static irqreturn_t rotate_irq(int irq, void *data) 1720 { 1721 struct ipu_image_convert_chan *chan = data; 1722 struct ipu_image_convert_priv *priv = chan->priv; 1723 struct ipu_image_convert_ctx *ctx; 1724 struct ipu_image_convert_run *run; 1725 unsigned long flags; 1726 irqreturn_t ret; 1727 1728 spin_lock_irqsave(&chan->irqlock, flags); 1729 1730 /* get current run and its context */ 1731 run = chan->current_run; 1732 if (!run) { 1733 ret = IRQ_NONE; 1734 goto out; 1735 } 1736 1737 ctx = run->ctx; 1738 1739 if (!ipu_rot_mode_is_irt(ctx->rot_mode)) { 1740 /* this was NOT a rotation operation, shouldn't happen */ 1741 dev_err(priv->ipu->dev, "Unexpected rotation interrupt\n"); 1742 spin_unlock_irqrestore(&chan->irqlock, flags); 1743 return IRQ_HANDLED; 1744 } 1745 1746 ret = do_irq(run); 1747 out: 1748 spin_unlock_irqrestore(&chan->irqlock, flags); 1749 return ret; 1750 } 1751 1752 /* 1753 * try to force the completion of runs for this ctx. Called when 1754 * abort wait times out in ipu_image_convert_abort(). 1755 */ 1756 static void force_abort(struct ipu_image_convert_ctx *ctx) 1757 { 1758 struct ipu_image_convert_chan *chan = ctx->chan; 1759 struct ipu_image_convert_run *run; 1760 unsigned long flags; 1761 1762 spin_lock_irqsave(&chan->irqlock, flags); 1763 1764 run = chan->current_run; 1765 if (run && run->ctx == ctx) { 1766 convert_stop(run); 1767 run->status = -EIO; 1768 list_add_tail(&run->list, &chan->done_q); 1769 chan->current_run = NULL; 1770 run_next(chan); 1771 } 1772 1773 spin_unlock_irqrestore(&chan->irqlock, flags); 1774 1775 empty_done_q(chan); 1776 } 1777 1778 static void release_ipu_resources(struct ipu_image_convert_chan *chan) 1779 { 1780 if (chan->out_eof_irq >= 0) 1781 free_irq(chan->out_eof_irq, chan); 1782 if (chan->rot_out_eof_irq >= 0) 1783 free_irq(chan->rot_out_eof_irq, chan); 1784 1785 if (!IS_ERR_OR_NULL(chan->in_chan)) 1786 ipu_idmac_put(chan->in_chan); 1787 if (!IS_ERR_OR_NULL(chan->out_chan)) 1788 ipu_idmac_put(chan->out_chan); 1789 if (!IS_ERR_OR_NULL(chan->rotation_in_chan)) 1790 ipu_idmac_put(chan->rotation_in_chan); 1791 if (!IS_ERR_OR_NULL(chan->rotation_out_chan)) 1792 ipu_idmac_put(chan->rotation_out_chan); 1793 if (!IS_ERR_OR_NULL(chan->ic)) 1794 ipu_ic_put(chan->ic); 1795 1796 chan->in_chan = chan->out_chan = chan->rotation_in_chan = 1797 chan->rotation_out_chan = NULL; 1798 chan->out_eof_irq = chan->rot_out_eof_irq = -1; 1799 } 1800 1801 static int get_ipu_resources(struct ipu_image_convert_chan *chan) 1802 { 1803 const struct ipu_image_convert_dma_chan *dma = chan->dma_ch; 1804 struct ipu_image_convert_priv *priv = chan->priv; 1805 int ret; 1806 1807 /* get IC */ 1808 chan->ic = ipu_ic_get(priv->ipu, chan->ic_task); 1809 if (IS_ERR(chan->ic)) { 1810 dev_err(priv->ipu->dev, "could not acquire IC\n"); 1811 ret = PTR_ERR(chan->ic); 1812 goto err; 1813 } 1814 1815 /* get IDMAC channels */ 1816 chan->in_chan = ipu_idmac_get(priv->ipu, dma->in); 1817 chan->out_chan = ipu_idmac_get(priv->ipu, dma->out); 1818 if (IS_ERR(chan->in_chan) || IS_ERR(chan->out_chan)) { 1819 dev_err(priv->ipu->dev, "could not acquire idmac channels\n"); 1820 ret = -EBUSY; 1821 goto err; 1822 } 1823 1824 chan->rotation_in_chan = ipu_idmac_get(priv->ipu, dma->rot_in); 1825 chan->rotation_out_chan = ipu_idmac_get(priv->ipu, dma->rot_out); 1826 if (IS_ERR(chan->rotation_in_chan) || IS_ERR(chan->rotation_out_chan)) { 1827 dev_err(priv->ipu->dev, 1828 "could not acquire idmac rotation channels\n"); 1829 ret = -EBUSY; 1830 goto err; 1831 } 1832 1833 /* acquire the EOF interrupts */ 1834 chan->out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1835 chan->out_chan, 1836 IPU_IRQ_EOF); 1837 1838 ret = request_threaded_irq(chan->out_eof_irq, norotate_irq, do_bh, 1839 0, "ipu-ic", chan); 1840 if (ret < 0) { 1841 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1842 chan->out_eof_irq); 1843 chan->out_eof_irq = -1; 1844 goto err; 1845 } 1846 1847 chan->rot_out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1848 chan->rotation_out_chan, 1849 IPU_IRQ_EOF); 1850 1851 ret = request_threaded_irq(chan->rot_out_eof_irq, rotate_irq, do_bh, 1852 0, "ipu-ic", chan); 1853 if (ret < 0) { 1854 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1855 chan->rot_out_eof_irq); 1856 chan->rot_out_eof_irq = -1; 1857 goto err; 1858 } 1859 1860 return 0; 1861 err: 1862 release_ipu_resources(chan); 1863 return ret; 1864 } 1865 1866 static int fill_image(struct ipu_image_convert_ctx *ctx, 1867 struct ipu_image_convert_image *ic_image, 1868 struct ipu_image *image, 1869 enum ipu_image_convert_type type) 1870 { 1871 struct ipu_image_convert_priv *priv = ctx->chan->priv; 1872 1873 ic_image->base = *image; 1874 ic_image->type = type; 1875 1876 ic_image->fmt = get_format(image->pix.pixelformat); 1877 if (!ic_image->fmt) { 1878 dev_err(priv->ipu->dev, "pixelformat not supported for %s\n", 1879 type == IMAGE_CONVERT_OUT ? "Output" : "Input"); 1880 return -EINVAL; 1881 } 1882 1883 if (ic_image->fmt->planar) 1884 ic_image->stride = ic_image->base.pix.width; 1885 else 1886 ic_image->stride = ic_image->base.pix.bytesperline; 1887 1888 return 0; 1889 } 1890 1891 /* borrowed from drivers/media/v4l2-core/v4l2-common.c */ 1892 static unsigned int clamp_align(unsigned int x, unsigned int min, 1893 unsigned int max, unsigned int align) 1894 { 1895 /* Bits that must be zero to be aligned */ 1896 unsigned int mask = ~((1 << align) - 1); 1897 1898 /* Clamp to aligned min and max */ 1899 x = clamp(x, (min + ~mask) & mask, max & mask); 1900 1901 /* Round to nearest aligned value */ 1902 if (align) 1903 x = (x + (1 << (align - 1))) & mask; 1904 1905 return x; 1906 } 1907 1908 /* Adjusts input/output images to IPU restrictions */ 1909 void ipu_image_convert_adjust(struct ipu_image *in, struct ipu_image *out, 1910 enum ipu_rotate_mode rot_mode) 1911 { 1912 const struct ipu_image_pixfmt *infmt, *outfmt; 1913 u32 w_align_out, h_align_out; 1914 u32 w_align_in, h_align_in; 1915 1916 infmt = get_format(in->pix.pixelformat); 1917 outfmt = get_format(out->pix.pixelformat); 1918 1919 /* set some default pixel formats if needed */ 1920 if (!infmt) { 1921 in->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1922 infmt = get_format(V4L2_PIX_FMT_RGB24); 1923 } 1924 if (!outfmt) { 1925 out->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1926 outfmt = get_format(V4L2_PIX_FMT_RGB24); 1927 } 1928 1929 /* image converter does not handle fields */ 1930 in->pix.field = out->pix.field = V4L2_FIELD_NONE; 1931 1932 /* resizer cannot downsize more than 4:1 */ 1933 if (ipu_rot_mode_is_irt(rot_mode)) { 1934 out->pix.height = max_t(__u32, out->pix.height, 1935 in->pix.width / 4); 1936 out->pix.width = max_t(__u32, out->pix.width, 1937 in->pix.height / 4); 1938 } else { 1939 out->pix.width = max_t(__u32, out->pix.width, 1940 in->pix.width / 4); 1941 out->pix.height = max_t(__u32, out->pix.height, 1942 in->pix.height / 4); 1943 } 1944 1945 /* align input width/height */ 1946 w_align_in = ilog2(tile_width_align(IMAGE_CONVERT_IN, infmt, 1947 rot_mode)); 1948 h_align_in = ilog2(tile_height_align(IMAGE_CONVERT_IN, infmt, 1949 rot_mode)); 1950 in->pix.width = clamp_align(in->pix.width, MIN_W, MAX_W, 1951 w_align_in); 1952 in->pix.height = clamp_align(in->pix.height, MIN_H, MAX_H, 1953 h_align_in); 1954 1955 /* align output width/height */ 1956 w_align_out = ilog2(tile_width_align(IMAGE_CONVERT_OUT, outfmt, 1957 rot_mode)); 1958 h_align_out = ilog2(tile_height_align(IMAGE_CONVERT_OUT, outfmt, 1959 rot_mode)); 1960 out->pix.width = clamp_align(out->pix.width, MIN_W, MAX_W, 1961 w_align_out); 1962 out->pix.height = clamp_align(out->pix.height, MIN_H, MAX_H, 1963 h_align_out); 1964 1965 /* set input/output strides and image sizes */ 1966 in->pix.bytesperline = infmt->planar ? 1967 clamp_align(in->pix.width, 2 << w_align_in, MAX_W, 1968 w_align_in) : 1969 clamp_align((in->pix.width * infmt->bpp) >> 3, 1970 ((2 << w_align_in) * infmt->bpp) >> 3, 1971 (MAX_W * infmt->bpp) >> 3, 1972 w_align_in); 1973 in->pix.sizeimage = infmt->planar ? 1974 (in->pix.height * in->pix.bytesperline * infmt->bpp) >> 3 : 1975 in->pix.height * in->pix.bytesperline; 1976 out->pix.bytesperline = outfmt->planar ? out->pix.width : 1977 (out->pix.width * outfmt->bpp) >> 3; 1978 out->pix.sizeimage = outfmt->planar ? 1979 (out->pix.height * out->pix.bytesperline * outfmt->bpp) >> 3 : 1980 out->pix.height * out->pix.bytesperline; 1981 } 1982 EXPORT_SYMBOL_GPL(ipu_image_convert_adjust); 1983 1984 /* 1985 * this is used by ipu_image_convert_prepare() to verify set input and 1986 * output images are valid before starting the conversion. Clients can 1987 * also call it before calling ipu_image_convert_prepare(). 1988 */ 1989 int ipu_image_convert_verify(struct ipu_image *in, struct ipu_image *out, 1990 enum ipu_rotate_mode rot_mode) 1991 { 1992 struct ipu_image testin, testout; 1993 1994 testin = *in; 1995 testout = *out; 1996 1997 ipu_image_convert_adjust(&testin, &testout, rot_mode); 1998 1999 if (testin.pix.width != in->pix.width || 2000 testin.pix.height != in->pix.height || 2001 testout.pix.width != out->pix.width || 2002 testout.pix.height != out->pix.height) 2003 return -EINVAL; 2004 2005 return 0; 2006 } 2007 EXPORT_SYMBOL_GPL(ipu_image_convert_verify); 2008 2009 /* 2010 * Call ipu_image_convert_prepare() to prepare for the conversion of 2011 * given images and rotation mode. Returns a new conversion context. 2012 */ 2013 struct ipu_image_convert_ctx * 2014 ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 2015 struct ipu_image *in, struct ipu_image *out, 2016 enum ipu_rotate_mode rot_mode, 2017 ipu_image_convert_cb_t complete, 2018 void *complete_context) 2019 { 2020 struct ipu_image_convert_priv *priv = ipu->image_convert_priv; 2021 struct ipu_image_convert_image *s_image, *d_image; 2022 struct ipu_image_convert_chan *chan; 2023 struct ipu_image_convert_ctx *ctx; 2024 unsigned long flags; 2025 unsigned int i; 2026 bool get_res; 2027 int ret; 2028 2029 if (!in || !out || !complete || 2030 (ic_task != IC_TASK_VIEWFINDER && 2031 ic_task != IC_TASK_POST_PROCESSOR)) 2032 return ERR_PTR(-EINVAL); 2033 2034 /* verify the in/out images before continuing */ 2035 ret = ipu_image_convert_verify(in, out, rot_mode); 2036 if (ret) { 2037 dev_err(priv->ipu->dev, "%s: in/out formats invalid\n", 2038 __func__); 2039 return ERR_PTR(ret); 2040 } 2041 2042 chan = &priv->chan[ic_task]; 2043 2044 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 2045 if (!ctx) 2046 return ERR_PTR(-ENOMEM); 2047 2048 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p\n", __func__, 2049 chan->ic_task, ctx); 2050 2051 ctx->chan = chan; 2052 init_completion(&ctx->aborted); 2053 2054 ctx->rot_mode = rot_mode; 2055 2056 /* Sets ctx->in.num_rows/cols as well */ 2057 ret = calc_image_resize_coefficients(ctx, in, out); 2058 if (ret) 2059 goto out_free; 2060 2061 s_image = &ctx->in; 2062 d_image = &ctx->out; 2063 2064 /* set tiling and rotation */ 2065 if (ipu_rot_mode_is_irt(rot_mode)) { 2066 d_image->num_rows = s_image->num_cols; 2067 d_image->num_cols = s_image->num_rows; 2068 } else { 2069 d_image->num_rows = s_image->num_rows; 2070 d_image->num_cols = s_image->num_cols; 2071 } 2072 2073 ctx->num_tiles = d_image->num_cols * d_image->num_rows; 2074 2075 ret = fill_image(ctx, s_image, in, IMAGE_CONVERT_IN); 2076 if (ret) 2077 goto out_free; 2078 ret = fill_image(ctx, d_image, out, IMAGE_CONVERT_OUT); 2079 if (ret) 2080 goto out_free; 2081 2082 calc_out_tile_map(ctx); 2083 2084 find_seams(ctx, s_image, d_image); 2085 2086 calc_tile_dimensions(ctx, s_image); 2087 ret = calc_tile_offsets(ctx, s_image); 2088 if (ret) 2089 goto out_free; 2090 2091 calc_tile_dimensions(ctx, d_image); 2092 ret = calc_tile_offsets(ctx, d_image); 2093 if (ret) 2094 goto out_free; 2095 2096 calc_tile_resize_coefficients(ctx); 2097 2098 ret = ipu_ic_calc_csc(&ctx->csc, 2099 s_image->base.pix.ycbcr_enc, 2100 s_image->base.pix.quantization, 2101 ipu_pixelformat_to_colorspace(s_image->fmt->fourcc), 2102 d_image->base.pix.ycbcr_enc, 2103 d_image->base.pix.quantization, 2104 ipu_pixelformat_to_colorspace(d_image->fmt->fourcc)); 2105 if (ret) 2106 goto out_free; 2107 2108 dump_format(ctx, s_image); 2109 dump_format(ctx, d_image); 2110 2111 ctx->complete = complete; 2112 ctx->complete_context = complete_context; 2113 2114 /* 2115 * Can we use double-buffering for this operation? If there is 2116 * only one tile (the whole image can be converted in a single 2117 * operation) there's no point in using double-buffering. Also, 2118 * the IPU's IDMAC channels allow only a single U and V plane 2119 * offset shared between both buffers, but these offsets change 2120 * for every tile, and therefore would have to be updated for 2121 * each buffer which is not possible. So double-buffering is 2122 * impossible when either the source or destination images are 2123 * a planar format (YUV420, YUV422P, etc.). Further, differently 2124 * sized tiles or different resizing coefficients per tile 2125 * prevent double-buffering as well. 2126 */ 2127 ctx->double_buffering = (ctx->num_tiles > 1 && 2128 !s_image->fmt->planar && 2129 !d_image->fmt->planar); 2130 for (i = 1; i < ctx->num_tiles; i++) { 2131 if (ctx->in.tile[i].width != ctx->in.tile[0].width || 2132 ctx->in.tile[i].height != ctx->in.tile[0].height || 2133 ctx->out.tile[i].width != ctx->out.tile[0].width || 2134 ctx->out.tile[i].height != ctx->out.tile[0].height) { 2135 ctx->double_buffering = false; 2136 break; 2137 } 2138 } 2139 for (i = 1; i < ctx->in.num_cols; i++) { 2140 if (ctx->resize_coeffs_h[i] != ctx->resize_coeffs_h[0]) { 2141 ctx->double_buffering = false; 2142 break; 2143 } 2144 } 2145 for (i = 1; i < ctx->in.num_rows; i++) { 2146 if (ctx->resize_coeffs_v[i] != ctx->resize_coeffs_v[0]) { 2147 ctx->double_buffering = false; 2148 break; 2149 } 2150 } 2151 2152 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 2153 unsigned long intermediate_size = d_image->tile[0].size; 2154 2155 for (i = 1; i < ctx->num_tiles; i++) { 2156 if (d_image->tile[i].size > intermediate_size) 2157 intermediate_size = d_image->tile[i].size; 2158 } 2159 2160 ret = alloc_dma_buf(priv, &ctx->rot_intermediate[0], 2161 intermediate_size); 2162 if (ret) 2163 goto out_free; 2164 if (ctx->double_buffering) { 2165 ret = alloc_dma_buf(priv, 2166 &ctx->rot_intermediate[1], 2167 intermediate_size); 2168 if (ret) 2169 goto out_free_dmabuf0; 2170 } 2171 } 2172 2173 spin_lock_irqsave(&chan->irqlock, flags); 2174 2175 get_res = list_empty(&chan->ctx_list); 2176 2177 list_add_tail(&ctx->list, &chan->ctx_list); 2178 2179 spin_unlock_irqrestore(&chan->irqlock, flags); 2180 2181 if (get_res) { 2182 ret = get_ipu_resources(chan); 2183 if (ret) 2184 goto out_free_dmabuf1; 2185 } 2186 2187 return ctx; 2188 2189 out_free_dmabuf1: 2190 free_dma_buf(priv, &ctx->rot_intermediate[1]); 2191 spin_lock_irqsave(&chan->irqlock, flags); 2192 list_del(&ctx->list); 2193 spin_unlock_irqrestore(&chan->irqlock, flags); 2194 out_free_dmabuf0: 2195 free_dma_buf(priv, &ctx->rot_intermediate[0]); 2196 out_free: 2197 kfree(ctx); 2198 return ERR_PTR(ret); 2199 } 2200 EXPORT_SYMBOL_GPL(ipu_image_convert_prepare); 2201 2202 /* 2203 * Carry out a single image conversion run. Only the physaddr's of the input 2204 * and output image buffers are needed. The conversion context must have 2205 * been created previously with ipu_image_convert_prepare(). 2206 */ 2207 int ipu_image_convert_queue(struct ipu_image_convert_run *run) 2208 { 2209 struct ipu_image_convert_chan *chan; 2210 struct ipu_image_convert_priv *priv; 2211 struct ipu_image_convert_ctx *ctx; 2212 unsigned long flags; 2213 int ret = 0; 2214 2215 if (!run || !run->ctx || !run->in_phys || !run->out_phys) 2216 return -EINVAL; 2217 2218 ctx = run->ctx; 2219 chan = ctx->chan; 2220 priv = chan->priv; 2221 2222 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p run %p\n", __func__, 2223 chan->ic_task, ctx, run); 2224 2225 INIT_LIST_HEAD(&run->list); 2226 2227 spin_lock_irqsave(&chan->irqlock, flags); 2228 2229 if (ctx->aborting) { 2230 ret = -EIO; 2231 goto unlock; 2232 } 2233 2234 list_add_tail(&run->list, &chan->pending_q); 2235 2236 if (!chan->current_run) { 2237 ret = do_run(run); 2238 if (ret) 2239 chan->current_run = NULL; 2240 } 2241 unlock: 2242 spin_unlock_irqrestore(&chan->irqlock, flags); 2243 return ret; 2244 } 2245 EXPORT_SYMBOL_GPL(ipu_image_convert_queue); 2246 2247 /* Abort any active or pending conversions for this context */ 2248 static void __ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 2249 { 2250 struct ipu_image_convert_chan *chan = ctx->chan; 2251 struct ipu_image_convert_priv *priv = chan->priv; 2252 struct ipu_image_convert_run *run, *active_run, *tmp; 2253 unsigned long flags; 2254 int run_count, ret; 2255 2256 spin_lock_irqsave(&chan->irqlock, flags); 2257 2258 /* move all remaining pending runs in this context to done_q */ 2259 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 2260 if (run->ctx != ctx) 2261 continue; 2262 run->status = -EIO; 2263 list_move_tail(&run->list, &chan->done_q); 2264 } 2265 2266 run_count = get_run_count(ctx, &chan->done_q); 2267 active_run = (chan->current_run && chan->current_run->ctx == ctx) ? 2268 chan->current_run : NULL; 2269 2270 if (active_run) 2271 reinit_completion(&ctx->aborted); 2272 2273 ctx->aborting = true; 2274 2275 spin_unlock_irqrestore(&chan->irqlock, flags); 2276 2277 if (!run_count && !active_run) { 2278 dev_dbg(priv->ipu->dev, 2279 "%s: task %u: no abort needed for ctx %p\n", 2280 __func__, chan->ic_task, ctx); 2281 return; 2282 } 2283 2284 if (!active_run) { 2285 empty_done_q(chan); 2286 return; 2287 } 2288 2289 dev_dbg(priv->ipu->dev, 2290 "%s: task %u: wait for completion: %d runs\n", 2291 __func__, chan->ic_task, run_count); 2292 2293 ret = wait_for_completion_timeout(&ctx->aborted, 2294 msecs_to_jiffies(10000)); 2295 if (ret == 0) { 2296 dev_warn(priv->ipu->dev, "%s: timeout\n", __func__); 2297 force_abort(ctx); 2298 } 2299 } 2300 2301 void ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 2302 { 2303 __ipu_image_convert_abort(ctx); 2304 ctx->aborting = false; 2305 } 2306 EXPORT_SYMBOL_GPL(ipu_image_convert_abort); 2307 2308 /* Unprepare image conversion context */ 2309 void ipu_image_convert_unprepare(struct ipu_image_convert_ctx *ctx) 2310 { 2311 struct ipu_image_convert_chan *chan = ctx->chan; 2312 struct ipu_image_convert_priv *priv = chan->priv; 2313 unsigned long flags; 2314 bool put_res; 2315 2316 /* make sure no runs are hanging around */ 2317 __ipu_image_convert_abort(ctx); 2318 2319 dev_dbg(priv->ipu->dev, "%s: task %u: removing ctx %p\n", __func__, 2320 chan->ic_task, ctx); 2321 2322 spin_lock_irqsave(&chan->irqlock, flags); 2323 2324 list_del(&ctx->list); 2325 2326 put_res = list_empty(&chan->ctx_list); 2327 2328 spin_unlock_irqrestore(&chan->irqlock, flags); 2329 2330 if (put_res) 2331 release_ipu_resources(chan); 2332 2333 free_dma_buf(priv, &ctx->rot_intermediate[1]); 2334 free_dma_buf(priv, &ctx->rot_intermediate[0]); 2335 2336 kfree(ctx); 2337 } 2338 EXPORT_SYMBOL_GPL(ipu_image_convert_unprepare); 2339 2340 /* 2341 * "Canned" asynchronous single image conversion. Allocates and returns 2342 * a new conversion run. On successful return the caller must free the 2343 * run and call ipu_image_convert_unprepare() after conversion completes. 2344 */ 2345 struct ipu_image_convert_run * 2346 ipu_image_convert(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 2347 struct ipu_image *in, struct ipu_image *out, 2348 enum ipu_rotate_mode rot_mode, 2349 ipu_image_convert_cb_t complete, 2350 void *complete_context) 2351 { 2352 struct ipu_image_convert_ctx *ctx; 2353 struct ipu_image_convert_run *run; 2354 int ret; 2355 2356 ctx = ipu_image_convert_prepare(ipu, ic_task, in, out, rot_mode, 2357 complete, complete_context); 2358 if (IS_ERR(ctx)) 2359 return ERR_CAST(ctx); 2360 2361 run = kzalloc(sizeof(*run), GFP_KERNEL); 2362 if (!run) { 2363 ipu_image_convert_unprepare(ctx); 2364 return ERR_PTR(-ENOMEM); 2365 } 2366 2367 run->ctx = ctx; 2368 run->in_phys = in->phys0; 2369 run->out_phys = out->phys0; 2370 2371 ret = ipu_image_convert_queue(run); 2372 if (ret) { 2373 ipu_image_convert_unprepare(ctx); 2374 kfree(run); 2375 return ERR_PTR(ret); 2376 } 2377 2378 return run; 2379 } 2380 EXPORT_SYMBOL_GPL(ipu_image_convert); 2381 2382 /* "Canned" synchronous single image conversion */ 2383 static void image_convert_sync_complete(struct ipu_image_convert_run *run, 2384 void *data) 2385 { 2386 struct completion *comp = data; 2387 2388 complete(comp); 2389 } 2390 2391 int ipu_image_convert_sync(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 2392 struct ipu_image *in, struct ipu_image *out, 2393 enum ipu_rotate_mode rot_mode) 2394 { 2395 struct ipu_image_convert_run *run; 2396 struct completion comp; 2397 int ret; 2398 2399 init_completion(&comp); 2400 2401 run = ipu_image_convert(ipu, ic_task, in, out, rot_mode, 2402 image_convert_sync_complete, &comp); 2403 if (IS_ERR(run)) 2404 return PTR_ERR(run); 2405 2406 ret = wait_for_completion_timeout(&comp, msecs_to_jiffies(10000)); 2407 ret = (ret == 0) ? -ETIMEDOUT : 0; 2408 2409 ipu_image_convert_unprepare(run->ctx); 2410 kfree(run); 2411 2412 return ret; 2413 } 2414 EXPORT_SYMBOL_GPL(ipu_image_convert_sync); 2415 2416 int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev) 2417 { 2418 struct ipu_image_convert_priv *priv; 2419 int i; 2420 2421 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 2422 if (!priv) 2423 return -ENOMEM; 2424 2425 ipu->image_convert_priv = priv; 2426 priv->ipu = ipu; 2427 2428 for (i = 0; i < IC_NUM_TASKS; i++) { 2429 struct ipu_image_convert_chan *chan = &priv->chan[i]; 2430 2431 chan->ic_task = i; 2432 chan->priv = priv; 2433 chan->dma_ch = &image_convert_dma_chan[i]; 2434 chan->out_eof_irq = -1; 2435 chan->rot_out_eof_irq = -1; 2436 2437 spin_lock_init(&chan->irqlock); 2438 INIT_LIST_HEAD(&chan->ctx_list); 2439 INIT_LIST_HEAD(&chan->pending_q); 2440 INIT_LIST_HEAD(&chan->done_q); 2441 } 2442 2443 return 0; 2444 } 2445 2446 void ipu_image_convert_exit(struct ipu_soc *ipu) 2447 { 2448 } 2449