1 /* 2 * Copyright (C) 2012-2016 Mentor Graphics Inc. 3 * 4 * Queued image conversion support, with tiling and rotation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include <linux/interrupt.h> 18 #include <linux/dma-mapping.h> 19 #include <video/imx-ipu-image-convert.h> 20 #include "ipu-prv.h" 21 22 /* 23 * The IC Resizer has a restriction that the output frame from the 24 * resizer must be 1024 or less in both width (pixels) and height 25 * (lines). 26 * 27 * The image converter attempts to split up a conversion when 28 * the desired output (converted) frame resolution exceeds the 29 * IC resizer limit of 1024 in either dimension. 30 * 31 * If either dimension of the output frame exceeds the limit, the 32 * dimension is split into 1, 2, or 4 equal stripes, for a maximum 33 * of 4*4 or 16 tiles. A conversion is then carried out for each 34 * tile (but taking care to pass the full frame stride length to 35 * the DMA channel's parameter memory!). IDMA double-buffering is used 36 * to convert each tile back-to-back when possible (see note below 37 * when double_buffering boolean is set). 38 * 39 * Note that the input frame must be split up into the same number 40 * of tiles as the output frame. 41 * 42 * FIXME: at this point there is no attempt to deal with visible seams 43 * at the tile boundaries when upscaling. The seams are caused by a reset 44 * of the bilinear upscale interpolation when starting a new tile. The 45 * seams are barely visible for small upscale factors, but become 46 * increasingly visible as the upscale factor gets larger, since more 47 * interpolated pixels get thrown out at the tile boundaries. A possilble 48 * fix might be to overlap tiles of different sizes, but this must be done 49 * while also maintaining the IDMAC dma buffer address alignment and 8x8 IRT 50 * alignment restrictions of each tile. 51 */ 52 53 #define MAX_STRIPES_W 4 54 #define MAX_STRIPES_H 4 55 #define MAX_TILES (MAX_STRIPES_W * MAX_STRIPES_H) 56 57 #define MIN_W 16 58 #define MIN_H 8 59 #define MAX_W 4096 60 #define MAX_H 4096 61 62 enum ipu_image_convert_type { 63 IMAGE_CONVERT_IN = 0, 64 IMAGE_CONVERT_OUT, 65 }; 66 67 struct ipu_image_convert_dma_buf { 68 void *virt; 69 dma_addr_t phys; 70 unsigned long len; 71 }; 72 73 struct ipu_image_convert_dma_chan { 74 int in; 75 int out; 76 int rot_in; 77 int rot_out; 78 int vdi_in_p; 79 int vdi_in; 80 int vdi_in_n; 81 }; 82 83 /* dimensions of one tile */ 84 struct ipu_image_tile { 85 u32 width; 86 u32 height; 87 /* size and strides are in bytes */ 88 u32 size; 89 u32 stride; 90 u32 rot_stride; 91 /* start Y or packed offset of this tile */ 92 u32 offset; 93 /* offset from start to tile in U plane, for planar formats */ 94 u32 u_off; 95 /* offset from start to tile in V plane, for planar formats */ 96 u32 v_off; 97 }; 98 99 struct ipu_image_convert_image { 100 struct ipu_image base; 101 enum ipu_image_convert_type type; 102 103 const struct ipu_image_pixfmt *fmt; 104 unsigned int stride; 105 106 /* # of rows (horizontal stripes) if dest height is > 1024 */ 107 unsigned int num_rows; 108 /* # of columns (vertical stripes) if dest width is > 1024 */ 109 unsigned int num_cols; 110 111 struct ipu_image_tile tile[MAX_TILES]; 112 }; 113 114 struct ipu_image_pixfmt { 115 u32 fourcc; /* V4L2 fourcc */ 116 int bpp; /* total bpp */ 117 int uv_width_dec; /* decimation in width for U/V planes */ 118 int uv_height_dec; /* decimation in height for U/V planes */ 119 bool planar; /* planar format */ 120 bool uv_swapped; /* U and V planes are swapped */ 121 bool uv_packed; /* partial planar (U and V in same plane) */ 122 }; 123 124 struct ipu_image_convert_ctx; 125 struct ipu_image_convert_chan; 126 struct ipu_image_convert_priv; 127 128 struct ipu_image_convert_ctx { 129 struct ipu_image_convert_chan *chan; 130 131 ipu_image_convert_cb_t complete; 132 void *complete_context; 133 134 /* Source/destination image data and rotation mode */ 135 struct ipu_image_convert_image in; 136 struct ipu_image_convert_image out; 137 enum ipu_rotate_mode rot_mode; 138 139 /* intermediate buffer for rotation */ 140 struct ipu_image_convert_dma_buf rot_intermediate[2]; 141 142 /* current buffer number for double buffering */ 143 int cur_buf_num; 144 145 bool aborting; 146 struct completion aborted; 147 148 /* can we use double-buffering for this conversion operation? */ 149 bool double_buffering; 150 /* num_rows * num_cols */ 151 unsigned int num_tiles; 152 /* next tile to process */ 153 unsigned int next_tile; 154 /* where to place converted tile in dest image */ 155 unsigned int out_tile_map[MAX_TILES]; 156 157 struct list_head list; 158 }; 159 160 struct ipu_image_convert_chan { 161 struct ipu_image_convert_priv *priv; 162 163 enum ipu_ic_task ic_task; 164 const struct ipu_image_convert_dma_chan *dma_ch; 165 166 struct ipu_ic *ic; 167 struct ipuv3_channel *in_chan; 168 struct ipuv3_channel *out_chan; 169 struct ipuv3_channel *rotation_in_chan; 170 struct ipuv3_channel *rotation_out_chan; 171 172 /* the IPU end-of-frame irqs */ 173 int out_eof_irq; 174 int rot_out_eof_irq; 175 176 spinlock_t irqlock; 177 178 /* list of convert contexts */ 179 struct list_head ctx_list; 180 /* queue of conversion runs */ 181 struct list_head pending_q; 182 /* queue of completed runs */ 183 struct list_head done_q; 184 185 /* the current conversion run */ 186 struct ipu_image_convert_run *current_run; 187 }; 188 189 struct ipu_image_convert_priv { 190 struct ipu_image_convert_chan chan[IC_NUM_TASKS]; 191 struct ipu_soc *ipu; 192 }; 193 194 static const struct ipu_image_convert_dma_chan 195 image_convert_dma_chan[IC_NUM_TASKS] = { 196 [IC_TASK_VIEWFINDER] = { 197 .in = IPUV3_CHANNEL_MEM_IC_PRP_VF, 198 .out = IPUV3_CHANNEL_IC_PRP_VF_MEM, 199 .rot_in = IPUV3_CHANNEL_MEM_ROT_VF, 200 .rot_out = IPUV3_CHANNEL_ROT_VF_MEM, 201 .vdi_in_p = IPUV3_CHANNEL_MEM_VDI_PREV, 202 .vdi_in = IPUV3_CHANNEL_MEM_VDI_CUR, 203 .vdi_in_n = IPUV3_CHANNEL_MEM_VDI_NEXT, 204 }, 205 [IC_TASK_POST_PROCESSOR] = { 206 .in = IPUV3_CHANNEL_MEM_IC_PP, 207 .out = IPUV3_CHANNEL_IC_PP_MEM, 208 .rot_in = IPUV3_CHANNEL_MEM_ROT_PP, 209 .rot_out = IPUV3_CHANNEL_ROT_PP_MEM, 210 }, 211 }; 212 213 static const struct ipu_image_pixfmt image_convert_formats[] = { 214 { 215 .fourcc = V4L2_PIX_FMT_RGB565, 216 .bpp = 16, 217 }, { 218 .fourcc = V4L2_PIX_FMT_RGB24, 219 .bpp = 24, 220 }, { 221 .fourcc = V4L2_PIX_FMT_BGR24, 222 .bpp = 24, 223 }, { 224 .fourcc = V4L2_PIX_FMT_RGB32, 225 .bpp = 32, 226 }, { 227 .fourcc = V4L2_PIX_FMT_BGR32, 228 .bpp = 32, 229 }, { 230 .fourcc = V4L2_PIX_FMT_XRGB32, 231 .bpp = 32, 232 }, { 233 .fourcc = V4L2_PIX_FMT_XBGR32, 234 .bpp = 32, 235 }, { 236 .fourcc = V4L2_PIX_FMT_YUYV, 237 .bpp = 16, 238 .uv_width_dec = 2, 239 .uv_height_dec = 1, 240 }, { 241 .fourcc = V4L2_PIX_FMT_UYVY, 242 .bpp = 16, 243 .uv_width_dec = 2, 244 .uv_height_dec = 1, 245 }, { 246 .fourcc = V4L2_PIX_FMT_YUV420, 247 .bpp = 12, 248 .planar = true, 249 .uv_width_dec = 2, 250 .uv_height_dec = 2, 251 }, { 252 .fourcc = V4L2_PIX_FMT_YVU420, 253 .bpp = 12, 254 .planar = true, 255 .uv_width_dec = 2, 256 .uv_height_dec = 2, 257 .uv_swapped = true, 258 }, { 259 .fourcc = V4L2_PIX_FMT_NV12, 260 .bpp = 12, 261 .planar = true, 262 .uv_width_dec = 2, 263 .uv_height_dec = 2, 264 .uv_packed = true, 265 }, { 266 .fourcc = V4L2_PIX_FMT_YUV422P, 267 .bpp = 16, 268 .planar = true, 269 .uv_width_dec = 2, 270 .uv_height_dec = 1, 271 }, { 272 .fourcc = V4L2_PIX_FMT_NV16, 273 .bpp = 16, 274 .planar = true, 275 .uv_width_dec = 2, 276 .uv_height_dec = 1, 277 .uv_packed = true, 278 }, 279 }; 280 281 static const struct ipu_image_pixfmt *get_format(u32 fourcc) 282 { 283 const struct ipu_image_pixfmt *ret = NULL; 284 unsigned int i; 285 286 for (i = 0; i < ARRAY_SIZE(image_convert_formats); i++) { 287 if (image_convert_formats[i].fourcc == fourcc) { 288 ret = &image_convert_formats[i]; 289 break; 290 } 291 } 292 293 return ret; 294 } 295 296 static void dump_format(struct ipu_image_convert_ctx *ctx, 297 struct ipu_image_convert_image *ic_image) 298 { 299 struct ipu_image_convert_chan *chan = ctx->chan; 300 struct ipu_image_convert_priv *priv = chan->priv; 301 302 dev_dbg(priv->ipu->dev, 303 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles of size %dx%d), %c%c%c%c\n", 304 chan->ic_task, ctx, 305 ic_image->type == IMAGE_CONVERT_OUT ? "Output" : "Input", 306 ic_image->base.pix.width, ic_image->base.pix.height, 307 ic_image->num_cols, ic_image->num_rows, 308 ic_image->tile[0].width, ic_image->tile[0].height, 309 ic_image->fmt->fourcc & 0xff, 310 (ic_image->fmt->fourcc >> 8) & 0xff, 311 (ic_image->fmt->fourcc >> 16) & 0xff, 312 (ic_image->fmt->fourcc >> 24) & 0xff); 313 } 314 315 int ipu_image_convert_enum_format(int index, u32 *fourcc) 316 { 317 const struct ipu_image_pixfmt *fmt; 318 319 if (index >= (int)ARRAY_SIZE(image_convert_formats)) 320 return -EINVAL; 321 322 /* Format found */ 323 fmt = &image_convert_formats[index]; 324 *fourcc = fmt->fourcc; 325 return 0; 326 } 327 EXPORT_SYMBOL_GPL(ipu_image_convert_enum_format); 328 329 static void free_dma_buf(struct ipu_image_convert_priv *priv, 330 struct ipu_image_convert_dma_buf *buf) 331 { 332 if (buf->virt) 333 dma_free_coherent(priv->ipu->dev, 334 buf->len, buf->virt, buf->phys); 335 buf->virt = NULL; 336 buf->phys = 0; 337 } 338 339 static int alloc_dma_buf(struct ipu_image_convert_priv *priv, 340 struct ipu_image_convert_dma_buf *buf, 341 int size) 342 { 343 buf->len = PAGE_ALIGN(size); 344 buf->virt = dma_alloc_coherent(priv->ipu->dev, buf->len, &buf->phys, 345 GFP_DMA | GFP_KERNEL); 346 if (!buf->virt) { 347 dev_err(priv->ipu->dev, "failed to alloc dma buffer\n"); 348 return -ENOMEM; 349 } 350 351 return 0; 352 } 353 354 static inline int num_stripes(int dim) 355 { 356 if (dim <= 1024) 357 return 1; 358 else if (dim <= 2048) 359 return 2; 360 else 361 return 4; 362 } 363 364 static void calc_tile_dimensions(struct ipu_image_convert_ctx *ctx, 365 struct ipu_image_convert_image *image) 366 { 367 int i; 368 369 for (i = 0; i < ctx->num_tiles; i++) { 370 struct ipu_image_tile *tile = &image->tile[i]; 371 372 tile->height = image->base.pix.height / image->num_rows; 373 tile->width = image->base.pix.width / image->num_cols; 374 tile->size = ((tile->height * image->fmt->bpp) >> 3) * 375 tile->width; 376 377 if (image->fmt->planar) { 378 tile->stride = tile->width; 379 tile->rot_stride = tile->height; 380 } else { 381 tile->stride = 382 (image->fmt->bpp * tile->width) >> 3; 383 tile->rot_stride = 384 (image->fmt->bpp * tile->height) >> 3; 385 } 386 } 387 } 388 389 /* 390 * Use the rotation transformation to find the tile coordinates 391 * (row, col) of a tile in the destination frame that corresponds 392 * to the given tile coordinates of a source frame. The destination 393 * coordinate is then converted to a tile index. 394 */ 395 static int transform_tile_index(struct ipu_image_convert_ctx *ctx, 396 int src_row, int src_col) 397 { 398 struct ipu_image_convert_chan *chan = ctx->chan; 399 struct ipu_image_convert_priv *priv = chan->priv; 400 struct ipu_image_convert_image *s_image = &ctx->in; 401 struct ipu_image_convert_image *d_image = &ctx->out; 402 int dst_row, dst_col; 403 404 /* with no rotation it's a 1:1 mapping */ 405 if (ctx->rot_mode == IPU_ROTATE_NONE) 406 return src_row * s_image->num_cols + src_col; 407 408 /* 409 * before doing the transform, first we have to translate 410 * source row,col for an origin in the center of s_image 411 */ 412 src_row = src_row * 2 - (s_image->num_rows - 1); 413 src_col = src_col * 2 - (s_image->num_cols - 1); 414 415 /* do the rotation transform */ 416 if (ctx->rot_mode & IPU_ROT_BIT_90) { 417 dst_col = -src_row; 418 dst_row = src_col; 419 } else { 420 dst_col = src_col; 421 dst_row = src_row; 422 } 423 424 /* apply flip */ 425 if (ctx->rot_mode & IPU_ROT_BIT_HFLIP) 426 dst_col = -dst_col; 427 if (ctx->rot_mode & IPU_ROT_BIT_VFLIP) 428 dst_row = -dst_row; 429 430 dev_dbg(priv->ipu->dev, "task %u: ctx %p: [%d,%d] --> [%d,%d]\n", 431 chan->ic_task, ctx, src_col, src_row, dst_col, dst_row); 432 433 /* 434 * finally translate dest row,col using an origin in upper 435 * left of d_image 436 */ 437 dst_row += d_image->num_rows - 1; 438 dst_col += d_image->num_cols - 1; 439 dst_row /= 2; 440 dst_col /= 2; 441 442 return dst_row * d_image->num_cols + dst_col; 443 } 444 445 /* 446 * Fill the out_tile_map[] with transformed destination tile indeces. 447 */ 448 static void calc_out_tile_map(struct ipu_image_convert_ctx *ctx) 449 { 450 struct ipu_image_convert_image *s_image = &ctx->in; 451 unsigned int row, col, tile = 0; 452 453 for (row = 0; row < s_image->num_rows; row++) { 454 for (col = 0; col < s_image->num_cols; col++) { 455 ctx->out_tile_map[tile] = 456 transform_tile_index(ctx, row, col); 457 tile++; 458 } 459 } 460 } 461 462 static int calc_tile_offsets_planar(struct ipu_image_convert_ctx *ctx, 463 struct ipu_image_convert_image *image) 464 { 465 struct ipu_image_convert_chan *chan = ctx->chan; 466 struct ipu_image_convert_priv *priv = chan->priv; 467 const struct ipu_image_pixfmt *fmt = image->fmt; 468 unsigned int row, col, tile = 0; 469 u32 H, w, h, y_stride, uv_stride; 470 u32 uv_row_off, uv_col_off, uv_off, u_off, v_off, tmp; 471 u32 y_row_off, y_col_off, y_off; 472 u32 y_size, uv_size; 473 474 /* setup some convenience vars */ 475 H = image->base.pix.height; 476 477 y_stride = image->stride; 478 uv_stride = y_stride / fmt->uv_width_dec; 479 if (fmt->uv_packed) 480 uv_stride *= 2; 481 482 y_size = H * y_stride; 483 uv_size = y_size / (fmt->uv_width_dec * fmt->uv_height_dec); 484 485 for (row = 0; row < image->num_rows; row++) { 486 w = image->tile[tile].width; 487 h = image->tile[tile].height; 488 y_row_off = row * h * y_stride; 489 uv_row_off = (row * h * uv_stride) / fmt->uv_height_dec; 490 491 for (col = 0; col < image->num_cols; col++) { 492 y_col_off = col * w; 493 uv_col_off = y_col_off / fmt->uv_width_dec; 494 if (fmt->uv_packed) 495 uv_col_off *= 2; 496 497 y_off = y_row_off + y_col_off; 498 uv_off = uv_row_off + uv_col_off; 499 500 u_off = y_size - y_off + uv_off; 501 v_off = (fmt->uv_packed) ? 0 : u_off + uv_size; 502 if (fmt->uv_swapped) { 503 tmp = u_off; 504 u_off = v_off; 505 v_off = tmp; 506 } 507 508 image->tile[tile].offset = y_off; 509 image->tile[tile].u_off = u_off; 510 image->tile[tile++].v_off = v_off; 511 512 if ((y_off & 0x7) || (u_off & 0x7) || (v_off & 0x7)) { 513 dev_err(priv->ipu->dev, 514 "task %u: ctx %p: %s@[%d,%d]: " 515 "y_off %08x, u_off %08x, v_off %08x\n", 516 chan->ic_task, ctx, 517 image->type == IMAGE_CONVERT_IN ? 518 "Input" : "Output", row, col, 519 y_off, u_off, v_off); 520 return -EINVAL; 521 } 522 } 523 } 524 525 return 0; 526 } 527 528 static int calc_tile_offsets_packed(struct ipu_image_convert_ctx *ctx, 529 struct ipu_image_convert_image *image) 530 { 531 struct ipu_image_convert_chan *chan = ctx->chan; 532 struct ipu_image_convert_priv *priv = chan->priv; 533 const struct ipu_image_pixfmt *fmt = image->fmt; 534 unsigned int row, col, tile = 0; 535 u32 w, h, bpp, stride, offset; 536 u32 row_off, col_off; 537 538 /* setup some convenience vars */ 539 stride = image->stride; 540 bpp = fmt->bpp; 541 542 for (row = 0; row < image->num_rows; row++) { 543 w = image->tile[tile].width; 544 h = image->tile[tile].height; 545 row_off = row * h * stride; 546 547 for (col = 0; col < image->num_cols; col++) { 548 col_off = (col * w * bpp) >> 3; 549 550 offset = row_off + col_off; 551 552 image->tile[tile].offset = offset; 553 image->tile[tile].u_off = 0; 554 image->tile[tile++].v_off = 0; 555 556 if (offset & 0x7) { 557 dev_err(priv->ipu->dev, 558 "task %u: ctx %p: %s@[%d,%d]: " 559 "phys %08x\n", 560 chan->ic_task, ctx, 561 image->type == IMAGE_CONVERT_IN ? 562 "Input" : "Output", row, col, 563 row_off + col_off); 564 return -EINVAL; 565 } 566 } 567 } 568 569 return 0; 570 } 571 572 static int calc_tile_offsets(struct ipu_image_convert_ctx *ctx, 573 struct ipu_image_convert_image *image) 574 { 575 if (image->fmt->planar) 576 return calc_tile_offsets_planar(ctx, image); 577 578 return calc_tile_offsets_packed(ctx, image); 579 } 580 581 /* 582 * return the number of runs in given queue (pending_q or done_q) 583 * for this context. hold irqlock when calling. 584 */ 585 static int get_run_count(struct ipu_image_convert_ctx *ctx, 586 struct list_head *q) 587 { 588 struct ipu_image_convert_run *run; 589 int count = 0; 590 591 lockdep_assert_held(&ctx->chan->irqlock); 592 593 list_for_each_entry(run, q, list) { 594 if (run->ctx == ctx) 595 count++; 596 } 597 598 return count; 599 } 600 601 static void convert_stop(struct ipu_image_convert_run *run) 602 { 603 struct ipu_image_convert_ctx *ctx = run->ctx; 604 struct ipu_image_convert_chan *chan = ctx->chan; 605 struct ipu_image_convert_priv *priv = chan->priv; 606 607 dev_dbg(priv->ipu->dev, "%s: task %u: stopping ctx %p run %p\n", 608 __func__, chan->ic_task, ctx, run); 609 610 /* disable IC tasks and the channels */ 611 ipu_ic_task_disable(chan->ic); 612 ipu_idmac_disable_channel(chan->in_chan); 613 ipu_idmac_disable_channel(chan->out_chan); 614 615 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 616 ipu_idmac_disable_channel(chan->rotation_in_chan); 617 ipu_idmac_disable_channel(chan->rotation_out_chan); 618 ipu_idmac_unlink(chan->out_chan, chan->rotation_in_chan); 619 } 620 621 ipu_ic_disable(chan->ic); 622 } 623 624 static void init_idmac_channel(struct ipu_image_convert_ctx *ctx, 625 struct ipuv3_channel *channel, 626 struct ipu_image_convert_image *image, 627 enum ipu_rotate_mode rot_mode, 628 bool rot_swap_width_height, 629 unsigned int tile) 630 { 631 struct ipu_image_convert_chan *chan = ctx->chan; 632 unsigned int burst_size; 633 u32 width, height, stride; 634 dma_addr_t addr0, addr1 = 0; 635 struct ipu_image tile_image; 636 unsigned int tile_idx[2]; 637 638 if (image->type == IMAGE_CONVERT_OUT) { 639 tile_idx[0] = ctx->out_tile_map[tile]; 640 tile_idx[1] = ctx->out_tile_map[1]; 641 } else { 642 tile_idx[0] = tile; 643 tile_idx[1] = 1; 644 } 645 646 if (rot_swap_width_height) { 647 width = image->tile[tile_idx[0]].height; 648 height = image->tile[tile_idx[0]].width; 649 stride = image->tile[tile_idx[0]].rot_stride; 650 addr0 = ctx->rot_intermediate[0].phys; 651 if (ctx->double_buffering) 652 addr1 = ctx->rot_intermediate[1].phys; 653 } else { 654 width = image->tile[tile_idx[0]].width; 655 height = image->tile[tile_idx[0]].height; 656 stride = image->stride; 657 addr0 = image->base.phys0 + 658 image->tile[tile_idx[0]].offset; 659 if (ctx->double_buffering) 660 addr1 = image->base.phys0 + 661 image->tile[tile_idx[1]].offset; 662 } 663 664 ipu_cpmem_zero(channel); 665 666 memset(&tile_image, 0, sizeof(tile_image)); 667 tile_image.pix.width = tile_image.rect.width = width; 668 tile_image.pix.height = tile_image.rect.height = height; 669 tile_image.pix.bytesperline = stride; 670 tile_image.pix.pixelformat = image->fmt->fourcc; 671 tile_image.phys0 = addr0; 672 tile_image.phys1 = addr1; 673 if (image->fmt->planar && !rot_swap_width_height) { 674 tile_image.u_offset = image->tile[tile_idx[0]].u_off; 675 tile_image.v_offset = image->tile[tile_idx[0]].v_off; 676 } 677 678 ipu_cpmem_set_image(channel, &tile_image); 679 680 if (rot_mode) 681 ipu_cpmem_set_rotation(channel, rot_mode); 682 683 if (channel == chan->rotation_in_chan || 684 channel == chan->rotation_out_chan) { 685 burst_size = 8; 686 ipu_cpmem_set_block_mode(channel); 687 } else 688 burst_size = (width % 16) ? 8 : 16; 689 690 ipu_cpmem_set_burstsize(channel, burst_size); 691 692 ipu_ic_task_idma_init(chan->ic, channel, width, height, 693 burst_size, rot_mode); 694 695 /* 696 * Setting a non-zero AXI ID collides with the PRG AXI snooping, so 697 * only do this when there is no PRG present. 698 */ 699 if (!channel->ipu->prg_priv) 700 ipu_cpmem_set_axi_id(channel, 1); 701 702 ipu_idmac_set_double_buffer(channel, ctx->double_buffering); 703 } 704 705 static int convert_start(struct ipu_image_convert_run *run, unsigned int tile) 706 { 707 struct ipu_image_convert_ctx *ctx = run->ctx; 708 struct ipu_image_convert_chan *chan = ctx->chan; 709 struct ipu_image_convert_priv *priv = chan->priv; 710 struct ipu_image_convert_image *s_image = &ctx->in; 711 struct ipu_image_convert_image *d_image = &ctx->out; 712 enum ipu_color_space src_cs, dest_cs; 713 unsigned int dst_tile = ctx->out_tile_map[tile]; 714 unsigned int dest_width, dest_height; 715 int ret; 716 717 dev_dbg(priv->ipu->dev, "%s: task %u: starting ctx %p run %p tile %u -> %u\n", 718 __func__, chan->ic_task, ctx, run, tile, dst_tile); 719 720 src_cs = ipu_pixelformat_to_colorspace(s_image->fmt->fourcc); 721 dest_cs = ipu_pixelformat_to_colorspace(d_image->fmt->fourcc); 722 723 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 724 /* swap width/height for resizer */ 725 dest_width = d_image->tile[dst_tile].height; 726 dest_height = d_image->tile[dst_tile].width; 727 } else { 728 dest_width = d_image->tile[dst_tile].width; 729 dest_height = d_image->tile[dst_tile].height; 730 } 731 732 /* setup the IC resizer and CSC */ 733 ret = ipu_ic_task_init(chan->ic, 734 s_image->tile[tile].width, 735 s_image->tile[tile].height, 736 dest_width, 737 dest_height, 738 src_cs, dest_cs); 739 if (ret) { 740 dev_err(priv->ipu->dev, "ipu_ic_task_init failed, %d\n", ret); 741 return ret; 742 } 743 744 /* init the source MEM-->IC PP IDMAC channel */ 745 init_idmac_channel(ctx, chan->in_chan, s_image, 746 IPU_ROTATE_NONE, false, tile); 747 748 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 749 /* init the IC PP-->MEM IDMAC channel */ 750 init_idmac_channel(ctx, chan->out_chan, d_image, 751 IPU_ROTATE_NONE, true, tile); 752 753 /* init the MEM-->IC PP ROT IDMAC channel */ 754 init_idmac_channel(ctx, chan->rotation_in_chan, d_image, 755 ctx->rot_mode, true, tile); 756 757 /* init the destination IC PP ROT-->MEM IDMAC channel */ 758 init_idmac_channel(ctx, chan->rotation_out_chan, d_image, 759 IPU_ROTATE_NONE, false, tile); 760 761 /* now link IC PP-->MEM to MEM-->IC PP ROT */ 762 ipu_idmac_link(chan->out_chan, chan->rotation_in_chan); 763 } else { 764 /* init the destination IC PP-->MEM IDMAC channel */ 765 init_idmac_channel(ctx, chan->out_chan, d_image, 766 ctx->rot_mode, false, tile); 767 } 768 769 /* enable the IC */ 770 ipu_ic_enable(chan->ic); 771 772 /* set buffers ready */ 773 ipu_idmac_select_buffer(chan->in_chan, 0); 774 ipu_idmac_select_buffer(chan->out_chan, 0); 775 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 776 ipu_idmac_select_buffer(chan->rotation_out_chan, 0); 777 if (ctx->double_buffering) { 778 ipu_idmac_select_buffer(chan->in_chan, 1); 779 ipu_idmac_select_buffer(chan->out_chan, 1); 780 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 781 ipu_idmac_select_buffer(chan->rotation_out_chan, 1); 782 } 783 784 /* enable the channels! */ 785 ipu_idmac_enable_channel(chan->in_chan); 786 ipu_idmac_enable_channel(chan->out_chan); 787 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 788 ipu_idmac_enable_channel(chan->rotation_in_chan); 789 ipu_idmac_enable_channel(chan->rotation_out_chan); 790 } 791 792 ipu_ic_task_enable(chan->ic); 793 794 ipu_cpmem_dump(chan->in_chan); 795 ipu_cpmem_dump(chan->out_chan); 796 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 797 ipu_cpmem_dump(chan->rotation_in_chan); 798 ipu_cpmem_dump(chan->rotation_out_chan); 799 } 800 801 ipu_dump(priv->ipu); 802 803 return 0; 804 } 805 806 /* hold irqlock when calling */ 807 static int do_run(struct ipu_image_convert_run *run) 808 { 809 struct ipu_image_convert_ctx *ctx = run->ctx; 810 struct ipu_image_convert_chan *chan = ctx->chan; 811 812 lockdep_assert_held(&chan->irqlock); 813 814 ctx->in.base.phys0 = run->in_phys; 815 ctx->out.base.phys0 = run->out_phys; 816 817 ctx->cur_buf_num = 0; 818 ctx->next_tile = 1; 819 820 /* remove run from pending_q and set as current */ 821 list_del(&run->list); 822 chan->current_run = run; 823 824 return convert_start(run, 0); 825 } 826 827 /* hold irqlock when calling */ 828 static void run_next(struct ipu_image_convert_chan *chan) 829 { 830 struct ipu_image_convert_priv *priv = chan->priv; 831 struct ipu_image_convert_run *run, *tmp; 832 int ret; 833 834 lockdep_assert_held(&chan->irqlock); 835 836 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 837 /* skip contexts that are aborting */ 838 if (run->ctx->aborting) { 839 dev_dbg(priv->ipu->dev, 840 "%s: task %u: skipping aborting ctx %p run %p\n", 841 __func__, chan->ic_task, run->ctx, run); 842 continue; 843 } 844 845 ret = do_run(run); 846 if (!ret) 847 break; 848 849 /* 850 * something went wrong with start, add the run 851 * to done q and continue to the next run in the 852 * pending q. 853 */ 854 run->status = ret; 855 list_add_tail(&run->list, &chan->done_q); 856 chan->current_run = NULL; 857 } 858 } 859 860 static void empty_done_q(struct ipu_image_convert_chan *chan) 861 { 862 struct ipu_image_convert_priv *priv = chan->priv; 863 struct ipu_image_convert_run *run; 864 unsigned long flags; 865 866 spin_lock_irqsave(&chan->irqlock, flags); 867 868 while (!list_empty(&chan->done_q)) { 869 run = list_entry(chan->done_q.next, 870 struct ipu_image_convert_run, 871 list); 872 873 list_del(&run->list); 874 875 dev_dbg(priv->ipu->dev, 876 "%s: task %u: completing ctx %p run %p with %d\n", 877 __func__, chan->ic_task, run->ctx, run, run->status); 878 879 /* call the completion callback and free the run */ 880 spin_unlock_irqrestore(&chan->irqlock, flags); 881 run->ctx->complete(run, run->ctx->complete_context); 882 spin_lock_irqsave(&chan->irqlock, flags); 883 } 884 885 spin_unlock_irqrestore(&chan->irqlock, flags); 886 } 887 888 /* 889 * the bottom half thread clears out the done_q, calling the 890 * completion handler for each. 891 */ 892 static irqreturn_t do_bh(int irq, void *dev_id) 893 { 894 struct ipu_image_convert_chan *chan = dev_id; 895 struct ipu_image_convert_priv *priv = chan->priv; 896 struct ipu_image_convert_ctx *ctx; 897 unsigned long flags; 898 899 dev_dbg(priv->ipu->dev, "%s: task %u: enter\n", __func__, 900 chan->ic_task); 901 902 empty_done_q(chan); 903 904 spin_lock_irqsave(&chan->irqlock, flags); 905 906 /* 907 * the done_q is cleared out, signal any contexts 908 * that are aborting that abort can complete. 909 */ 910 list_for_each_entry(ctx, &chan->ctx_list, list) { 911 if (ctx->aborting) { 912 dev_dbg(priv->ipu->dev, 913 "%s: task %u: signaling abort for ctx %p\n", 914 __func__, chan->ic_task, ctx); 915 complete_all(&ctx->aborted); 916 } 917 } 918 919 spin_unlock_irqrestore(&chan->irqlock, flags); 920 921 dev_dbg(priv->ipu->dev, "%s: task %u: exit\n", __func__, 922 chan->ic_task); 923 924 return IRQ_HANDLED; 925 } 926 927 /* hold irqlock when calling */ 928 static irqreturn_t do_irq(struct ipu_image_convert_run *run) 929 { 930 struct ipu_image_convert_ctx *ctx = run->ctx; 931 struct ipu_image_convert_chan *chan = ctx->chan; 932 struct ipu_image_tile *src_tile, *dst_tile; 933 struct ipu_image_convert_image *s_image = &ctx->in; 934 struct ipu_image_convert_image *d_image = &ctx->out; 935 struct ipuv3_channel *outch; 936 unsigned int dst_idx; 937 938 lockdep_assert_held(&chan->irqlock); 939 940 outch = ipu_rot_mode_is_irt(ctx->rot_mode) ? 941 chan->rotation_out_chan : chan->out_chan; 942 943 /* 944 * It is difficult to stop the channel DMA before the channels 945 * enter the paused state. Without double-buffering the channels 946 * are always in a paused state when the EOF irq occurs, so it 947 * is safe to stop the channels now. For double-buffering we 948 * just ignore the abort until the operation completes, when it 949 * is safe to shut down. 950 */ 951 if (ctx->aborting && !ctx->double_buffering) { 952 convert_stop(run); 953 run->status = -EIO; 954 goto done; 955 } 956 957 if (ctx->next_tile == ctx->num_tiles) { 958 /* 959 * the conversion is complete 960 */ 961 convert_stop(run); 962 run->status = 0; 963 goto done; 964 } 965 966 /* 967 * not done, place the next tile buffers. 968 */ 969 if (!ctx->double_buffering) { 970 971 src_tile = &s_image->tile[ctx->next_tile]; 972 dst_idx = ctx->out_tile_map[ctx->next_tile]; 973 dst_tile = &d_image->tile[dst_idx]; 974 975 ipu_cpmem_set_buffer(chan->in_chan, 0, 976 s_image->base.phys0 + src_tile->offset); 977 ipu_cpmem_set_buffer(outch, 0, 978 d_image->base.phys0 + dst_tile->offset); 979 if (s_image->fmt->planar) 980 ipu_cpmem_set_uv_offset(chan->in_chan, 981 src_tile->u_off, 982 src_tile->v_off); 983 if (d_image->fmt->planar) 984 ipu_cpmem_set_uv_offset(outch, 985 dst_tile->u_off, 986 dst_tile->v_off); 987 988 ipu_idmac_select_buffer(chan->in_chan, 0); 989 ipu_idmac_select_buffer(outch, 0); 990 991 } else if (ctx->next_tile < ctx->num_tiles - 1) { 992 993 src_tile = &s_image->tile[ctx->next_tile + 1]; 994 dst_idx = ctx->out_tile_map[ctx->next_tile + 1]; 995 dst_tile = &d_image->tile[dst_idx]; 996 997 ipu_cpmem_set_buffer(chan->in_chan, ctx->cur_buf_num, 998 s_image->base.phys0 + src_tile->offset); 999 ipu_cpmem_set_buffer(outch, ctx->cur_buf_num, 1000 d_image->base.phys0 + dst_tile->offset); 1001 1002 ipu_idmac_select_buffer(chan->in_chan, ctx->cur_buf_num); 1003 ipu_idmac_select_buffer(outch, ctx->cur_buf_num); 1004 1005 ctx->cur_buf_num ^= 1; 1006 } 1007 1008 ctx->next_tile++; 1009 return IRQ_HANDLED; 1010 done: 1011 list_add_tail(&run->list, &chan->done_q); 1012 chan->current_run = NULL; 1013 run_next(chan); 1014 return IRQ_WAKE_THREAD; 1015 } 1016 1017 static irqreturn_t norotate_irq(int irq, void *data) 1018 { 1019 struct ipu_image_convert_chan *chan = data; 1020 struct ipu_image_convert_ctx *ctx; 1021 struct ipu_image_convert_run *run; 1022 unsigned long flags; 1023 irqreturn_t ret; 1024 1025 spin_lock_irqsave(&chan->irqlock, flags); 1026 1027 /* get current run and its context */ 1028 run = chan->current_run; 1029 if (!run) { 1030 ret = IRQ_NONE; 1031 goto out; 1032 } 1033 1034 ctx = run->ctx; 1035 1036 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1037 /* this is a rotation operation, just ignore */ 1038 spin_unlock_irqrestore(&chan->irqlock, flags); 1039 return IRQ_HANDLED; 1040 } 1041 1042 ret = do_irq(run); 1043 out: 1044 spin_unlock_irqrestore(&chan->irqlock, flags); 1045 return ret; 1046 } 1047 1048 static irqreturn_t rotate_irq(int irq, void *data) 1049 { 1050 struct ipu_image_convert_chan *chan = data; 1051 struct ipu_image_convert_priv *priv = chan->priv; 1052 struct ipu_image_convert_ctx *ctx; 1053 struct ipu_image_convert_run *run; 1054 unsigned long flags; 1055 irqreturn_t ret; 1056 1057 spin_lock_irqsave(&chan->irqlock, flags); 1058 1059 /* get current run and its context */ 1060 run = chan->current_run; 1061 if (!run) { 1062 ret = IRQ_NONE; 1063 goto out; 1064 } 1065 1066 ctx = run->ctx; 1067 1068 if (!ipu_rot_mode_is_irt(ctx->rot_mode)) { 1069 /* this was NOT a rotation operation, shouldn't happen */ 1070 dev_err(priv->ipu->dev, "Unexpected rotation interrupt\n"); 1071 spin_unlock_irqrestore(&chan->irqlock, flags); 1072 return IRQ_HANDLED; 1073 } 1074 1075 ret = do_irq(run); 1076 out: 1077 spin_unlock_irqrestore(&chan->irqlock, flags); 1078 return ret; 1079 } 1080 1081 /* 1082 * try to force the completion of runs for this ctx. Called when 1083 * abort wait times out in ipu_image_convert_abort(). 1084 */ 1085 static void force_abort(struct ipu_image_convert_ctx *ctx) 1086 { 1087 struct ipu_image_convert_chan *chan = ctx->chan; 1088 struct ipu_image_convert_run *run; 1089 unsigned long flags; 1090 1091 spin_lock_irqsave(&chan->irqlock, flags); 1092 1093 run = chan->current_run; 1094 if (run && run->ctx == ctx) { 1095 convert_stop(run); 1096 run->status = -EIO; 1097 list_add_tail(&run->list, &chan->done_q); 1098 chan->current_run = NULL; 1099 run_next(chan); 1100 } 1101 1102 spin_unlock_irqrestore(&chan->irqlock, flags); 1103 1104 empty_done_q(chan); 1105 } 1106 1107 static void release_ipu_resources(struct ipu_image_convert_chan *chan) 1108 { 1109 if (chan->out_eof_irq >= 0) 1110 free_irq(chan->out_eof_irq, chan); 1111 if (chan->rot_out_eof_irq >= 0) 1112 free_irq(chan->rot_out_eof_irq, chan); 1113 1114 if (!IS_ERR_OR_NULL(chan->in_chan)) 1115 ipu_idmac_put(chan->in_chan); 1116 if (!IS_ERR_OR_NULL(chan->out_chan)) 1117 ipu_idmac_put(chan->out_chan); 1118 if (!IS_ERR_OR_NULL(chan->rotation_in_chan)) 1119 ipu_idmac_put(chan->rotation_in_chan); 1120 if (!IS_ERR_OR_NULL(chan->rotation_out_chan)) 1121 ipu_idmac_put(chan->rotation_out_chan); 1122 if (!IS_ERR_OR_NULL(chan->ic)) 1123 ipu_ic_put(chan->ic); 1124 1125 chan->in_chan = chan->out_chan = chan->rotation_in_chan = 1126 chan->rotation_out_chan = NULL; 1127 chan->out_eof_irq = chan->rot_out_eof_irq = -1; 1128 } 1129 1130 static int get_ipu_resources(struct ipu_image_convert_chan *chan) 1131 { 1132 const struct ipu_image_convert_dma_chan *dma = chan->dma_ch; 1133 struct ipu_image_convert_priv *priv = chan->priv; 1134 int ret; 1135 1136 /* get IC */ 1137 chan->ic = ipu_ic_get(priv->ipu, chan->ic_task); 1138 if (IS_ERR(chan->ic)) { 1139 dev_err(priv->ipu->dev, "could not acquire IC\n"); 1140 ret = PTR_ERR(chan->ic); 1141 goto err; 1142 } 1143 1144 /* get IDMAC channels */ 1145 chan->in_chan = ipu_idmac_get(priv->ipu, dma->in); 1146 chan->out_chan = ipu_idmac_get(priv->ipu, dma->out); 1147 if (IS_ERR(chan->in_chan) || IS_ERR(chan->out_chan)) { 1148 dev_err(priv->ipu->dev, "could not acquire idmac channels\n"); 1149 ret = -EBUSY; 1150 goto err; 1151 } 1152 1153 chan->rotation_in_chan = ipu_idmac_get(priv->ipu, dma->rot_in); 1154 chan->rotation_out_chan = ipu_idmac_get(priv->ipu, dma->rot_out); 1155 if (IS_ERR(chan->rotation_in_chan) || IS_ERR(chan->rotation_out_chan)) { 1156 dev_err(priv->ipu->dev, 1157 "could not acquire idmac rotation channels\n"); 1158 ret = -EBUSY; 1159 goto err; 1160 } 1161 1162 /* acquire the EOF interrupts */ 1163 chan->out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1164 chan->out_chan, 1165 IPU_IRQ_EOF); 1166 1167 ret = request_threaded_irq(chan->out_eof_irq, norotate_irq, do_bh, 1168 0, "ipu-ic", chan); 1169 if (ret < 0) { 1170 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1171 chan->out_eof_irq); 1172 chan->out_eof_irq = -1; 1173 goto err; 1174 } 1175 1176 chan->rot_out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1177 chan->rotation_out_chan, 1178 IPU_IRQ_EOF); 1179 1180 ret = request_threaded_irq(chan->rot_out_eof_irq, rotate_irq, do_bh, 1181 0, "ipu-ic", chan); 1182 if (ret < 0) { 1183 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1184 chan->rot_out_eof_irq); 1185 chan->rot_out_eof_irq = -1; 1186 goto err; 1187 } 1188 1189 return 0; 1190 err: 1191 release_ipu_resources(chan); 1192 return ret; 1193 } 1194 1195 static int fill_image(struct ipu_image_convert_ctx *ctx, 1196 struct ipu_image_convert_image *ic_image, 1197 struct ipu_image *image, 1198 enum ipu_image_convert_type type) 1199 { 1200 struct ipu_image_convert_priv *priv = ctx->chan->priv; 1201 1202 ic_image->base = *image; 1203 ic_image->type = type; 1204 1205 ic_image->fmt = get_format(image->pix.pixelformat); 1206 if (!ic_image->fmt) { 1207 dev_err(priv->ipu->dev, "pixelformat not supported for %s\n", 1208 type == IMAGE_CONVERT_OUT ? "Output" : "Input"); 1209 return -EINVAL; 1210 } 1211 1212 if (ic_image->fmt->planar) 1213 ic_image->stride = ic_image->base.pix.width; 1214 else 1215 ic_image->stride = ic_image->base.pix.bytesperline; 1216 1217 calc_tile_dimensions(ctx, ic_image); 1218 1219 return calc_tile_offsets(ctx, ic_image); 1220 } 1221 1222 /* borrowed from drivers/media/v4l2-core/v4l2-common.c */ 1223 static unsigned int clamp_align(unsigned int x, unsigned int min, 1224 unsigned int max, unsigned int align) 1225 { 1226 /* Bits that must be zero to be aligned */ 1227 unsigned int mask = ~((1 << align) - 1); 1228 1229 /* Clamp to aligned min and max */ 1230 x = clamp(x, (min + ~mask) & mask, max & mask); 1231 1232 /* Round to nearest aligned value */ 1233 if (align) 1234 x = (x + (1 << (align - 1))) & mask; 1235 1236 return x; 1237 } 1238 1239 /* 1240 * We have to adjust the tile width such that the tile physaddrs and 1241 * U and V plane offsets are multiples of 8 bytes as required by 1242 * the IPU DMA Controller. For the planar formats, this corresponds 1243 * to a pixel alignment of 16 (but use a more formal equation since 1244 * the variables are available). For all the packed formats, 8 is 1245 * good enough. 1246 */ 1247 static inline u32 tile_width_align(const struct ipu_image_pixfmt *fmt) 1248 { 1249 return fmt->planar ? 8 * fmt->uv_width_dec : 8; 1250 } 1251 1252 /* 1253 * For tile height alignment, we have to ensure that the output tile 1254 * heights are multiples of 8 lines if the IRT is required by the 1255 * given rotation mode (the IRT performs rotations on 8x8 blocks 1256 * at a time). If the IRT is not used, or for input image tiles, 1257 * 2 lines are good enough. 1258 */ 1259 static inline u32 tile_height_align(enum ipu_image_convert_type type, 1260 enum ipu_rotate_mode rot_mode) 1261 { 1262 return (type == IMAGE_CONVERT_OUT && 1263 ipu_rot_mode_is_irt(rot_mode)) ? 8 : 2; 1264 } 1265 1266 /* Adjusts input/output images to IPU restrictions */ 1267 void ipu_image_convert_adjust(struct ipu_image *in, struct ipu_image *out, 1268 enum ipu_rotate_mode rot_mode) 1269 { 1270 const struct ipu_image_pixfmt *infmt, *outfmt; 1271 unsigned int num_in_rows, num_in_cols; 1272 unsigned int num_out_rows, num_out_cols; 1273 u32 w_align, h_align; 1274 1275 infmt = get_format(in->pix.pixelformat); 1276 outfmt = get_format(out->pix.pixelformat); 1277 1278 /* set some default pixel formats if needed */ 1279 if (!infmt) { 1280 in->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1281 infmt = get_format(V4L2_PIX_FMT_RGB24); 1282 } 1283 if (!outfmt) { 1284 out->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1285 outfmt = get_format(V4L2_PIX_FMT_RGB24); 1286 } 1287 1288 /* image converter does not handle fields */ 1289 in->pix.field = out->pix.field = V4L2_FIELD_NONE; 1290 1291 /* resizer cannot downsize more than 4:1 */ 1292 if (ipu_rot_mode_is_irt(rot_mode)) { 1293 out->pix.height = max_t(__u32, out->pix.height, 1294 in->pix.width / 4); 1295 out->pix.width = max_t(__u32, out->pix.width, 1296 in->pix.height / 4); 1297 } else { 1298 out->pix.width = max_t(__u32, out->pix.width, 1299 in->pix.width / 4); 1300 out->pix.height = max_t(__u32, out->pix.height, 1301 in->pix.height / 4); 1302 } 1303 1304 /* get tiling rows/cols from output format */ 1305 num_out_rows = num_stripes(out->pix.height); 1306 num_out_cols = num_stripes(out->pix.width); 1307 if (ipu_rot_mode_is_irt(rot_mode)) { 1308 num_in_rows = num_out_cols; 1309 num_in_cols = num_out_rows; 1310 } else { 1311 num_in_rows = num_out_rows; 1312 num_in_cols = num_out_cols; 1313 } 1314 1315 /* align input width/height */ 1316 w_align = ilog2(tile_width_align(infmt) * num_in_cols); 1317 h_align = ilog2(tile_height_align(IMAGE_CONVERT_IN, rot_mode) * 1318 num_in_rows); 1319 in->pix.width = clamp_align(in->pix.width, MIN_W, MAX_W, w_align); 1320 in->pix.height = clamp_align(in->pix.height, MIN_H, MAX_H, h_align); 1321 1322 /* align output width/height */ 1323 w_align = ilog2(tile_width_align(outfmt) * num_out_cols); 1324 h_align = ilog2(tile_height_align(IMAGE_CONVERT_OUT, rot_mode) * 1325 num_out_rows); 1326 out->pix.width = clamp_align(out->pix.width, MIN_W, MAX_W, w_align); 1327 out->pix.height = clamp_align(out->pix.height, MIN_H, MAX_H, h_align); 1328 1329 /* set input/output strides and image sizes */ 1330 in->pix.bytesperline = (in->pix.width * infmt->bpp) >> 3; 1331 in->pix.sizeimage = in->pix.height * in->pix.bytesperline; 1332 out->pix.bytesperline = (out->pix.width * outfmt->bpp) >> 3; 1333 out->pix.sizeimage = out->pix.height * out->pix.bytesperline; 1334 } 1335 EXPORT_SYMBOL_GPL(ipu_image_convert_adjust); 1336 1337 /* 1338 * this is used by ipu_image_convert_prepare() to verify set input and 1339 * output images are valid before starting the conversion. Clients can 1340 * also call it before calling ipu_image_convert_prepare(). 1341 */ 1342 int ipu_image_convert_verify(struct ipu_image *in, struct ipu_image *out, 1343 enum ipu_rotate_mode rot_mode) 1344 { 1345 struct ipu_image testin, testout; 1346 1347 testin = *in; 1348 testout = *out; 1349 1350 ipu_image_convert_adjust(&testin, &testout, rot_mode); 1351 1352 if (testin.pix.width != in->pix.width || 1353 testin.pix.height != in->pix.height || 1354 testout.pix.width != out->pix.width || 1355 testout.pix.height != out->pix.height) 1356 return -EINVAL; 1357 1358 return 0; 1359 } 1360 EXPORT_SYMBOL_GPL(ipu_image_convert_verify); 1361 1362 /* 1363 * Call ipu_image_convert_prepare() to prepare for the conversion of 1364 * given images and rotation mode. Returns a new conversion context. 1365 */ 1366 struct ipu_image_convert_ctx * 1367 ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1368 struct ipu_image *in, struct ipu_image *out, 1369 enum ipu_rotate_mode rot_mode, 1370 ipu_image_convert_cb_t complete, 1371 void *complete_context) 1372 { 1373 struct ipu_image_convert_priv *priv = ipu->image_convert_priv; 1374 struct ipu_image_convert_image *s_image, *d_image; 1375 struct ipu_image_convert_chan *chan; 1376 struct ipu_image_convert_ctx *ctx; 1377 unsigned long flags; 1378 bool get_res; 1379 int ret; 1380 1381 if (!in || !out || !complete || 1382 (ic_task != IC_TASK_VIEWFINDER && 1383 ic_task != IC_TASK_POST_PROCESSOR)) 1384 return ERR_PTR(-EINVAL); 1385 1386 /* verify the in/out images before continuing */ 1387 ret = ipu_image_convert_verify(in, out, rot_mode); 1388 if (ret) { 1389 dev_err(priv->ipu->dev, "%s: in/out formats invalid\n", 1390 __func__); 1391 return ERR_PTR(ret); 1392 } 1393 1394 chan = &priv->chan[ic_task]; 1395 1396 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 1397 if (!ctx) 1398 return ERR_PTR(-ENOMEM); 1399 1400 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p\n", __func__, 1401 chan->ic_task, ctx); 1402 1403 ctx->chan = chan; 1404 init_completion(&ctx->aborted); 1405 1406 s_image = &ctx->in; 1407 d_image = &ctx->out; 1408 1409 /* set tiling and rotation */ 1410 d_image->num_rows = num_stripes(out->pix.height); 1411 d_image->num_cols = num_stripes(out->pix.width); 1412 if (ipu_rot_mode_is_irt(rot_mode)) { 1413 s_image->num_rows = d_image->num_cols; 1414 s_image->num_cols = d_image->num_rows; 1415 } else { 1416 s_image->num_rows = d_image->num_rows; 1417 s_image->num_cols = d_image->num_cols; 1418 } 1419 1420 ctx->num_tiles = d_image->num_cols * d_image->num_rows; 1421 ctx->rot_mode = rot_mode; 1422 1423 ret = fill_image(ctx, s_image, in, IMAGE_CONVERT_IN); 1424 if (ret) 1425 goto out_free; 1426 ret = fill_image(ctx, d_image, out, IMAGE_CONVERT_OUT); 1427 if (ret) 1428 goto out_free; 1429 1430 calc_out_tile_map(ctx); 1431 1432 dump_format(ctx, s_image); 1433 dump_format(ctx, d_image); 1434 1435 ctx->complete = complete; 1436 ctx->complete_context = complete_context; 1437 1438 /* 1439 * Can we use double-buffering for this operation? If there is 1440 * only one tile (the whole image can be converted in a single 1441 * operation) there's no point in using double-buffering. Also, 1442 * the IPU's IDMAC channels allow only a single U and V plane 1443 * offset shared between both buffers, but these offsets change 1444 * for every tile, and therefore would have to be updated for 1445 * each buffer which is not possible. So double-buffering is 1446 * impossible when either the source or destination images are 1447 * a planar format (YUV420, YUV422P, etc.). 1448 */ 1449 ctx->double_buffering = (ctx->num_tiles > 1 && 1450 !s_image->fmt->planar && 1451 !d_image->fmt->planar); 1452 1453 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1454 unsigned long intermediate_size = d_image->tile[0].size; 1455 unsigned int i; 1456 1457 for (i = 1; i < ctx->num_tiles; i++) { 1458 if (d_image->tile[i].size > intermediate_size) 1459 intermediate_size = d_image->tile[i].size; 1460 } 1461 1462 ret = alloc_dma_buf(priv, &ctx->rot_intermediate[0], 1463 intermediate_size); 1464 if (ret) 1465 goto out_free; 1466 if (ctx->double_buffering) { 1467 ret = alloc_dma_buf(priv, 1468 &ctx->rot_intermediate[1], 1469 intermediate_size); 1470 if (ret) 1471 goto out_free_dmabuf0; 1472 } 1473 } 1474 1475 spin_lock_irqsave(&chan->irqlock, flags); 1476 1477 get_res = list_empty(&chan->ctx_list); 1478 1479 list_add_tail(&ctx->list, &chan->ctx_list); 1480 1481 spin_unlock_irqrestore(&chan->irqlock, flags); 1482 1483 if (get_res) { 1484 ret = get_ipu_resources(chan); 1485 if (ret) 1486 goto out_free_dmabuf1; 1487 } 1488 1489 return ctx; 1490 1491 out_free_dmabuf1: 1492 free_dma_buf(priv, &ctx->rot_intermediate[1]); 1493 spin_lock_irqsave(&chan->irqlock, flags); 1494 list_del(&ctx->list); 1495 spin_unlock_irqrestore(&chan->irqlock, flags); 1496 out_free_dmabuf0: 1497 free_dma_buf(priv, &ctx->rot_intermediate[0]); 1498 out_free: 1499 kfree(ctx); 1500 return ERR_PTR(ret); 1501 } 1502 EXPORT_SYMBOL_GPL(ipu_image_convert_prepare); 1503 1504 /* 1505 * Carry out a single image conversion run. Only the physaddr's of the input 1506 * and output image buffers are needed. The conversion context must have 1507 * been created previously with ipu_image_convert_prepare(). 1508 */ 1509 int ipu_image_convert_queue(struct ipu_image_convert_run *run) 1510 { 1511 struct ipu_image_convert_chan *chan; 1512 struct ipu_image_convert_priv *priv; 1513 struct ipu_image_convert_ctx *ctx; 1514 unsigned long flags; 1515 int ret = 0; 1516 1517 if (!run || !run->ctx || !run->in_phys || !run->out_phys) 1518 return -EINVAL; 1519 1520 ctx = run->ctx; 1521 chan = ctx->chan; 1522 priv = chan->priv; 1523 1524 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p run %p\n", __func__, 1525 chan->ic_task, ctx, run); 1526 1527 INIT_LIST_HEAD(&run->list); 1528 1529 spin_lock_irqsave(&chan->irqlock, flags); 1530 1531 if (ctx->aborting) { 1532 ret = -EIO; 1533 goto unlock; 1534 } 1535 1536 list_add_tail(&run->list, &chan->pending_q); 1537 1538 if (!chan->current_run) { 1539 ret = do_run(run); 1540 if (ret) 1541 chan->current_run = NULL; 1542 } 1543 unlock: 1544 spin_unlock_irqrestore(&chan->irqlock, flags); 1545 return ret; 1546 } 1547 EXPORT_SYMBOL_GPL(ipu_image_convert_queue); 1548 1549 /* Abort any active or pending conversions for this context */ 1550 static void __ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 1551 { 1552 struct ipu_image_convert_chan *chan = ctx->chan; 1553 struct ipu_image_convert_priv *priv = chan->priv; 1554 struct ipu_image_convert_run *run, *active_run, *tmp; 1555 unsigned long flags; 1556 int run_count, ret; 1557 1558 spin_lock_irqsave(&chan->irqlock, flags); 1559 1560 /* move all remaining pending runs in this context to done_q */ 1561 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 1562 if (run->ctx != ctx) 1563 continue; 1564 run->status = -EIO; 1565 list_move_tail(&run->list, &chan->done_q); 1566 } 1567 1568 run_count = get_run_count(ctx, &chan->done_q); 1569 active_run = (chan->current_run && chan->current_run->ctx == ctx) ? 1570 chan->current_run : NULL; 1571 1572 if (active_run) 1573 reinit_completion(&ctx->aborted); 1574 1575 ctx->aborting = true; 1576 1577 spin_unlock_irqrestore(&chan->irqlock, flags); 1578 1579 if (!run_count && !active_run) { 1580 dev_dbg(priv->ipu->dev, 1581 "%s: task %u: no abort needed for ctx %p\n", 1582 __func__, chan->ic_task, ctx); 1583 return; 1584 } 1585 1586 if (!active_run) { 1587 empty_done_q(chan); 1588 return; 1589 } 1590 1591 dev_dbg(priv->ipu->dev, 1592 "%s: task %u: wait for completion: %d runs\n", 1593 __func__, chan->ic_task, run_count); 1594 1595 ret = wait_for_completion_timeout(&ctx->aborted, 1596 msecs_to_jiffies(10000)); 1597 if (ret == 0) { 1598 dev_warn(priv->ipu->dev, "%s: timeout\n", __func__); 1599 force_abort(ctx); 1600 } 1601 } 1602 1603 void ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 1604 { 1605 __ipu_image_convert_abort(ctx); 1606 ctx->aborting = false; 1607 } 1608 EXPORT_SYMBOL_GPL(ipu_image_convert_abort); 1609 1610 /* Unprepare image conversion context */ 1611 void ipu_image_convert_unprepare(struct ipu_image_convert_ctx *ctx) 1612 { 1613 struct ipu_image_convert_chan *chan = ctx->chan; 1614 struct ipu_image_convert_priv *priv = chan->priv; 1615 unsigned long flags; 1616 bool put_res; 1617 1618 /* make sure no runs are hanging around */ 1619 __ipu_image_convert_abort(ctx); 1620 1621 dev_dbg(priv->ipu->dev, "%s: task %u: removing ctx %p\n", __func__, 1622 chan->ic_task, ctx); 1623 1624 spin_lock_irqsave(&chan->irqlock, flags); 1625 1626 list_del(&ctx->list); 1627 1628 put_res = list_empty(&chan->ctx_list); 1629 1630 spin_unlock_irqrestore(&chan->irqlock, flags); 1631 1632 if (put_res) 1633 release_ipu_resources(chan); 1634 1635 free_dma_buf(priv, &ctx->rot_intermediate[1]); 1636 free_dma_buf(priv, &ctx->rot_intermediate[0]); 1637 1638 kfree(ctx); 1639 } 1640 EXPORT_SYMBOL_GPL(ipu_image_convert_unprepare); 1641 1642 /* 1643 * "Canned" asynchronous single image conversion. Allocates and returns 1644 * a new conversion run. On successful return the caller must free the 1645 * run and call ipu_image_convert_unprepare() after conversion completes. 1646 */ 1647 struct ipu_image_convert_run * 1648 ipu_image_convert(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1649 struct ipu_image *in, struct ipu_image *out, 1650 enum ipu_rotate_mode rot_mode, 1651 ipu_image_convert_cb_t complete, 1652 void *complete_context) 1653 { 1654 struct ipu_image_convert_ctx *ctx; 1655 struct ipu_image_convert_run *run; 1656 int ret; 1657 1658 ctx = ipu_image_convert_prepare(ipu, ic_task, in, out, rot_mode, 1659 complete, complete_context); 1660 if (IS_ERR(ctx)) 1661 return ERR_CAST(ctx); 1662 1663 run = kzalloc(sizeof(*run), GFP_KERNEL); 1664 if (!run) { 1665 ipu_image_convert_unprepare(ctx); 1666 return ERR_PTR(-ENOMEM); 1667 } 1668 1669 run->ctx = ctx; 1670 run->in_phys = in->phys0; 1671 run->out_phys = out->phys0; 1672 1673 ret = ipu_image_convert_queue(run); 1674 if (ret) { 1675 ipu_image_convert_unprepare(ctx); 1676 kfree(run); 1677 return ERR_PTR(ret); 1678 } 1679 1680 return run; 1681 } 1682 EXPORT_SYMBOL_GPL(ipu_image_convert); 1683 1684 /* "Canned" synchronous single image conversion */ 1685 static void image_convert_sync_complete(struct ipu_image_convert_run *run, 1686 void *data) 1687 { 1688 struct completion *comp = data; 1689 1690 complete(comp); 1691 } 1692 1693 int ipu_image_convert_sync(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1694 struct ipu_image *in, struct ipu_image *out, 1695 enum ipu_rotate_mode rot_mode) 1696 { 1697 struct ipu_image_convert_run *run; 1698 struct completion comp; 1699 int ret; 1700 1701 init_completion(&comp); 1702 1703 run = ipu_image_convert(ipu, ic_task, in, out, rot_mode, 1704 image_convert_sync_complete, &comp); 1705 if (IS_ERR(run)) 1706 return PTR_ERR(run); 1707 1708 ret = wait_for_completion_timeout(&comp, msecs_to_jiffies(10000)); 1709 ret = (ret == 0) ? -ETIMEDOUT : 0; 1710 1711 ipu_image_convert_unprepare(run->ctx); 1712 kfree(run); 1713 1714 return ret; 1715 } 1716 EXPORT_SYMBOL_GPL(ipu_image_convert_sync); 1717 1718 int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev) 1719 { 1720 struct ipu_image_convert_priv *priv; 1721 int i; 1722 1723 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1724 if (!priv) 1725 return -ENOMEM; 1726 1727 ipu->image_convert_priv = priv; 1728 priv->ipu = ipu; 1729 1730 for (i = 0; i < IC_NUM_TASKS; i++) { 1731 struct ipu_image_convert_chan *chan = &priv->chan[i]; 1732 1733 chan->ic_task = i; 1734 chan->priv = priv; 1735 chan->dma_ch = &image_convert_dma_chan[i]; 1736 chan->out_eof_irq = -1; 1737 chan->rot_out_eof_irq = -1; 1738 1739 spin_lock_init(&chan->irqlock); 1740 INIT_LIST_HEAD(&chan->ctx_list); 1741 INIT_LIST_HEAD(&chan->pending_q); 1742 INIT_LIST_HEAD(&chan->done_q); 1743 } 1744 1745 return 0; 1746 } 1747 1748 void ipu_image_convert_exit(struct ipu_soc *ipu) 1749 { 1750 } 1751