1 /* 2 * Copyright (C) 2012-2016 Mentor Graphics Inc. 3 * 4 * Queued image conversion support, with tiling and rotation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include <linux/interrupt.h> 18 #include <linux/dma-mapping.h> 19 #include <video/imx-ipu-image-convert.h> 20 #include "ipu-prv.h" 21 22 /* 23 * The IC Resizer has a restriction that the output frame from the 24 * resizer must be 1024 or less in both width (pixels) and height 25 * (lines). 26 * 27 * The image converter attempts to split up a conversion when 28 * the desired output (converted) frame resolution exceeds the 29 * IC resizer limit of 1024 in either dimension. 30 * 31 * If either dimension of the output frame exceeds the limit, the 32 * dimension is split into 1, 2, or 4 equal stripes, for a maximum 33 * of 4*4 or 16 tiles. A conversion is then carried out for each 34 * tile (but taking care to pass the full frame stride length to 35 * the DMA channel's parameter memory!). IDMA double-buffering is used 36 * to convert each tile back-to-back when possible (see note below 37 * when double_buffering boolean is set). 38 * 39 * Note that the input frame must be split up into the same number 40 * of tiles as the output frame. 41 * 42 * FIXME: at this point there is no attempt to deal with visible seams 43 * at the tile boundaries when upscaling. The seams are caused by a reset 44 * of the bilinear upscale interpolation when starting a new tile. The 45 * seams are barely visible for small upscale factors, but become 46 * increasingly visible as the upscale factor gets larger, since more 47 * interpolated pixels get thrown out at the tile boundaries. A possilble 48 * fix might be to overlap tiles of different sizes, but this must be done 49 * while also maintaining the IDMAC dma buffer address alignment and 8x8 IRT 50 * alignment restrictions of each tile. 51 */ 52 53 #define MAX_STRIPES_W 4 54 #define MAX_STRIPES_H 4 55 #define MAX_TILES (MAX_STRIPES_W * MAX_STRIPES_H) 56 57 #define MIN_W 16 58 #define MIN_H 8 59 #define MAX_W 4096 60 #define MAX_H 4096 61 62 enum ipu_image_convert_type { 63 IMAGE_CONVERT_IN = 0, 64 IMAGE_CONVERT_OUT, 65 }; 66 67 struct ipu_image_convert_dma_buf { 68 void *virt; 69 dma_addr_t phys; 70 unsigned long len; 71 }; 72 73 struct ipu_image_convert_dma_chan { 74 int in; 75 int out; 76 int rot_in; 77 int rot_out; 78 int vdi_in_p; 79 int vdi_in; 80 int vdi_in_n; 81 }; 82 83 /* dimensions of one tile */ 84 struct ipu_image_tile { 85 u32 width; 86 u32 height; 87 /* size and strides are in bytes */ 88 u32 size; 89 u32 stride; 90 u32 rot_stride; 91 /* start Y or packed offset of this tile */ 92 u32 offset; 93 /* offset from start to tile in U plane, for planar formats */ 94 u32 u_off; 95 /* offset from start to tile in V plane, for planar formats */ 96 u32 v_off; 97 }; 98 99 struct ipu_image_convert_image { 100 struct ipu_image base; 101 enum ipu_image_convert_type type; 102 103 const struct ipu_image_pixfmt *fmt; 104 unsigned int stride; 105 106 /* # of rows (horizontal stripes) if dest height is > 1024 */ 107 unsigned int num_rows; 108 /* # of columns (vertical stripes) if dest width is > 1024 */ 109 unsigned int num_cols; 110 111 struct ipu_image_tile tile[MAX_TILES]; 112 }; 113 114 struct ipu_image_pixfmt { 115 u32 fourcc; /* V4L2 fourcc */ 116 int bpp; /* total bpp */ 117 int uv_width_dec; /* decimation in width for U/V planes */ 118 int uv_height_dec; /* decimation in height for U/V planes */ 119 bool planar; /* planar format */ 120 bool uv_swapped; /* U and V planes are swapped */ 121 bool uv_packed; /* partial planar (U and V in same plane) */ 122 }; 123 124 struct ipu_image_convert_ctx; 125 struct ipu_image_convert_chan; 126 struct ipu_image_convert_priv; 127 128 struct ipu_image_convert_ctx { 129 struct ipu_image_convert_chan *chan; 130 131 ipu_image_convert_cb_t complete; 132 void *complete_context; 133 134 /* Source/destination image data and rotation mode */ 135 struct ipu_image_convert_image in; 136 struct ipu_image_convert_image out; 137 enum ipu_rotate_mode rot_mode; 138 139 /* intermediate buffer for rotation */ 140 struct ipu_image_convert_dma_buf rot_intermediate[2]; 141 142 /* current buffer number for double buffering */ 143 int cur_buf_num; 144 145 bool aborting; 146 struct completion aborted; 147 148 /* can we use double-buffering for this conversion operation? */ 149 bool double_buffering; 150 /* num_rows * num_cols */ 151 unsigned int num_tiles; 152 /* next tile to process */ 153 unsigned int next_tile; 154 /* where to place converted tile in dest image */ 155 unsigned int out_tile_map[MAX_TILES]; 156 157 struct list_head list; 158 }; 159 160 struct ipu_image_convert_chan { 161 struct ipu_image_convert_priv *priv; 162 163 enum ipu_ic_task ic_task; 164 const struct ipu_image_convert_dma_chan *dma_ch; 165 166 struct ipu_ic *ic; 167 struct ipuv3_channel *in_chan; 168 struct ipuv3_channel *out_chan; 169 struct ipuv3_channel *rotation_in_chan; 170 struct ipuv3_channel *rotation_out_chan; 171 172 /* the IPU end-of-frame irqs */ 173 int out_eof_irq; 174 int rot_out_eof_irq; 175 176 spinlock_t irqlock; 177 178 /* list of convert contexts */ 179 struct list_head ctx_list; 180 /* queue of conversion runs */ 181 struct list_head pending_q; 182 /* queue of completed runs */ 183 struct list_head done_q; 184 185 /* the current conversion run */ 186 struct ipu_image_convert_run *current_run; 187 }; 188 189 struct ipu_image_convert_priv { 190 struct ipu_image_convert_chan chan[IC_NUM_TASKS]; 191 struct ipu_soc *ipu; 192 }; 193 194 static const struct ipu_image_convert_dma_chan 195 image_convert_dma_chan[IC_NUM_TASKS] = { 196 [IC_TASK_VIEWFINDER] = { 197 .in = IPUV3_CHANNEL_MEM_IC_PRP_VF, 198 .out = IPUV3_CHANNEL_IC_PRP_VF_MEM, 199 .rot_in = IPUV3_CHANNEL_MEM_ROT_VF, 200 .rot_out = IPUV3_CHANNEL_ROT_VF_MEM, 201 .vdi_in_p = IPUV3_CHANNEL_MEM_VDI_PREV, 202 .vdi_in = IPUV3_CHANNEL_MEM_VDI_CUR, 203 .vdi_in_n = IPUV3_CHANNEL_MEM_VDI_NEXT, 204 }, 205 [IC_TASK_POST_PROCESSOR] = { 206 .in = IPUV3_CHANNEL_MEM_IC_PP, 207 .out = IPUV3_CHANNEL_IC_PP_MEM, 208 .rot_in = IPUV3_CHANNEL_MEM_ROT_PP, 209 .rot_out = IPUV3_CHANNEL_ROT_PP_MEM, 210 }, 211 }; 212 213 static const struct ipu_image_pixfmt image_convert_formats[] = { 214 { 215 .fourcc = V4L2_PIX_FMT_RGB565, 216 .bpp = 16, 217 }, { 218 .fourcc = V4L2_PIX_FMT_RGB24, 219 .bpp = 24, 220 }, { 221 .fourcc = V4L2_PIX_FMT_BGR24, 222 .bpp = 24, 223 }, { 224 .fourcc = V4L2_PIX_FMT_RGB32, 225 .bpp = 32, 226 }, { 227 .fourcc = V4L2_PIX_FMT_BGR32, 228 .bpp = 32, 229 }, { 230 .fourcc = V4L2_PIX_FMT_XRGB32, 231 .bpp = 32, 232 }, { 233 .fourcc = V4L2_PIX_FMT_XBGR32, 234 .bpp = 32, 235 }, { 236 .fourcc = V4L2_PIX_FMT_YUYV, 237 .bpp = 16, 238 .uv_width_dec = 2, 239 .uv_height_dec = 1, 240 }, { 241 .fourcc = V4L2_PIX_FMT_UYVY, 242 .bpp = 16, 243 .uv_width_dec = 2, 244 .uv_height_dec = 1, 245 }, { 246 .fourcc = V4L2_PIX_FMT_YUV420, 247 .bpp = 12, 248 .planar = true, 249 .uv_width_dec = 2, 250 .uv_height_dec = 2, 251 }, { 252 .fourcc = V4L2_PIX_FMT_YVU420, 253 .bpp = 12, 254 .planar = true, 255 .uv_width_dec = 2, 256 .uv_height_dec = 2, 257 .uv_swapped = true, 258 }, { 259 .fourcc = V4L2_PIX_FMT_NV12, 260 .bpp = 12, 261 .planar = true, 262 .uv_width_dec = 2, 263 .uv_height_dec = 2, 264 .uv_packed = true, 265 }, { 266 .fourcc = V4L2_PIX_FMT_YUV422P, 267 .bpp = 16, 268 .planar = true, 269 .uv_width_dec = 2, 270 .uv_height_dec = 1, 271 }, { 272 .fourcc = V4L2_PIX_FMT_NV16, 273 .bpp = 16, 274 .planar = true, 275 .uv_width_dec = 2, 276 .uv_height_dec = 1, 277 .uv_packed = true, 278 }, 279 }; 280 281 static const struct ipu_image_pixfmt *get_format(u32 fourcc) 282 { 283 const struct ipu_image_pixfmt *ret = NULL; 284 unsigned int i; 285 286 for (i = 0; i < ARRAY_SIZE(image_convert_formats); i++) { 287 if (image_convert_formats[i].fourcc == fourcc) { 288 ret = &image_convert_formats[i]; 289 break; 290 } 291 } 292 293 return ret; 294 } 295 296 static void dump_format(struct ipu_image_convert_ctx *ctx, 297 struct ipu_image_convert_image *ic_image) 298 { 299 struct ipu_image_convert_chan *chan = ctx->chan; 300 struct ipu_image_convert_priv *priv = chan->priv; 301 302 dev_dbg(priv->ipu->dev, 303 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles of size %dx%d), %c%c%c%c\n", 304 chan->ic_task, ctx, 305 ic_image->type == IMAGE_CONVERT_OUT ? "Output" : "Input", 306 ic_image->base.pix.width, ic_image->base.pix.height, 307 ic_image->num_cols, ic_image->num_rows, 308 ic_image->tile[0].width, ic_image->tile[0].height, 309 ic_image->fmt->fourcc & 0xff, 310 (ic_image->fmt->fourcc >> 8) & 0xff, 311 (ic_image->fmt->fourcc >> 16) & 0xff, 312 (ic_image->fmt->fourcc >> 24) & 0xff); 313 } 314 315 int ipu_image_convert_enum_format(int index, u32 *fourcc) 316 { 317 const struct ipu_image_pixfmt *fmt; 318 319 if (index >= (int)ARRAY_SIZE(image_convert_formats)) 320 return -EINVAL; 321 322 /* Format found */ 323 fmt = &image_convert_formats[index]; 324 *fourcc = fmt->fourcc; 325 return 0; 326 } 327 EXPORT_SYMBOL_GPL(ipu_image_convert_enum_format); 328 329 static void free_dma_buf(struct ipu_image_convert_priv *priv, 330 struct ipu_image_convert_dma_buf *buf) 331 { 332 if (buf->virt) 333 dma_free_coherent(priv->ipu->dev, 334 buf->len, buf->virt, buf->phys); 335 buf->virt = NULL; 336 buf->phys = 0; 337 } 338 339 static int alloc_dma_buf(struct ipu_image_convert_priv *priv, 340 struct ipu_image_convert_dma_buf *buf, 341 int size) 342 { 343 buf->len = PAGE_ALIGN(size); 344 buf->virt = dma_alloc_coherent(priv->ipu->dev, buf->len, &buf->phys, 345 GFP_DMA | GFP_KERNEL); 346 if (!buf->virt) { 347 dev_err(priv->ipu->dev, "failed to alloc dma buffer\n"); 348 return -ENOMEM; 349 } 350 351 return 0; 352 } 353 354 static inline int num_stripes(int dim) 355 { 356 if (dim <= 1024) 357 return 1; 358 else if (dim <= 2048) 359 return 2; 360 else 361 return 4; 362 } 363 364 static void calc_tile_dimensions(struct ipu_image_convert_ctx *ctx, 365 struct ipu_image_convert_image *image) 366 { 367 int i; 368 369 for (i = 0; i < ctx->num_tiles; i++) { 370 struct ipu_image_tile *tile = &image->tile[i]; 371 372 tile->height = image->base.pix.height / image->num_rows; 373 tile->width = image->base.pix.width / image->num_cols; 374 tile->size = ((tile->height * image->fmt->bpp) >> 3) * 375 tile->width; 376 377 if (image->fmt->planar) { 378 tile->stride = tile->width; 379 tile->rot_stride = tile->height; 380 } else { 381 tile->stride = 382 (image->fmt->bpp * tile->width) >> 3; 383 tile->rot_stride = 384 (image->fmt->bpp * tile->height) >> 3; 385 } 386 } 387 } 388 389 /* 390 * Use the rotation transformation to find the tile coordinates 391 * (row, col) of a tile in the destination frame that corresponds 392 * to the given tile coordinates of a source frame. The destination 393 * coordinate is then converted to a tile index. 394 */ 395 static int transform_tile_index(struct ipu_image_convert_ctx *ctx, 396 int src_row, int src_col) 397 { 398 struct ipu_image_convert_chan *chan = ctx->chan; 399 struct ipu_image_convert_priv *priv = chan->priv; 400 struct ipu_image_convert_image *s_image = &ctx->in; 401 struct ipu_image_convert_image *d_image = &ctx->out; 402 int dst_row, dst_col; 403 404 /* with no rotation it's a 1:1 mapping */ 405 if (ctx->rot_mode == IPU_ROTATE_NONE) 406 return src_row * s_image->num_cols + src_col; 407 408 /* 409 * before doing the transform, first we have to translate 410 * source row,col for an origin in the center of s_image 411 */ 412 src_row = src_row * 2 - (s_image->num_rows - 1); 413 src_col = src_col * 2 - (s_image->num_cols - 1); 414 415 /* do the rotation transform */ 416 if (ctx->rot_mode & IPU_ROT_BIT_90) { 417 dst_col = -src_row; 418 dst_row = src_col; 419 } else { 420 dst_col = src_col; 421 dst_row = src_row; 422 } 423 424 /* apply flip */ 425 if (ctx->rot_mode & IPU_ROT_BIT_HFLIP) 426 dst_col = -dst_col; 427 if (ctx->rot_mode & IPU_ROT_BIT_VFLIP) 428 dst_row = -dst_row; 429 430 dev_dbg(priv->ipu->dev, "task %u: ctx %p: [%d,%d] --> [%d,%d]\n", 431 chan->ic_task, ctx, src_col, src_row, dst_col, dst_row); 432 433 /* 434 * finally translate dest row,col using an origin in upper 435 * left of d_image 436 */ 437 dst_row += d_image->num_rows - 1; 438 dst_col += d_image->num_cols - 1; 439 dst_row /= 2; 440 dst_col /= 2; 441 442 return dst_row * d_image->num_cols + dst_col; 443 } 444 445 /* 446 * Fill the out_tile_map[] with transformed destination tile indeces. 447 */ 448 static void calc_out_tile_map(struct ipu_image_convert_ctx *ctx) 449 { 450 struct ipu_image_convert_image *s_image = &ctx->in; 451 unsigned int row, col, tile = 0; 452 453 for (row = 0; row < s_image->num_rows; row++) { 454 for (col = 0; col < s_image->num_cols; col++) { 455 ctx->out_tile_map[tile] = 456 transform_tile_index(ctx, row, col); 457 tile++; 458 } 459 } 460 } 461 462 static int calc_tile_offsets_planar(struct ipu_image_convert_ctx *ctx, 463 struct ipu_image_convert_image *image) 464 { 465 struct ipu_image_convert_chan *chan = ctx->chan; 466 struct ipu_image_convert_priv *priv = chan->priv; 467 const struct ipu_image_pixfmt *fmt = image->fmt; 468 unsigned int row, col, tile = 0; 469 u32 H, w, h, y_stride, uv_stride; 470 u32 uv_row_off, uv_col_off, uv_off, u_off, v_off, tmp; 471 u32 y_row_off, y_col_off, y_off; 472 u32 y_size, uv_size; 473 474 /* setup some convenience vars */ 475 H = image->base.pix.height; 476 477 y_stride = image->stride; 478 uv_stride = y_stride / fmt->uv_width_dec; 479 if (fmt->uv_packed) 480 uv_stride *= 2; 481 482 y_size = H * y_stride; 483 uv_size = y_size / (fmt->uv_width_dec * fmt->uv_height_dec); 484 485 for (row = 0; row < image->num_rows; row++) { 486 w = image->tile[tile].width; 487 h = image->tile[tile].height; 488 y_row_off = row * h * y_stride; 489 uv_row_off = (row * h * uv_stride) / fmt->uv_height_dec; 490 491 for (col = 0; col < image->num_cols; col++) { 492 y_col_off = col * w; 493 uv_col_off = y_col_off / fmt->uv_width_dec; 494 if (fmt->uv_packed) 495 uv_col_off *= 2; 496 497 y_off = y_row_off + y_col_off; 498 uv_off = uv_row_off + uv_col_off; 499 500 u_off = y_size - y_off + uv_off; 501 v_off = (fmt->uv_packed) ? 0 : u_off + uv_size; 502 if (fmt->uv_swapped) { 503 tmp = u_off; 504 u_off = v_off; 505 v_off = tmp; 506 } 507 508 image->tile[tile].offset = y_off; 509 image->tile[tile].u_off = u_off; 510 image->tile[tile++].v_off = v_off; 511 512 if ((y_off & 0x7) || (u_off & 0x7) || (v_off & 0x7)) { 513 dev_err(priv->ipu->dev, 514 "task %u: ctx %p: %s@[%d,%d]: " 515 "y_off %08x, u_off %08x, v_off %08x\n", 516 chan->ic_task, ctx, 517 image->type == IMAGE_CONVERT_IN ? 518 "Input" : "Output", row, col, 519 y_off, u_off, v_off); 520 return -EINVAL; 521 } 522 } 523 } 524 525 return 0; 526 } 527 528 static int calc_tile_offsets_packed(struct ipu_image_convert_ctx *ctx, 529 struct ipu_image_convert_image *image) 530 { 531 struct ipu_image_convert_chan *chan = ctx->chan; 532 struct ipu_image_convert_priv *priv = chan->priv; 533 const struct ipu_image_pixfmt *fmt = image->fmt; 534 unsigned int row, col, tile = 0; 535 u32 w, h, bpp, stride, offset; 536 u32 row_off, col_off; 537 538 /* setup some convenience vars */ 539 stride = image->stride; 540 bpp = fmt->bpp; 541 542 for (row = 0; row < image->num_rows; row++) { 543 w = image->tile[tile].width; 544 h = image->tile[tile].height; 545 row_off = row * h * stride; 546 547 for (col = 0; col < image->num_cols; col++) { 548 col_off = (col * w * bpp) >> 3; 549 550 offset = row_off + col_off; 551 552 image->tile[tile].offset = offset; 553 image->tile[tile].u_off = 0; 554 image->tile[tile++].v_off = 0; 555 556 if (offset & 0x7) { 557 dev_err(priv->ipu->dev, 558 "task %u: ctx %p: %s@[%d,%d]: " 559 "phys %08x\n", 560 chan->ic_task, ctx, 561 image->type == IMAGE_CONVERT_IN ? 562 "Input" : "Output", row, col, 563 row_off + col_off); 564 return -EINVAL; 565 } 566 } 567 } 568 569 return 0; 570 } 571 572 static int calc_tile_offsets(struct ipu_image_convert_ctx *ctx, 573 struct ipu_image_convert_image *image) 574 { 575 if (image->fmt->planar) 576 return calc_tile_offsets_planar(ctx, image); 577 578 return calc_tile_offsets_packed(ctx, image); 579 } 580 581 /* 582 * return the number of runs in given queue (pending_q or done_q) 583 * for this context. hold irqlock when calling. 584 */ 585 static int get_run_count(struct ipu_image_convert_ctx *ctx, 586 struct list_head *q) 587 { 588 struct ipu_image_convert_run *run; 589 int count = 0; 590 591 lockdep_assert_held(&ctx->chan->irqlock); 592 593 list_for_each_entry(run, q, list) { 594 if (run->ctx == ctx) 595 count++; 596 } 597 598 return count; 599 } 600 601 static void convert_stop(struct ipu_image_convert_run *run) 602 { 603 struct ipu_image_convert_ctx *ctx = run->ctx; 604 struct ipu_image_convert_chan *chan = ctx->chan; 605 struct ipu_image_convert_priv *priv = chan->priv; 606 607 dev_dbg(priv->ipu->dev, "%s: task %u: stopping ctx %p run %p\n", 608 __func__, chan->ic_task, ctx, run); 609 610 /* disable IC tasks and the channels */ 611 ipu_ic_task_disable(chan->ic); 612 ipu_idmac_disable_channel(chan->in_chan); 613 ipu_idmac_disable_channel(chan->out_chan); 614 615 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 616 ipu_idmac_disable_channel(chan->rotation_in_chan); 617 ipu_idmac_disable_channel(chan->rotation_out_chan); 618 ipu_idmac_unlink(chan->out_chan, chan->rotation_in_chan); 619 } 620 621 ipu_ic_disable(chan->ic); 622 } 623 624 static void init_idmac_channel(struct ipu_image_convert_ctx *ctx, 625 struct ipuv3_channel *channel, 626 struct ipu_image_convert_image *image, 627 enum ipu_rotate_mode rot_mode, 628 bool rot_swap_width_height) 629 { 630 struct ipu_image_convert_chan *chan = ctx->chan; 631 unsigned int burst_size; 632 u32 width, height, stride; 633 dma_addr_t addr0, addr1 = 0; 634 struct ipu_image tile_image; 635 unsigned int tile_idx[2]; 636 637 if (image->type == IMAGE_CONVERT_OUT) { 638 tile_idx[0] = ctx->out_tile_map[0]; 639 tile_idx[1] = ctx->out_tile_map[1]; 640 } else { 641 tile_idx[0] = 0; 642 tile_idx[1] = 1; 643 } 644 645 if (rot_swap_width_height) { 646 width = image->tile[0].height; 647 height = image->tile[0].width; 648 stride = image->tile[0].rot_stride; 649 addr0 = ctx->rot_intermediate[0].phys; 650 if (ctx->double_buffering) 651 addr1 = ctx->rot_intermediate[1].phys; 652 } else { 653 width = image->tile[0].width; 654 height = image->tile[0].height; 655 stride = image->stride; 656 addr0 = image->base.phys0 + 657 image->tile[tile_idx[0]].offset; 658 if (ctx->double_buffering) 659 addr1 = image->base.phys0 + 660 image->tile[tile_idx[1]].offset; 661 } 662 663 ipu_cpmem_zero(channel); 664 665 memset(&tile_image, 0, sizeof(tile_image)); 666 tile_image.pix.width = tile_image.rect.width = width; 667 tile_image.pix.height = tile_image.rect.height = height; 668 tile_image.pix.bytesperline = stride; 669 tile_image.pix.pixelformat = image->fmt->fourcc; 670 tile_image.phys0 = addr0; 671 tile_image.phys1 = addr1; 672 if (image->fmt->planar && !rot_swap_width_height) { 673 tile_image.u_offset = image->tile[tile_idx[0]].u_off; 674 tile_image.v_offset = image->tile[tile_idx[0]].v_off; 675 } 676 677 ipu_cpmem_set_image(channel, &tile_image); 678 679 if (rot_mode) 680 ipu_cpmem_set_rotation(channel, rot_mode); 681 682 if (channel == chan->rotation_in_chan || 683 channel == chan->rotation_out_chan) { 684 burst_size = 8; 685 ipu_cpmem_set_block_mode(channel); 686 } else 687 burst_size = (width % 16) ? 8 : 16; 688 689 ipu_cpmem_set_burstsize(channel, burst_size); 690 691 ipu_ic_task_idma_init(chan->ic, channel, width, height, 692 burst_size, rot_mode); 693 694 /* 695 * Setting a non-zero AXI ID collides with the PRG AXI snooping, so 696 * only do this when there is no PRG present. 697 */ 698 if (!channel->ipu->prg_priv) 699 ipu_cpmem_set_axi_id(channel, 1); 700 701 ipu_idmac_set_double_buffer(channel, ctx->double_buffering); 702 } 703 704 static int convert_start(struct ipu_image_convert_run *run) 705 { 706 struct ipu_image_convert_ctx *ctx = run->ctx; 707 struct ipu_image_convert_chan *chan = ctx->chan; 708 struct ipu_image_convert_priv *priv = chan->priv; 709 struct ipu_image_convert_image *s_image = &ctx->in; 710 struct ipu_image_convert_image *d_image = &ctx->out; 711 enum ipu_color_space src_cs, dest_cs; 712 unsigned int dest_width, dest_height; 713 int ret; 714 715 dev_dbg(priv->ipu->dev, "%s: task %u: starting ctx %p run %p\n", 716 __func__, chan->ic_task, ctx, run); 717 718 src_cs = ipu_pixelformat_to_colorspace(s_image->fmt->fourcc); 719 dest_cs = ipu_pixelformat_to_colorspace(d_image->fmt->fourcc); 720 721 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 722 /* swap width/height for resizer */ 723 dest_width = d_image->tile[0].height; 724 dest_height = d_image->tile[0].width; 725 } else { 726 dest_width = d_image->tile[0].width; 727 dest_height = d_image->tile[0].height; 728 } 729 730 /* setup the IC resizer and CSC */ 731 ret = ipu_ic_task_init(chan->ic, 732 s_image->tile[0].width, 733 s_image->tile[0].height, 734 dest_width, 735 dest_height, 736 src_cs, dest_cs); 737 if (ret) { 738 dev_err(priv->ipu->dev, "ipu_ic_task_init failed, %d\n", ret); 739 return ret; 740 } 741 742 /* init the source MEM-->IC PP IDMAC channel */ 743 init_idmac_channel(ctx, chan->in_chan, s_image, 744 IPU_ROTATE_NONE, false); 745 746 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 747 /* init the IC PP-->MEM IDMAC channel */ 748 init_idmac_channel(ctx, chan->out_chan, d_image, 749 IPU_ROTATE_NONE, true); 750 751 /* init the MEM-->IC PP ROT IDMAC channel */ 752 init_idmac_channel(ctx, chan->rotation_in_chan, d_image, 753 ctx->rot_mode, true); 754 755 /* init the destination IC PP ROT-->MEM IDMAC channel */ 756 init_idmac_channel(ctx, chan->rotation_out_chan, d_image, 757 IPU_ROTATE_NONE, false); 758 759 /* now link IC PP-->MEM to MEM-->IC PP ROT */ 760 ipu_idmac_link(chan->out_chan, chan->rotation_in_chan); 761 } else { 762 /* init the destination IC PP-->MEM IDMAC channel */ 763 init_idmac_channel(ctx, chan->out_chan, d_image, 764 ctx->rot_mode, false); 765 } 766 767 /* enable the IC */ 768 ipu_ic_enable(chan->ic); 769 770 /* set buffers ready */ 771 ipu_idmac_select_buffer(chan->in_chan, 0); 772 ipu_idmac_select_buffer(chan->out_chan, 0); 773 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 774 ipu_idmac_select_buffer(chan->rotation_out_chan, 0); 775 if (ctx->double_buffering) { 776 ipu_idmac_select_buffer(chan->in_chan, 1); 777 ipu_idmac_select_buffer(chan->out_chan, 1); 778 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 779 ipu_idmac_select_buffer(chan->rotation_out_chan, 1); 780 } 781 782 /* enable the channels! */ 783 ipu_idmac_enable_channel(chan->in_chan); 784 ipu_idmac_enable_channel(chan->out_chan); 785 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 786 ipu_idmac_enable_channel(chan->rotation_in_chan); 787 ipu_idmac_enable_channel(chan->rotation_out_chan); 788 } 789 790 ipu_ic_task_enable(chan->ic); 791 792 ipu_cpmem_dump(chan->in_chan); 793 ipu_cpmem_dump(chan->out_chan); 794 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 795 ipu_cpmem_dump(chan->rotation_in_chan); 796 ipu_cpmem_dump(chan->rotation_out_chan); 797 } 798 799 ipu_dump(priv->ipu); 800 801 return 0; 802 } 803 804 /* hold irqlock when calling */ 805 static int do_run(struct ipu_image_convert_run *run) 806 { 807 struct ipu_image_convert_ctx *ctx = run->ctx; 808 struct ipu_image_convert_chan *chan = ctx->chan; 809 810 lockdep_assert_held(&chan->irqlock); 811 812 ctx->in.base.phys0 = run->in_phys; 813 ctx->out.base.phys0 = run->out_phys; 814 815 ctx->cur_buf_num = 0; 816 ctx->next_tile = 1; 817 818 /* remove run from pending_q and set as current */ 819 list_del(&run->list); 820 chan->current_run = run; 821 822 return convert_start(run); 823 } 824 825 /* hold irqlock when calling */ 826 static void run_next(struct ipu_image_convert_chan *chan) 827 { 828 struct ipu_image_convert_priv *priv = chan->priv; 829 struct ipu_image_convert_run *run, *tmp; 830 int ret; 831 832 lockdep_assert_held(&chan->irqlock); 833 834 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 835 /* skip contexts that are aborting */ 836 if (run->ctx->aborting) { 837 dev_dbg(priv->ipu->dev, 838 "%s: task %u: skipping aborting ctx %p run %p\n", 839 __func__, chan->ic_task, run->ctx, run); 840 continue; 841 } 842 843 ret = do_run(run); 844 if (!ret) 845 break; 846 847 /* 848 * something went wrong with start, add the run 849 * to done q and continue to the next run in the 850 * pending q. 851 */ 852 run->status = ret; 853 list_add_tail(&run->list, &chan->done_q); 854 chan->current_run = NULL; 855 } 856 } 857 858 static void empty_done_q(struct ipu_image_convert_chan *chan) 859 { 860 struct ipu_image_convert_priv *priv = chan->priv; 861 struct ipu_image_convert_run *run; 862 unsigned long flags; 863 864 spin_lock_irqsave(&chan->irqlock, flags); 865 866 while (!list_empty(&chan->done_q)) { 867 run = list_entry(chan->done_q.next, 868 struct ipu_image_convert_run, 869 list); 870 871 list_del(&run->list); 872 873 dev_dbg(priv->ipu->dev, 874 "%s: task %u: completing ctx %p run %p with %d\n", 875 __func__, chan->ic_task, run->ctx, run, run->status); 876 877 /* call the completion callback and free the run */ 878 spin_unlock_irqrestore(&chan->irqlock, flags); 879 run->ctx->complete(run, run->ctx->complete_context); 880 spin_lock_irqsave(&chan->irqlock, flags); 881 } 882 883 spin_unlock_irqrestore(&chan->irqlock, flags); 884 } 885 886 /* 887 * the bottom half thread clears out the done_q, calling the 888 * completion handler for each. 889 */ 890 static irqreturn_t do_bh(int irq, void *dev_id) 891 { 892 struct ipu_image_convert_chan *chan = dev_id; 893 struct ipu_image_convert_priv *priv = chan->priv; 894 struct ipu_image_convert_ctx *ctx; 895 unsigned long flags; 896 897 dev_dbg(priv->ipu->dev, "%s: task %u: enter\n", __func__, 898 chan->ic_task); 899 900 empty_done_q(chan); 901 902 spin_lock_irqsave(&chan->irqlock, flags); 903 904 /* 905 * the done_q is cleared out, signal any contexts 906 * that are aborting that abort can complete. 907 */ 908 list_for_each_entry(ctx, &chan->ctx_list, list) { 909 if (ctx->aborting) { 910 dev_dbg(priv->ipu->dev, 911 "%s: task %u: signaling abort for ctx %p\n", 912 __func__, chan->ic_task, ctx); 913 complete_all(&ctx->aborted); 914 } 915 } 916 917 spin_unlock_irqrestore(&chan->irqlock, flags); 918 919 dev_dbg(priv->ipu->dev, "%s: task %u: exit\n", __func__, 920 chan->ic_task); 921 922 return IRQ_HANDLED; 923 } 924 925 /* hold irqlock when calling */ 926 static irqreturn_t do_irq(struct ipu_image_convert_run *run) 927 { 928 struct ipu_image_convert_ctx *ctx = run->ctx; 929 struct ipu_image_convert_chan *chan = ctx->chan; 930 struct ipu_image_tile *src_tile, *dst_tile; 931 struct ipu_image_convert_image *s_image = &ctx->in; 932 struct ipu_image_convert_image *d_image = &ctx->out; 933 struct ipuv3_channel *outch; 934 unsigned int dst_idx; 935 936 lockdep_assert_held(&chan->irqlock); 937 938 outch = ipu_rot_mode_is_irt(ctx->rot_mode) ? 939 chan->rotation_out_chan : chan->out_chan; 940 941 /* 942 * It is difficult to stop the channel DMA before the channels 943 * enter the paused state. Without double-buffering the channels 944 * are always in a paused state when the EOF irq occurs, so it 945 * is safe to stop the channels now. For double-buffering we 946 * just ignore the abort until the operation completes, when it 947 * is safe to shut down. 948 */ 949 if (ctx->aborting && !ctx->double_buffering) { 950 convert_stop(run); 951 run->status = -EIO; 952 goto done; 953 } 954 955 if (ctx->next_tile == ctx->num_tiles) { 956 /* 957 * the conversion is complete 958 */ 959 convert_stop(run); 960 run->status = 0; 961 goto done; 962 } 963 964 /* 965 * not done, place the next tile buffers. 966 */ 967 if (!ctx->double_buffering) { 968 969 src_tile = &s_image->tile[ctx->next_tile]; 970 dst_idx = ctx->out_tile_map[ctx->next_tile]; 971 dst_tile = &d_image->tile[dst_idx]; 972 973 ipu_cpmem_set_buffer(chan->in_chan, 0, 974 s_image->base.phys0 + src_tile->offset); 975 ipu_cpmem_set_buffer(outch, 0, 976 d_image->base.phys0 + dst_tile->offset); 977 if (s_image->fmt->planar) 978 ipu_cpmem_set_uv_offset(chan->in_chan, 979 src_tile->u_off, 980 src_tile->v_off); 981 if (d_image->fmt->planar) 982 ipu_cpmem_set_uv_offset(outch, 983 dst_tile->u_off, 984 dst_tile->v_off); 985 986 ipu_idmac_select_buffer(chan->in_chan, 0); 987 ipu_idmac_select_buffer(outch, 0); 988 989 } else if (ctx->next_tile < ctx->num_tiles - 1) { 990 991 src_tile = &s_image->tile[ctx->next_tile + 1]; 992 dst_idx = ctx->out_tile_map[ctx->next_tile + 1]; 993 dst_tile = &d_image->tile[dst_idx]; 994 995 ipu_cpmem_set_buffer(chan->in_chan, ctx->cur_buf_num, 996 s_image->base.phys0 + src_tile->offset); 997 ipu_cpmem_set_buffer(outch, ctx->cur_buf_num, 998 d_image->base.phys0 + dst_tile->offset); 999 1000 ipu_idmac_select_buffer(chan->in_chan, ctx->cur_buf_num); 1001 ipu_idmac_select_buffer(outch, ctx->cur_buf_num); 1002 1003 ctx->cur_buf_num ^= 1; 1004 } 1005 1006 ctx->next_tile++; 1007 return IRQ_HANDLED; 1008 done: 1009 list_add_tail(&run->list, &chan->done_q); 1010 chan->current_run = NULL; 1011 run_next(chan); 1012 return IRQ_WAKE_THREAD; 1013 } 1014 1015 static irqreturn_t norotate_irq(int irq, void *data) 1016 { 1017 struct ipu_image_convert_chan *chan = data; 1018 struct ipu_image_convert_ctx *ctx; 1019 struct ipu_image_convert_run *run; 1020 unsigned long flags; 1021 irqreturn_t ret; 1022 1023 spin_lock_irqsave(&chan->irqlock, flags); 1024 1025 /* get current run and its context */ 1026 run = chan->current_run; 1027 if (!run) { 1028 ret = IRQ_NONE; 1029 goto out; 1030 } 1031 1032 ctx = run->ctx; 1033 1034 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1035 /* this is a rotation operation, just ignore */ 1036 spin_unlock_irqrestore(&chan->irqlock, flags); 1037 return IRQ_HANDLED; 1038 } 1039 1040 ret = do_irq(run); 1041 out: 1042 spin_unlock_irqrestore(&chan->irqlock, flags); 1043 return ret; 1044 } 1045 1046 static irqreturn_t rotate_irq(int irq, void *data) 1047 { 1048 struct ipu_image_convert_chan *chan = data; 1049 struct ipu_image_convert_priv *priv = chan->priv; 1050 struct ipu_image_convert_ctx *ctx; 1051 struct ipu_image_convert_run *run; 1052 unsigned long flags; 1053 irqreturn_t ret; 1054 1055 spin_lock_irqsave(&chan->irqlock, flags); 1056 1057 /* get current run and its context */ 1058 run = chan->current_run; 1059 if (!run) { 1060 ret = IRQ_NONE; 1061 goto out; 1062 } 1063 1064 ctx = run->ctx; 1065 1066 if (!ipu_rot_mode_is_irt(ctx->rot_mode)) { 1067 /* this was NOT a rotation operation, shouldn't happen */ 1068 dev_err(priv->ipu->dev, "Unexpected rotation interrupt\n"); 1069 spin_unlock_irqrestore(&chan->irqlock, flags); 1070 return IRQ_HANDLED; 1071 } 1072 1073 ret = do_irq(run); 1074 out: 1075 spin_unlock_irqrestore(&chan->irqlock, flags); 1076 return ret; 1077 } 1078 1079 /* 1080 * try to force the completion of runs for this ctx. Called when 1081 * abort wait times out in ipu_image_convert_abort(). 1082 */ 1083 static void force_abort(struct ipu_image_convert_ctx *ctx) 1084 { 1085 struct ipu_image_convert_chan *chan = ctx->chan; 1086 struct ipu_image_convert_run *run; 1087 unsigned long flags; 1088 1089 spin_lock_irqsave(&chan->irqlock, flags); 1090 1091 run = chan->current_run; 1092 if (run && run->ctx == ctx) { 1093 convert_stop(run); 1094 run->status = -EIO; 1095 list_add_tail(&run->list, &chan->done_q); 1096 chan->current_run = NULL; 1097 run_next(chan); 1098 } 1099 1100 spin_unlock_irqrestore(&chan->irqlock, flags); 1101 1102 empty_done_q(chan); 1103 } 1104 1105 static void release_ipu_resources(struct ipu_image_convert_chan *chan) 1106 { 1107 if (chan->out_eof_irq >= 0) 1108 free_irq(chan->out_eof_irq, chan); 1109 if (chan->rot_out_eof_irq >= 0) 1110 free_irq(chan->rot_out_eof_irq, chan); 1111 1112 if (!IS_ERR_OR_NULL(chan->in_chan)) 1113 ipu_idmac_put(chan->in_chan); 1114 if (!IS_ERR_OR_NULL(chan->out_chan)) 1115 ipu_idmac_put(chan->out_chan); 1116 if (!IS_ERR_OR_NULL(chan->rotation_in_chan)) 1117 ipu_idmac_put(chan->rotation_in_chan); 1118 if (!IS_ERR_OR_NULL(chan->rotation_out_chan)) 1119 ipu_idmac_put(chan->rotation_out_chan); 1120 if (!IS_ERR_OR_NULL(chan->ic)) 1121 ipu_ic_put(chan->ic); 1122 1123 chan->in_chan = chan->out_chan = chan->rotation_in_chan = 1124 chan->rotation_out_chan = NULL; 1125 chan->out_eof_irq = chan->rot_out_eof_irq = -1; 1126 } 1127 1128 static int get_ipu_resources(struct ipu_image_convert_chan *chan) 1129 { 1130 const struct ipu_image_convert_dma_chan *dma = chan->dma_ch; 1131 struct ipu_image_convert_priv *priv = chan->priv; 1132 int ret; 1133 1134 /* get IC */ 1135 chan->ic = ipu_ic_get(priv->ipu, chan->ic_task); 1136 if (IS_ERR(chan->ic)) { 1137 dev_err(priv->ipu->dev, "could not acquire IC\n"); 1138 ret = PTR_ERR(chan->ic); 1139 goto err; 1140 } 1141 1142 /* get IDMAC channels */ 1143 chan->in_chan = ipu_idmac_get(priv->ipu, dma->in); 1144 chan->out_chan = ipu_idmac_get(priv->ipu, dma->out); 1145 if (IS_ERR(chan->in_chan) || IS_ERR(chan->out_chan)) { 1146 dev_err(priv->ipu->dev, "could not acquire idmac channels\n"); 1147 ret = -EBUSY; 1148 goto err; 1149 } 1150 1151 chan->rotation_in_chan = ipu_idmac_get(priv->ipu, dma->rot_in); 1152 chan->rotation_out_chan = ipu_idmac_get(priv->ipu, dma->rot_out); 1153 if (IS_ERR(chan->rotation_in_chan) || IS_ERR(chan->rotation_out_chan)) { 1154 dev_err(priv->ipu->dev, 1155 "could not acquire idmac rotation channels\n"); 1156 ret = -EBUSY; 1157 goto err; 1158 } 1159 1160 /* acquire the EOF interrupts */ 1161 chan->out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1162 chan->out_chan, 1163 IPU_IRQ_EOF); 1164 1165 ret = request_threaded_irq(chan->out_eof_irq, norotate_irq, do_bh, 1166 0, "ipu-ic", chan); 1167 if (ret < 0) { 1168 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1169 chan->out_eof_irq); 1170 chan->out_eof_irq = -1; 1171 goto err; 1172 } 1173 1174 chan->rot_out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1175 chan->rotation_out_chan, 1176 IPU_IRQ_EOF); 1177 1178 ret = request_threaded_irq(chan->rot_out_eof_irq, rotate_irq, do_bh, 1179 0, "ipu-ic", chan); 1180 if (ret < 0) { 1181 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1182 chan->rot_out_eof_irq); 1183 chan->rot_out_eof_irq = -1; 1184 goto err; 1185 } 1186 1187 return 0; 1188 err: 1189 release_ipu_resources(chan); 1190 return ret; 1191 } 1192 1193 static int fill_image(struct ipu_image_convert_ctx *ctx, 1194 struct ipu_image_convert_image *ic_image, 1195 struct ipu_image *image, 1196 enum ipu_image_convert_type type) 1197 { 1198 struct ipu_image_convert_priv *priv = ctx->chan->priv; 1199 1200 ic_image->base = *image; 1201 ic_image->type = type; 1202 1203 ic_image->fmt = get_format(image->pix.pixelformat); 1204 if (!ic_image->fmt) { 1205 dev_err(priv->ipu->dev, "pixelformat not supported for %s\n", 1206 type == IMAGE_CONVERT_OUT ? "Output" : "Input"); 1207 return -EINVAL; 1208 } 1209 1210 if (ic_image->fmt->planar) 1211 ic_image->stride = ic_image->base.pix.width; 1212 else 1213 ic_image->stride = ic_image->base.pix.bytesperline; 1214 1215 calc_tile_dimensions(ctx, ic_image); 1216 1217 return calc_tile_offsets(ctx, ic_image); 1218 } 1219 1220 /* borrowed from drivers/media/v4l2-core/v4l2-common.c */ 1221 static unsigned int clamp_align(unsigned int x, unsigned int min, 1222 unsigned int max, unsigned int align) 1223 { 1224 /* Bits that must be zero to be aligned */ 1225 unsigned int mask = ~((1 << align) - 1); 1226 1227 /* Clamp to aligned min and max */ 1228 x = clamp(x, (min + ~mask) & mask, max & mask); 1229 1230 /* Round to nearest aligned value */ 1231 if (align) 1232 x = (x + (1 << (align - 1))) & mask; 1233 1234 return x; 1235 } 1236 1237 /* 1238 * We have to adjust the tile width such that the tile physaddrs and 1239 * U and V plane offsets are multiples of 8 bytes as required by 1240 * the IPU DMA Controller. For the planar formats, this corresponds 1241 * to a pixel alignment of 16 (but use a more formal equation since 1242 * the variables are available). For all the packed formats, 8 is 1243 * good enough. 1244 */ 1245 static inline u32 tile_width_align(const struct ipu_image_pixfmt *fmt) 1246 { 1247 return fmt->planar ? 8 * fmt->uv_width_dec : 8; 1248 } 1249 1250 /* 1251 * For tile height alignment, we have to ensure that the output tile 1252 * heights are multiples of 8 lines if the IRT is required by the 1253 * given rotation mode (the IRT performs rotations on 8x8 blocks 1254 * at a time). If the IRT is not used, or for input image tiles, 1255 * 2 lines are good enough. 1256 */ 1257 static inline u32 tile_height_align(enum ipu_image_convert_type type, 1258 enum ipu_rotate_mode rot_mode) 1259 { 1260 return (type == IMAGE_CONVERT_OUT && 1261 ipu_rot_mode_is_irt(rot_mode)) ? 8 : 2; 1262 } 1263 1264 /* Adjusts input/output images to IPU restrictions */ 1265 void ipu_image_convert_adjust(struct ipu_image *in, struct ipu_image *out, 1266 enum ipu_rotate_mode rot_mode) 1267 { 1268 const struct ipu_image_pixfmt *infmt, *outfmt; 1269 unsigned int num_in_rows, num_in_cols; 1270 unsigned int num_out_rows, num_out_cols; 1271 u32 w_align, h_align; 1272 1273 infmt = get_format(in->pix.pixelformat); 1274 outfmt = get_format(out->pix.pixelformat); 1275 1276 /* set some default pixel formats if needed */ 1277 if (!infmt) { 1278 in->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1279 infmt = get_format(V4L2_PIX_FMT_RGB24); 1280 } 1281 if (!outfmt) { 1282 out->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1283 outfmt = get_format(V4L2_PIX_FMT_RGB24); 1284 } 1285 1286 /* image converter does not handle fields */ 1287 in->pix.field = out->pix.field = V4L2_FIELD_NONE; 1288 1289 /* resizer cannot downsize more than 4:1 */ 1290 if (ipu_rot_mode_is_irt(rot_mode)) { 1291 out->pix.height = max_t(__u32, out->pix.height, 1292 in->pix.width / 4); 1293 out->pix.width = max_t(__u32, out->pix.width, 1294 in->pix.height / 4); 1295 } else { 1296 out->pix.width = max_t(__u32, out->pix.width, 1297 in->pix.width / 4); 1298 out->pix.height = max_t(__u32, out->pix.height, 1299 in->pix.height / 4); 1300 } 1301 1302 /* get tiling rows/cols from output format */ 1303 num_out_rows = num_stripes(out->pix.height); 1304 num_out_cols = num_stripes(out->pix.width); 1305 if (ipu_rot_mode_is_irt(rot_mode)) { 1306 num_in_rows = num_out_cols; 1307 num_in_cols = num_out_rows; 1308 } else { 1309 num_in_rows = num_out_rows; 1310 num_in_cols = num_out_cols; 1311 } 1312 1313 /* align input width/height */ 1314 w_align = ilog2(tile_width_align(infmt) * num_in_cols); 1315 h_align = ilog2(tile_height_align(IMAGE_CONVERT_IN, rot_mode) * 1316 num_in_rows); 1317 in->pix.width = clamp_align(in->pix.width, MIN_W, MAX_W, w_align); 1318 in->pix.height = clamp_align(in->pix.height, MIN_H, MAX_H, h_align); 1319 1320 /* align output width/height */ 1321 w_align = ilog2(tile_width_align(outfmt) * num_out_cols); 1322 h_align = ilog2(tile_height_align(IMAGE_CONVERT_OUT, rot_mode) * 1323 num_out_rows); 1324 out->pix.width = clamp_align(out->pix.width, MIN_W, MAX_W, w_align); 1325 out->pix.height = clamp_align(out->pix.height, MIN_H, MAX_H, h_align); 1326 1327 /* set input/output strides and image sizes */ 1328 in->pix.bytesperline = (in->pix.width * infmt->bpp) >> 3; 1329 in->pix.sizeimage = in->pix.height * in->pix.bytesperline; 1330 out->pix.bytesperline = (out->pix.width * outfmt->bpp) >> 3; 1331 out->pix.sizeimage = out->pix.height * out->pix.bytesperline; 1332 } 1333 EXPORT_SYMBOL_GPL(ipu_image_convert_adjust); 1334 1335 /* 1336 * this is used by ipu_image_convert_prepare() to verify set input and 1337 * output images are valid before starting the conversion. Clients can 1338 * also call it before calling ipu_image_convert_prepare(). 1339 */ 1340 int ipu_image_convert_verify(struct ipu_image *in, struct ipu_image *out, 1341 enum ipu_rotate_mode rot_mode) 1342 { 1343 struct ipu_image testin, testout; 1344 1345 testin = *in; 1346 testout = *out; 1347 1348 ipu_image_convert_adjust(&testin, &testout, rot_mode); 1349 1350 if (testin.pix.width != in->pix.width || 1351 testin.pix.height != in->pix.height || 1352 testout.pix.width != out->pix.width || 1353 testout.pix.height != out->pix.height) 1354 return -EINVAL; 1355 1356 return 0; 1357 } 1358 EXPORT_SYMBOL_GPL(ipu_image_convert_verify); 1359 1360 /* 1361 * Call ipu_image_convert_prepare() to prepare for the conversion of 1362 * given images and rotation mode. Returns a new conversion context. 1363 */ 1364 struct ipu_image_convert_ctx * 1365 ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1366 struct ipu_image *in, struct ipu_image *out, 1367 enum ipu_rotate_mode rot_mode, 1368 ipu_image_convert_cb_t complete, 1369 void *complete_context) 1370 { 1371 struct ipu_image_convert_priv *priv = ipu->image_convert_priv; 1372 struct ipu_image_convert_image *s_image, *d_image; 1373 struct ipu_image_convert_chan *chan; 1374 struct ipu_image_convert_ctx *ctx; 1375 unsigned long flags; 1376 bool get_res; 1377 int ret; 1378 1379 if (!in || !out || !complete || 1380 (ic_task != IC_TASK_VIEWFINDER && 1381 ic_task != IC_TASK_POST_PROCESSOR)) 1382 return ERR_PTR(-EINVAL); 1383 1384 /* verify the in/out images before continuing */ 1385 ret = ipu_image_convert_verify(in, out, rot_mode); 1386 if (ret) { 1387 dev_err(priv->ipu->dev, "%s: in/out formats invalid\n", 1388 __func__); 1389 return ERR_PTR(ret); 1390 } 1391 1392 chan = &priv->chan[ic_task]; 1393 1394 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 1395 if (!ctx) 1396 return ERR_PTR(-ENOMEM); 1397 1398 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p\n", __func__, 1399 chan->ic_task, ctx); 1400 1401 ctx->chan = chan; 1402 init_completion(&ctx->aborted); 1403 1404 s_image = &ctx->in; 1405 d_image = &ctx->out; 1406 1407 /* set tiling and rotation */ 1408 d_image->num_rows = num_stripes(out->pix.height); 1409 d_image->num_cols = num_stripes(out->pix.width); 1410 if (ipu_rot_mode_is_irt(rot_mode)) { 1411 s_image->num_rows = d_image->num_cols; 1412 s_image->num_cols = d_image->num_rows; 1413 } else { 1414 s_image->num_rows = d_image->num_rows; 1415 s_image->num_cols = d_image->num_cols; 1416 } 1417 1418 ctx->num_tiles = d_image->num_cols * d_image->num_rows; 1419 ctx->rot_mode = rot_mode; 1420 1421 ret = fill_image(ctx, s_image, in, IMAGE_CONVERT_IN); 1422 if (ret) 1423 goto out_free; 1424 ret = fill_image(ctx, d_image, out, IMAGE_CONVERT_OUT); 1425 if (ret) 1426 goto out_free; 1427 1428 calc_out_tile_map(ctx); 1429 1430 dump_format(ctx, s_image); 1431 dump_format(ctx, d_image); 1432 1433 ctx->complete = complete; 1434 ctx->complete_context = complete_context; 1435 1436 /* 1437 * Can we use double-buffering for this operation? If there is 1438 * only one tile (the whole image can be converted in a single 1439 * operation) there's no point in using double-buffering. Also, 1440 * the IPU's IDMAC channels allow only a single U and V plane 1441 * offset shared between both buffers, but these offsets change 1442 * for every tile, and therefore would have to be updated for 1443 * each buffer which is not possible. So double-buffering is 1444 * impossible when either the source or destination images are 1445 * a planar format (YUV420, YUV422P, etc.). 1446 */ 1447 ctx->double_buffering = (ctx->num_tiles > 1 && 1448 !s_image->fmt->planar && 1449 !d_image->fmt->planar); 1450 1451 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1452 ret = alloc_dma_buf(priv, &ctx->rot_intermediate[0], 1453 d_image->tile[0].size); 1454 if (ret) 1455 goto out_free; 1456 if (ctx->double_buffering) { 1457 ret = alloc_dma_buf(priv, 1458 &ctx->rot_intermediate[1], 1459 d_image->tile[0].size); 1460 if (ret) 1461 goto out_free_dmabuf0; 1462 } 1463 } 1464 1465 spin_lock_irqsave(&chan->irqlock, flags); 1466 1467 get_res = list_empty(&chan->ctx_list); 1468 1469 list_add_tail(&ctx->list, &chan->ctx_list); 1470 1471 spin_unlock_irqrestore(&chan->irqlock, flags); 1472 1473 if (get_res) { 1474 ret = get_ipu_resources(chan); 1475 if (ret) 1476 goto out_free_dmabuf1; 1477 } 1478 1479 return ctx; 1480 1481 out_free_dmabuf1: 1482 free_dma_buf(priv, &ctx->rot_intermediate[1]); 1483 spin_lock_irqsave(&chan->irqlock, flags); 1484 list_del(&ctx->list); 1485 spin_unlock_irqrestore(&chan->irqlock, flags); 1486 out_free_dmabuf0: 1487 free_dma_buf(priv, &ctx->rot_intermediate[0]); 1488 out_free: 1489 kfree(ctx); 1490 return ERR_PTR(ret); 1491 } 1492 EXPORT_SYMBOL_GPL(ipu_image_convert_prepare); 1493 1494 /* 1495 * Carry out a single image conversion run. Only the physaddr's of the input 1496 * and output image buffers are needed. The conversion context must have 1497 * been created previously with ipu_image_convert_prepare(). 1498 */ 1499 int ipu_image_convert_queue(struct ipu_image_convert_run *run) 1500 { 1501 struct ipu_image_convert_chan *chan; 1502 struct ipu_image_convert_priv *priv; 1503 struct ipu_image_convert_ctx *ctx; 1504 unsigned long flags; 1505 int ret = 0; 1506 1507 if (!run || !run->ctx || !run->in_phys || !run->out_phys) 1508 return -EINVAL; 1509 1510 ctx = run->ctx; 1511 chan = ctx->chan; 1512 priv = chan->priv; 1513 1514 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p run %p\n", __func__, 1515 chan->ic_task, ctx, run); 1516 1517 INIT_LIST_HEAD(&run->list); 1518 1519 spin_lock_irqsave(&chan->irqlock, flags); 1520 1521 if (ctx->aborting) { 1522 ret = -EIO; 1523 goto unlock; 1524 } 1525 1526 list_add_tail(&run->list, &chan->pending_q); 1527 1528 if (!chan->current_run) { 1529 ret = do_run(run); 1530 if (ret) 1531 chan->current_run = NULL; 1532 } 1533 unlock: 1534 spin_unlock_irqrestore(&chan->irqlock, flags); 1535 return ret; 1536 } 1537 EXPORT_SYMBOL_GPL(ipu_image_convert_queue); 1538 1539 /* Abort any active or pending conversions for this context */ 1540 static void __ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 1541 { 1542 struct ipu_image_convert_chan *chan = ctx->chan; 1543 struct ipu_image_convert_priv *priv = chan->priv; 1544 struct ipu_image_convert_run *run, *active_run, *tmp; 1545 unsigned long flags; 1546 int run_count, ret; 1547 1548 spin_lock_irqsave(&chan->irqlock, flags); 1549 1550 /* move all remaining pending runs in this context to done_q */ 1551 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 1552 if (run->ctx != ctx) 1553 continue; 1554 run->status = -EIO; 1555 list_move_tail(&run->list, &chan->done_q); 1556 } 1557 1558 run_count = get_run_count(ctx, &chan->done_q); 1559 active_run = (chan->current_run && chan->current_run->ctx == ctx) ? 1560 chan->current_run : NULL; 1561 1562 if (active_run) 1563 reinit_completion(&ctx->aborted); 1564 1565 ctx->aborting = true; 1566 1567 spin_unlock_irqrestore(&chan->irqlock, flags); 1568 1569 if (!run_count && !active_run) { 1570 dev_dbg(priv->ipu->dev, 1571 "%s: task %u: no abort needed for ctx %p\n", 1572 __func__, chan->ic_task, ctx); 1573 return; 1574 } 1575 1576 if (!active_run) { 1577 empty_done_q(chan); 1578 return; 1579 } 1580 1581 dev_dbg(priv->ipu->dev, 1582 "%s: task %u: wait for completion: %d runs\n", 1583 __func__, chan->ic_task, run_count); 1584 1585 ret = wait_for_completion_timeout(&ctx->aborted, 1586 msecs_to_jiffies(10000)); 1587 if (ret == 0) { 1588 dev_warn(priv->ipu->dev, "%s: timeout\n", __func__); 1589 force_abort(ctx); 1590 } 1591 } 1592 1593 void ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 1594 { 1595 __ipu_image_convert_abort(ctx); 1596 ctx->aborting = false; 1597 } 1598 EXPORT_SYMBOL_GPL(ipu_image_convert_abort); 1599 1600 /* Unprepare image conversion context */ 1601 void ipu_image_convert_unprepare(struct ipu_image_convert_ctx *ctx) 1602 { 1603 struct ipu_image_convert_chan *chan = ctx->chan; 1604 struct ipu_image_convert_priv *priv = chan->priv; 1605 unsigned long flags; 1606 bool put_res; 1607 1608 /* make sure no runs are hanging around */ 1609 __ipu_image_convert_abort(ctx); 1610 1611 dev_dbg(priv->ipu->dev, "%s: task %u: removing ctx %p\n", __func__, 1612 chan->ic_task, ctx); 1613 1614 spin_lock_irqsave(&chan->irqlock, flags); 1615 1616 list_del(&ctx->list); 1617 1618 put_res = list_empty(&chan->ctx_list); 1619 1620 spin_unlock_irqrestore(&chan->irqlock, flags); 1621 1622 if (put_res) 1623 release_ipu_resources(chan); 1624 1625 free_dma_buf(priv, &ctx->rot_intermediate[1]); 1626 free_dma_buf(priv, &ctx->rot_intermediate[0]); 1627 1628 kfree(ctx); 1629 } 1630 EXPORT_SYMBOL_GPL(ipu_image_convert_unprepare); 1631 1632 /* 1633 * "Canned" asynchronous single image conversion. Allocates and returns 1634 * a new conversion run. On successful return the caller must free the 1635 * run and call ipu_image_convert_unprepare() after conversion completes. 1636 */ 1637 struct ipu_image_convert_run * 1638 ipu_image_convert(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1639 struct ipu_image *in, struct ipu_image *out, 1640 enum ipu_rotate_mode rot_mode, 1641 ipu_image_convert_cb_t complete, 1642 void *complete_context) 1643 { 1644 struct ipu_image_convert_ctx *ctx; 1645 struct ipu_image_convert_run *run; 1646 int ret; 1647 1648 ctx = ipu_image_convert_prepare(ipu, ic_task, in, out, rot_mode, 1649 complete, complete_context); 1650 if (IS_ERR(ctx)) 1651 return ERR_CAST(ctx); 1652 1653 run = kzalloc(sizeof(*run), GFP_KERNEL); 1654 if (!run) { 1655 ipu_image_convert_unprepare(ctx); 1656 return ERR_PTR(-ENOMEM); 1657 } 1658 1659 run->ctx = ctx; 1660 run->in_phys = in->phys0; 1661 run->out_phys = out->phys0; 1662 1663 ret = ipu_image_convert_queue(run); 1664 if (ret) { 1665 ipu_image_convert_unprepare(ctx); 1666 kfree(run); 1667 return ERR_PTR(ret); 1668 } 1669 1670 return run; 1671 } 1672 EXPORT_SYMBOL_GPL(ipu_image_convert); 1673 1674 /* "Canned" synchronous single image conversion */ 1675 static void image_convert_sync_complete(struct ipu_image_convert_run *run, 1676 void *data) 1677 { 1678 struct completion *comp = data; 1679 1680 complete(comp); 1681 } 1682 1683 int ipu_image_convert_sync(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1684 struct ipu_image *in, struct ipu_image *out, 1685 enum ipu_rotate_mode rot_mode) 1686 { 1687 struct ipu_image_convert_run *run; 1688 struct completion comp; 1689 int ret; 1690 1691 init_completion(&comp); 1692 1693 run = ipu_image_convert(ipu, ic_task, in, out, rot_mode, 1694 image_convert_sync_complete, &comp); 1695 if (IS_ERR(run)) 1696 return PTR_ERR(run); 1697 1698 ret = wait_for_completion_timeout(&comp, msecs_to_jiffies(10000)); 1699 ret = (ret == 0) ? -ETIMEDOUT : 0; 1700 1701 ipu_image_convert_unprepare(run->ctx); 1702 kfree(run); 1703 1704 return ret; 1705 } 1706 EXPORT_SYMBOL_GPL(ipu_image_convert_sync); 1707 1708 int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev) 1709 { 1710 struct ipu_image_convert_priv *priv; 1711 int i; 1712 1713 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1714 if (!priv) 1715 return -ENOMEM; 1716 1717 ipu->image_convert_priv = priv; 1718 priv->ipu = ipu; 1719 1720 for (i = 0; i < IC_NUM_TASKS; i++) { 1721 struct ipu_image_convert_chan *chan = &priv->chan[i]; 1722 1723 chan->ic_task = i; 1724 chan->priv = priv; 1725 chan->dma_ch = &image_convert_dma_chan[i]; 1726 chan->out_eof_irq = -1; 1727 chan->rot_out_eof_irq = -1; 1728 1729 spin_lock_init(&chan->irqlock); 1730 INIT_LIST_HEAD(&chan->ctx_list); 1731 INIT_LIST_HEAD(&chan->pending_q); 1732 INIT_LIST_HEAD(&chan->done_q); 1733 } 1734 1735 return 0; 1736 } 1737 1738 void ipu_image_convert_exit(struct ipu_soc *ipu) 1739 { 1740 } 1741