1 /* 2 * Copyright (C) 2012-2016 Mentor Graphics Inc. 3 * 4 * Queued image conversion support, with tiling and rotation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include <linux/interrupt.h> 18 #include <linux/dma-mapping.h> 19 #include <video/imx-ipu-image-convert.h> 20 #include "ipu-prv.h" 21 22 /* 23 * The IC Resizer has a restriction that the output frame from the 24 * resizer must be 1024 or less in both width (pixels) and height 25 * (lines). 26 * 27 * The image converter attempts to split up a conversion when 28 * the desired output (converted) frame resolution exceeds the 29 * IC resizer limit of 1024 in either dimension. 30 * 31 * If either dimension of the output frame exceeds the limit, the 32 * dimension is split into 1, 2, or 4 equal stripes, for a maximum 33 * of 4*4 or 16 tiles. A conversion is then carried out for each 34 * tile (but taking care to pass the full frame stride length to 35 * the DMA channel's parameter memory!). IDMA double-buffering is used 36 * to convert each tile back-to-back when possible (see note below 37 * when double_buffering boolean is set). 38 * 39 * Note that the input frame must be split up into the same number 40 * of tiles as the output frame. 41 * 42 * FIXME: at this point there is no attempt to deal with visible seams 43 * at the tile boundaries when upscaling. The seams are caused by a reset 44 * of the bilinear upscale interpolation when starting a new tile. The 45 * seams are barely visible for small upscale factors, but become 46 * increasingly visible as the upscale factor gets larger, since more 47 * interpolated pixels get thrown out at the tile boundaries. A possilble 48 * fix might be to overlap tiles of different sizes, but this must be done 49 * while also maintaining the IDMAC dma buffer address alignment and 8x8 IRT 50 * alignment restrictions of each tile. 51 */ 52 53 #define MAX_STRIPES_W 4 54 #define MAX_STRIPES_H 4 55 #define MAX_TILES (MAX_STRIPES_W * MAX_STRIPES_H) 56 57 #define MIN_W 16 58 #define MIN_H 8 59 #define MAX_W 4096 60 #define MAX_H 4096 61 62 enum ipu_image_convert_type { 63 IMAGE_CONVERT_IN = 0, 64 IMAGE_CONVERT_OUT, 65 }; 66 67 struct ipu_image_convert_dma_buf { 68 void *virt; 69 dma_addr_t phys; 70 unsigned long len; 71 }; 72 73 struct ipu_image_convert_dma_chan { 74 int in; 75 int out; 76 int rot_in; 77 int rot_out; 78 int vdi_in_p; 79 int vdi_in; 80 int vdi_in_n; 81 }; 82 83 /* dimensions of one tile */ 84 struct ipu_image_tile { 85 u32 width; 86 u32 height; 87 u32 left; 88 u32 top; 89 /* size and strides are in bytes */ 90 u32 size; 91 u32 stride; 92 u32 rot_stride; 93 /* start Y or packed offset of this tile */ 94 u32 offset; 95 /* offset from start to tile in U plane, for planar formats */ 96 u32 u_off; 97 /* offset from start to tile in V plane, for planar formats */ 98 u32 v_off; 99 }; 100 101 struct ipu_image_convert_image { 102 struct ipu_image base; 103 enum ipu_image_convert_type type; 104 105 const struct ipu_image_pixfmt *fmt; 106 unsigned int stride; 107 108 /* # of rows (horizontal stripes) if dest height is > 1024 */ 109 unsigned int num_rows; 110 /* # of columns (vertical stripes) if dest width is > 1024 */ 111 unsigned int num_cols; 112 113 struct ipu_image_tile tile[MAX_TILES]; 114 }; 115 116 struct ipu_image_pixfmt { 117 u32 fourcc; /* V4L2 fourcc */ 118 int bpp; /* total bpp */ 119 int uv_width_dec; /* decimation in width for U/V planes */ 120 int uv_height_dec; /* decimation in height for U/V planes */ 121 bool planar; /* planar format */ 122 bool uv_swapped; /* U and V planes are swapped */ 123 bool uv_packed; /* partial planar (U and V in same plane) */ 124 }; 125 126 struct ipu_image_convert_ctx; 127 struct ipu_image_convert_chan; 128 struct ipu_image_convert_priv; 129 130 struct ipu_image_convert_ctx { 131 struct ipu_image_convert_chan *chan; 132 133 ipu_image_convert_cb_t complete; 134 void *complete_context; 135 136 /* Source/destination image data and rotation mode */ 137 struct ipu_image_convert_image in; 138 struct ipu_image_convert_image out; 139 enum ipu_rotate_mode rot_mode; 140 u32 downsize_coeff_h; 141 u32 downsize_coeff_v; 142 u32 image_resize_coeff_h; 143 u32 image_resize_coeff_v; 144 u32 resize_coeffs_h[MAX_STRIPES_W]; 145 u32 resize_coeffs_v[MAX_STRIPES_H]; 146 147 /* intermediate buffer for rotation */ 148 struct ipu_image_convert_dma_buf rot_intermediate[2]; 149 150 /* current buffer number for double buffering */ 151 int cur_buf_num; 152 153 bool aborting; 154 struct completion aborted; 155 156 /* can we use double-buffering for this conversion operation? */ 157 bool double_buffering; 158 /* num_rows * num_cols */ 159 unsigned int num_tiles; 160 /* next tile to process */ 161 unsigned int next_tile; 162 /* where to place converted tile in dest image */ 163 unsigned int out_tile_map[MAX_TILES]; 164 165 struct list_head list; 166 }; 167 168 struct ipu_image_convert_chan { 169 struct ipu_image_convert_priv *priv; 170 171 enum ipu_ic_task ic_task; 172 const struct ipu_image_convert_dma_chan *dma_ch; 173 174 struct ipu_ic *ic; 175 struct ipuv3_channel *in_chan; 176 struct ipuv3_channel *out_chan; 177 struct ipuv3_channel *rotation_in_chan; 178 struct ipuv3_channel *rotation_out_chan; 179 180 /* the IPU end-of-frame irqs */ 181 int out_eof_irq; 182 int rot_out_eof_irq; 183 184 spinlock_t irqlock; 185 186 /* list of convert contexts */ 187 struct list_head ctx_list; 188 /* queue of conversion runs */ 189 struct list_head pending_q; 190 /* queue of completed runs */ 191 struct list_head done_q; 192 193 /* the current conversion run */ 194 struct ipu_image_convert_run *current_run; 195 }; 196 197 struct ipu_image_convert_priv { 198 struct ipu_image_convert_chan chan[IC_NUM_TASKS]; 199 struct ipu_soc *ipu; 200 }; 201 202 static const struct ipu_image_convert_dma_chan 203 image_convert_dma_chan[IC_NUM_TASKS] = { 204 [IC_TASK_VIEWFINDER] = { 205 .in = IPUV3_CHANNEL_MEM_IC_PRP_VF, 206 .out = IPUV3_CHANNEL_IC_PRP_VF_MEM, 207 .rot_in = IPUV3_CHANNEL_MEM_ROT_VF, 208 .rot_out = IPUV3_CHANNEL_ROT_VF_MEM, 209 .vdi_in_p = IPUV3_CHANNEL_MEM_VDI_PREV, 210 .vdi_in = IPUV3_CHANNEL_MEM_VDI_CUR, 211 .vdi_in_n = IPUV3_CHANNEL_MEM_VDI_NEXT, 212 }, 213 [IC_TASK_POST_PROCESSOR] = { 214 .in = IPUV3_CHANNEL_MEM_IC_PP, 215 .out = IPUV3_CHANNEL_IC_PP_MEM, 216 .rot_in = IPUV3_CHANNEL_MEM_ROT_PP, 217 .rot_out = IPUV3_CHANNEL_ROT_PP_MEM, 218 }, 219 }; 220 221 static const struct ipu_image_pixfmt image_convert_formats[] = { 222 { 223 .fourcc = V4L2_PIX_FMT_RGB565, 224 .bpp = 16, 225 }, { 226 .fourcc = V4L2_PIX_FMT_RGB24, 227 .bpp = 24, 228 }, { 229 .fourcc = V4L2_PIX_FMT_BGR24, 230 .bpp = 24, 231 }, { 232 .fourcc = V4L2_PIX_FMT_RGB32, 233 .bpp = 32, 234 }, { 235 .fourcc = V4L2_PIX_FMT_BGR32, 236 .bpp = 32, 237 }, { 238 .fourcc = V4L2_PIX_FMT_XRGB32, 239 .bpp = 32, 240 }, { 241 .fourcc = V4L2_PIX_FMT_XBGR32, 242 .bpp = 32, 243 }, { 244 .fourcc = V4L2_PIX_FMT_YUYV, 245 .bpp = 16, 246 .uv_width_dec = 2, 247 .uv_height_dec = 1, 248 }, { 249 .fourcc = V4L2_PIX_FMT_UYVY, 250 .bpp = 16, 251 .uv_width_dec = 2, 252 .uv_height_dec = 1, 253 }, { 254 .fourcc = V4L2_PIX_FMT_YUV420, 255 .bpp = 12, 256 .planar = true, 257 .uv_width_dec = 2, 258 .uv_height_dec = 2, 259 }, { 260 .fourcc = V4L2_PIX_FMT_YVU420, 261 .bpp = 12, 262 .planar = true, 263 .uv_width_dec = 2, 264 .uv_height_dec = 2, 265 .uv_swapped = true, 266 }, { 267 .fourcc = V4L2_PIX_FMT_NV12, 268 .bpp = 12, 269 .planar = true, 270 .uv_width_dec = 2, 271 .uv_height_dec = 2, 272 .uv_packed = true, 273 }, { 274 .fourcc = V4L2_PIX_FMT_YUV422P, 275 .bpp = 16, 276 .planar = true, 277 .uv_width_dec = 2, 278 .uv_height_dec = 1, 279 }, { 280 .fourcc = V4L2_PIX_FMT_NV16, 281 .bpp = 16, 282 .planar = true, 283 .uv_width_dec = 2, 284 .uv_height_dec = 1, 285 .uv_packed = true, 286 }, 287 }; 288 289 static const struct ipu_image_pixfmt *get_format(u32 fourcc) 290 { 291 const struct ipu_image_pixfmt *ret = NULL; 292 unsigned int i; 293 294 for (i = 0; i < ARRAY_SIZE(image_convert_formats); i++) { 295 if (image_convert_formats[i].fourcc == fourcc) { 296 ret = &image_convert_formats[i]; 297 break; 298 } 299 } 300 301 return ret; 302 } 303 304 static void dump_format(struct ipu_image_convert_ctx *ctx, 305 struct ipu_image_convert_image *ic_image) 306 { 307 struct ipu_image_convert_chan *chan = ctx->chan; 308 struct ipu_image_convert_priv *priv = chan->priv; 309 310 dev_dbg(priv->ipu->dev, 311 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles of size %dx%d), %c%c%c%c\n", 312 chan->ic_task, ctx, 313 ic_image->type == IMAGE_CONVERT_OUT ? "Output" : "Input", 314 ic_image->base.pix.width, ic_image->base.pix.height, 315 ic_image->num_cols, ic_image->num_rows, 316 ic_image->tile[0].width, ic_image->tile[0].height, 317 ic_image->fmt->fourcc & 0xff, 318 (ic_image->fmt->fourcc >> 8) & 0xff, 319 (ic_image->fmt->fourcc >> 16) & 0xff, 320 (ic_image->fmt->fourcc >> 24) & 0xff); 321 } 322 323 int ipu_image_convert_enum_format(int index, u32 *fourcc) 324 { 325 const struct ipu_image_pixfmt *fmt; 326 327 if (index >= (int)ARRAY_SIZE(image_convert_formats)) 328 return -EINVAL; 329 330 /* Format found */ 331 fmt = &image_convert_formats[index]; 332 *fourcc = fmt->fourcc; 333 return 0; 334 } 335 EXPORT_SYMBOL_GPL(ipu_image_convert_enum_format); 336 337 static void free_dma_buf(struct ipu_image_convert_priv *priv, 338 struct ipu_image_convert_dma_buf *buf) 339 { 340 if (buf->virt) 341 dma_free_coherent(priv->ipu->dev, 342 buf->len, buf->virt, buf->phys); 343 buf->virt = NULL; 344 buf->phys = 0; 345 } 346 347 static int alloc_dma_buf(struct ipu_image_convert_priv *priv, 348 struct ipu_image_convert_dma_buf *buf, 349 int size) 350 { 351 buf->len = PAGE_ALIGN(size); 352 buf->virt = dma_alloc_coherent(priv->ipu->dev, buf->len, &buf->phys, 353 GFP_DMA | GFP_KERNEL); 354 if (!buf->virt) { 355 dev_err(priv->ipu->dev, "failed to alloc dma buffer\n"); 356 return -ENOMEM; 357 } 358 359 return 0; 360 } 361 362 static inline int num_stripes(int dim) 363 { 364 if (dim <= 1024) 365 return 1; 366 else if (dim <= 2048) 367 return 2; 368 else 369 return 4; 370 } 371 372 /* 373 * Calculate downsizing coefficients, which are the same for all tiles, 374 * and bilinear resizing coefficients, which are used to find the best 375 * seam positions. 376 */ 377 static int calc_image_resize_coefficients(struct ipu_image_convert_ctx *ctx, 378 struct ipu_image *in, 379 struct ipu_image *out) 380 { 381 u32 downsized_width = in->rect.width; 382 u32 downsized_height = in->rect.height; 383 u32 downsize_coeff_v = 0; 384 u32 downsize_coeff_h = 0; 385 u32 resized_width = out->rect.width; 386 u32 resized_height = out->rect.height; 387 u32 resize_coeff_h; 388 u32 resize_coeff_v; 389 390 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 391 resized_width = out->rect.height; 392 resized_height = out->rect.width; 393 } 394 395 /* Do not let invalid input lead to an endless loop below */ 396 if (WARN_ON(resized_width == 0 || resized_height == 0)) 397 return -EINVAL; 398 399 while (downsized_width >= resized_width * 2) { 400 downsized_width >>= 1; 401 downsize_coeff_h++; 402 } 403 404 while (downsized_height >= resized_height * 2) { 405 downsized_height >>= 1; 406 downsize_coeff_v++; 407 } 408 409 /* 410 * Calculate the bilinear resizing coefficients that could be used if 411 * we were converting with a single tile. The bottom right output pixel 412 * should sample as close as possible to the bottom right input pixel 413 * out of the decimator, but not overshoot it: 414 */ 415 resize_coeff_h = 8192 * (downsized_width - 1) / (resized_width - 1); 416 resize_coeff_v = 8192 * (downsized_height - 1) / (resized_height - 1); 417 418 dev_dbg(ctx->chan->priv->ipu->dev, 419 "%s: hscale: >>%u, *8192/%u vscale: >>%u, *8192/%u, %ux%u tiles\n", 420 __func__, downsize_coeff_h, resize_coeff_h, downsize_coeff_v, 421 resize_coeff_v, ctx->in.num_cols, ctx->in.num_rows); 422 423 if (downsize_coeff_h > 2 || downsize_coeff_v > 2 || 424 resize_coeff_h > 0x3fff || resize_coeff_v > 0x3fff) 425 return -EINVAL; 426 427 ctx->downsize_coeff_h = downsize_coeff_h; 428 ctx->downsize_coeff_v = downsize_coeff_v; 429 ctx->image_resize_coeff_h = resize_coeff_h; 430 ctx->image_resize_coeff_v = resize_coeff_v; 431 432 return 0; 433 } 434 435 /* 436 * We have to adjust the tile width such that the tile physaddrs and 437 * U and V plane offsets are multiples of 8 bytes as required by 438 * the IPU DMA Controller. For the planar formats, this corresponds 439 * to a pixel alignment of 16 (but use a more formal equation since 440 * the variables are available). For all the packed formats, 8 is 441 * good enough. 442 */ 443 static inline u32 tile_width_align(const struct ipu_image_pixfmt *fmt) 444 { 445 return fmt->planar ? 8 * fmt->uv_width_dec : 8; 446 } 447 448 /* 449 * For tile height alignment, we have to ensure that the output tile 450 * heights are multiples of 8 lines if the IRT is required by the 451 * given rotation mode (the IRT performs rotations on 8x8 blocks 452 * at a time). If the IRT is not used, or for input image tiles, 453 * 2 lines are good enough. 454 */ 455 static inline u32 tile_height_align(enum ipu_image_convert_type type, 456 enum ipu_rotate_mode rot_mode) 457 { 458 return (type == IMAGE_CONVERT_OUT && 459 ipu_rot_mode_is_irt(rot_mode)) ? 8 : 2; 460 } 461 462 static void calc_tile_dimensions(struct ipu_image_convert_ctx *ctx, 463 struct ipu_image_convert_image *image) 464 { 465 unsigned int i; 466 467 for (i = 0; i < ctx->num_tiles; i++) { 468 struct ipu_image_tile *tile = &image->tile[i]; 469 const unsigned int row = i / image->num_cols; 470 const unsigned int col = i % image->num_cols; 471 472 tile->height = image->base.pix.height / image->num_rows; 473 tile->width = image->base.pix.width / image->num_cols; 474 tile->left = col * tile->width; 475 tile->top = row * tile->height; 476 tile->size = ((tile->height * image->fmt->bpp) >> 3) * 477 tile->width; 478 479 if (image->fmt->planar) { 480 tile->stride = tile->width; 481 tile->rot_stride = tile->height; 482 } else { 483 tile->stride = 484 (image->fmt->bpp * tile->width) >> 3; 485 tile->rot_stride = 486 (image->fmt->bpp * tile->height) >> 3; 487 } 488 } 489 } 490 491 /* 492 * Use the rotation transformation to find the tile coordinates 493 * (row, col) of a tile in the destination frame that corresponds 494 * to the given tile coordinates of a source frame. The destination 495 * coordinate is then converted to a tile index. 496 */ 497 static int transform_tile_index(struct ipu_image_convert_ctx *ctx, 498 int src_row, int src_col) 499 { 500 struct ipu_image_convert_chan *chan = ctx->chan; 501 struct ipu_image_convert_priv *priv = chan->priv; 502 struct ipu_image_convert_image *s_image = &ctx->in; 503 struct ipu_image_convert_image *d_image = &ctx->out; 504 int dst_row, dst_col; 505 506 /* with no rotation it's a 1:1 mapping */ 507 if (ctx->rot_mode == IPU_ROTATE_NONE) 508 return src_row * s_image->num_cols + src_col; 509 510 /* 511 * before doing the transform, first we have to translate 512 * source row,col for an origin in the center of s_image 513 */ 514 src_row = src_row * 2 - (s_image->num_rows - 1); 515 src_col = src_col * 2 - (s_image->num_cols - 1); 516 517 /* do the rotation transform */ 518 if (ctx->rot_mode & IPU_ROT_BIT_90) { 519 dst_col = -src_row; 520 dst_row = src_col; 521 } else { 522 dst_col = src_col; 523 dst_row = src_row; 524 } 525 526 /* apply flip */ 527 if (ctx->rot_mode & IPU_ROT_BIT_HFLIP) 528 dst_col = -dst_col; 529 if (ctx->rot_mode & IPU_ROT_BIT_VFLIP) 530 dst_row = -dst_row; 531 532 dev_dbg(priv->ipu->dev, "task %u: ctx %p: [%d,%d] --> [%d,%d]\n", 533 chan->ic_task, ctx, src_col, src_row, dst_col, dst_row); 534 535 /* 536 * finally translate dest row,col using an origin in upper 537 * left of d_image 538 */ 539 dst_row += d_image->num_rows - 1; 540 dst_col += d_image->num_cols - 1; 541 dst_row /= 2; 542 dst_col /= 2; 543 544 return dst_row * d_image->num_cols + dst_col; 545 } 546 547 /* 548 * Fill the out_tile_map[] with transformed destination tile indeces. 549 */ 550 static void calc_out_tile_map(struct ipu_image_convert_ctx *ctx) 551 { 552 struct ipu_image_convert_image *s_image = &ctx->in; 553 unsigned int row, col, tile = 0; 554 555 for (row = 0; row < s_image->num_rows; row++) { 556 for (col = 0; col < s_image->num_cols; col++) { 557 ctx->out_tile_map[tile] = 558 transform_tile_index(ctx, row, col); 559 tile++; 560 } 561 } 562 } 563 564 static int calc_tile_offsets_planar(struct ipu_image_convert_ctx *ctx, 565 struct ipu_image_convert_image *image) 566 { 567 struct ipu_image_convert_chan *chan = ctx->chan; 568 struct ipu_image_convert_priv *priv = chan->priv; 569 const struct ipu_image_pixfmt *fmt = image->fmt; 570 unsigned int row, col, tile = 0; 571 u32 H, top, y_stride, uv_stride; 572 u32 uv_row_off, uv_col_off, uv_off, u_off, v_off, tmp; 573 u32 y_row_off, y_col_off, y_off; 574 u32 y_size, uv_size; 575 576 /* setup some convenience vars */ 577 H = image->base.pix.height; 578 579 y_stride = image->stride; 580 uv_stride = y_stride / fmt->uv_width_dec; 581 if (fmt->uv_packed) 582 uv_stride *= 2; 583 584 y_size = H * y_stride; 585 uv_size = y_size / (fmt->uv_width_dec * fmt->uv_height_dec); 586 587 for (row = 0; row < image->num_rows; row++) { 588 top = image->tile[tile].top; 589 y_row_off = top * y_stride; 590 uv_row_off = (top * uv_stride) / fmt->uv_height_dec; 591 592 for (col = 0; col < image->num_cols; col++) { 593 y_col_off = image->tile[tile].left; 594 uv_col_off = y_col_off / fmt->uv_width_dec; 595 if (fmt->uv_packed) 596 uv_col_off *= 2; 597 598 y_off = y_row_off + y_col_off; 599 uv_off = uv_row_off + uv_col_off; 600 601 u_off = y_size - y_off + uv_off; 602 v_off = (fmt->uv_packed) ? 0 : u_off + uv_size; 603 if (fmt->uv_swapped) { 604 tmp = u_off; 605 u_off = v_off; 606 v_off = tmp; 607 } 608 609 image->tile[tile].offset = y_off; 610 image->tile[tile].u_off = u_off; 611 image->tile[tile++].v_off = v_off; 612 613 if ((y_off & 0x7) || (u_off & 0x7) || (v_off & 0x7)) { 614 dev_err(priv->ipu->dev, 615 "task %u: ctx %p: %s@[%d,%d]: " 616 "y_off %08x, u_off %08x, v_off %08x\n", 617 chan->ic_task, ctx, 618 image->type == IMAGE_CONVERT_IN ? 619 "Input" : "Output", row, col, 620 y_off, u_off, v_off); 621 return -EINVAL; 622 } 623 } 624 } 625 626 return 0; 627 } 628 629 static int calc_tile_offsets_packed(struct ipu_image_convert_ctx *ctx, 630 struct ipu_image_convert_image *image) 631 { 632 struct ipu_image_convert_chan *chan = ctx->chan; 633 struct ipu_image_convert_priv *priv = chan->priv; 634 const struct ipu_image_pixfmt *fmt = image->fmt; 635 unsigned int row, col, tile = 0; 636 u32 bpp, stride, offset; 637 u32 row_off, col_off; 638 639 /* setup some convenience vars */ 640 stride = image->stride; 641 bpp = fmt->bpp; 642 643 for (row = 0; row < image->num_rows; row++) { 644 row_off = image->tile[tile].top * stride; 645 646 for (col = 0; col < image->num_cols; col++) { 647 col_off = (image->tile[tile].left * bpp) >> 3; 648 649 offset = row_off + col_off; 650 651 image->tile[tile].offset = offset; 652 image->tile[tile].u_off = 0; 653 image->tile[tile++].v_off = 0; 654 655 if (offset & 0x7) { 656 dev_err(priv->ipu->dev, 657 "task %u: ctx %p: %s@[%d,%d]: " 658 "phys %08x\n", 659 chan->ic_task, ctx, 660 image->type == IMAGE_CONVERT_IN ? 661 "Input" : "Output", row, col, 662 row_off + col_off); 663 return -EINVAL; 664 } 665 } 666 } 667 668 return 0; 669 } 670 671 static int calc_tile_offsets(struct ipu_image_convert_ctx *ctx, 672 struct ipu_image_convert_image *image) 673 { 674 if (image->fmt->planar) 675 return calc_tile_offsets_planar(ctx, image); 676 677 return calc_tile_offsets_packed(ctx, image); 678 } 679 680 /* 681 * Calculate the resizing ratio for the IC main processing section given input 682 * size, fixed downsizing coefficient, and output size. 683 * Either round to closest for the next tile's first pixel to minimize seams 684 * and distortion (for all but right column / bottom row), or round down to 685 * avoid sampling beyond the edges of the input image for this tile's last 686 * pixel. 687 * Returns the resizing coefficient, resizing ratio is 8192.0 / resize_coeff. 688 */ 689 static u32 calc_resize_coeff(u32 input_size, u32 downsize_coeff, 690 u32 output_size, bool allow_overshoot) 691 { 692 u32 downsized = input_size >> downsize_coeff; 693 694 if (allow_overshoot) 695 return DIV_ROUND_CLOSEST(8192 * downsized, output_size); 696 else 697 return 8192 * (downsized - 1) / (output_size - 1); 698 } 699 700 /* 701 * Slightly modify resize coefficients per tile to hide the bilinear 702 * interpolator reset at tile borders, shifting the right / bottom edge 703 * by up to a half input pixel. This removes noticeable seams between 704 * tiles at higher upscaling factors. 705 */ 706 static void calc_tile_resize_coefficients(struct ipu_image_convert_ctx *ctx) 707 { 708 struct ipu_image_convert_chan *chan = ctx->chan; 709 struct ipu_image_convert_priv *priv = chan->priv; 710 struct ipu_image_tile *in_tile, *out_tile; 711 unsigned int col, row, tile_idx; 712 unsigned int last_output; 713 714 for (col = 0; col < ctx->in.num_cols; col++) { 715 bool closest = (col < ctx->in.num_cols - 1) && 716 !(ctx->rot_mode & IPU_ROT_BIT_HFLIP); 717 u32 resized_width; 718 u32 resize_coeff_h; 719 720 tile_idx = col; 721 in_tile = &ctx->in.tile[tile_idx]; 722 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 723 724 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 725 resized_width = out_tile->height; 726 else 727 resized_width = out_tile->width; 728 729 resize_coeff_h = calc_resize_coeff(in_tile->width, 730 ctx->downsize_coeff_h, 731 resized_width, closest); 732 733 dev_dbg(priv->ipu->dev, "%s: column %u hscale: *8192/%u\n", 734 __func__, col, resize_coeff_h); 735 736 737 for (row = 0; row < ctx->in.num_rows; row++) { 738 tile_idx = row * ctx->in.num_cols + col; 739 in_tile = &ctx->in.tile[tile_idx]; 740 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 741 742 /* 743 * With the horizontal scaling factor known, round up 744 * resized width (output width or height) to burst size. 745 */ 746 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 747 out_tile->height = round_up(resized_width, 8); 748 else 749 out_tile->width = round_up(resized_width, 8); 750 751 /* 752 * Calculate input width from the last accessed input 753 * pixel given resized width and scaling coefficients. 754 * Round up to burst size. 755 */ 756 last_output = round_up(resized_width, 8) - 1; 757 if (closest) 758 last_output++; 759 in_tile->width = round_up( 760 (DIV_ROUND_UP(last_output * resize_coeff_h, 761 8192) + 1) 762 << ctx->downsize_coeff_h, 8); 763 } 764 765 ctx->resize_coeffs_h[col] = resize_coeff_h; 766 } 767 768 for (row = 0; row < ctx->in.num_rows; row++) { 769 bool closest = (row < ctx->in.num_rows - 1) && 770 !(ctx->rot_mode & IPU_ROT_BIT_VFLIP); 771 u32 resized_height; 772 u32 resize_coeff_v; 773 774 tile_idx = row * ctx->in.num_cols; 775 in_tile = &ctx->in.tile[tile_idx]; 776 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 777 778 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 779 resized_height = out_tile->width; 780 else 781 resized_height = out_tile->height; 782 783 resize_coeff_v = calc_resize_coeff(in_tile->height, 784 ctx->downsize_coeff_v, 785 resized_height, closest); 786 787 dev_dbg(priv->ipu->dev, "%s: row %u vscale: *8192/%u\n", 788 __func__, row, resize_coeff_v); 789 790 for (col = 0; col < ctx->in.num_cols; col++) { 791 tile_idx = row * ctx->in.num_cols + col; 792 in_tile = &ctx->in.tile[tile_idx]; 793 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 794 795 /* 796 * With the vertical scaling factor known, round up 797 * resized height (output width or height) to IDMAC 798 * limitations. 799 */ 800 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 801 out_tile->width = round_up(resized_height, 2); 802 else 803 out_tile->height = round_up(resized_height, 2); 804 805 /* 806 * Calculate input width from the last accessed input 807 * pixel given resized height and scaling coefficients. 808 * Align to IDMAC restrictions. 809 */ 810 last_output = round_up(resized_height, 2) - 1; 811 if (closest) 812 last_output++; 813 in_tile->height = round_up( 814 (DIV_ROUND_UP(last_output * resize_coeff_v, 815 8192) + 1) 816 << ctx->downsize_coeff_v, 2); 817 } 818 819 ctx->resize_coeffs_v[row] = resize_coeff_v; 820 } 821 } 822 823 /* 824 * return the number of runs in given queue (pending_q or done_q) 825 * for this context. hold irqlock when calling. 826 */ 827 static int get_run_count(struct ipu_image_convert_ctx *ctx, 828 struct list_head *q) 829 { 830 struct ipu_image_convert_run *run; 831 int count = 0; 832 833 lockdep_assert_held(&ctx->chan->irqlock); 834 835 list_for_each_entry(run, q, list) { 836 if (run->ctx == ctx) 837 count++; 838 } 839 840 return count; 841 } 842 843 static void convert_stop(struct ipu_image_convert_run *run) 844 { 845 struct ipu_image_convert_ctx *ctx = run->ctx; 846 struct ipu_image_convert_chan *chan = ctx->chan; 847 struct ipu_image_convert_priv *priv = chan->priv; 848 849 dev_dbg(priv->ipu->dev, "%s: task %u: stopping ctx %p run %p\n", 850 __func__, chan->ic_task, ctx, run); 851 852 /* disable IC tasks and the channels */ 853 ipu_ic_task_disable(chan->ic); 854 ipu_idmac_disable_channel(chan->in_chan); 855 ipu_idmac_disable_channel(chan->out_chan); 856 857 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 858 ipu_idmac_disable_channel(chan->rotation_in_chan); 859 ipu_idmac_disable_channel(chan->rotation_out_chan); 860 ipu_idmac_unlink(chan->out_chan, chan->rotation_in_chan); 861 } 862 863 ipu_ic_disable(chan->ic); 864 } 865 866 static void init_idmac_channel(struct ipu_image_convert_ctx *ctx, 867 struct ipuv3_channel *channel, 868 struct ipu_image_convert_image *image, 869 enum ipu_rotate_mode rot_mode, 870 bool rot_swap_width_height, 871 unsigned int tile) 872 { 873 struct ipu_image_convert_chan *chan = ctx->chan; 874 unsigned int burst_size; 875 u32 width, height, stride; 876 dma_addr_t addr0, addr1 = 0; 877 struct ipu_image tile_image; 878 unsigned int tile_idx[2]; 879 880 if (image->type == IMAGE_CONVERT_OUT) { 881 tile_idx[0] = ctx->out_tile_map[tile]; 882 tile_idx[1] = ctx->out_tile_map[1]; 883 } else { 884 tile_idx[0] = tile; 885 tile_idx[1] = 1; 886 } 887 888 if (rot_swap_width_height) { 889 width = image->tile[tile_idx[0]].height; 890 height = image->tile[tile_idx[0]].width; 891 stride = image->tile[tile_idx[0]].rot_stride; 892 addr0 = ctx->rot_intermediate[0].phys; 893 if (ctx->double_buffering) 894 addr1 = ctx->rot_intermediate[1].phys; 895 } else { 896 width = image->tile[tile_idx[0]].width; 897 height = image->tile[tile_idx[0]].height; 898 stride = image->stride; 899 addr0 = image->base.phys0 + 900 image->tile[tile_idx[0]].offset; 901 if (ctx->double_buffering) 902 addr1 = image->base.phys0 + 903 image->tile[tile_idx[1]].offset; 904 } 905 906 ipu_cpmem_zero(channel); 907 908 memset(&tile_image, 0, sizeof(tile_image)); 909 tile_image.pix.width = tile_image.rect.width = width; 910 tile_image.pix.height = tile_image.rect.height = height; 911 tile_image.pix.bytesperline = stride; 912 tile_image.pix.pixelformat = image->fmt->fourcc; 913 tile_image.phys0 = addr0; 914 tile_image.phys1 = addr1; 915 if (image->fmt->planar && !rot_swap_width_height) { 916 tile_image.u_offset = image->tile[tile_idx[0]].u_off; 917 tile_image.v_offset = image->tile[tile_idx[0]].v_off; 918 } 919 920 ipu_cpmem_set_image(channel, &tile_image); 921 922 if (rot_mode) 923 ipu_cpmem_set_rotation(channel, rot_mode); 924 925 if (channel == chan->rotation_in_chan || 926 channel == chan->rotation_out_chan) { 927 burst_size = 8; 928 ipu_cpmem_set_block_mode(channel); 929 } else 930 burst_size = (width % 16) ? 8 : 16; 931 932 ipu_cpmem_set_burstsize(channel, burst_size); 933 934 ipu_ic_task_idma_init(chan->ic, channel, width, height, 935 burst_size, rot_mode); 936 937 /* 938 * Setting a non-zero AXI ID collides with the PRG AXI snooping, so 939 * only do this when there is no PRG present. 940 */ 941 if (!channel->ipu->prg_priv) 942 ipu_cpmem_set_axi_id(channel, 1); 943 944 ipu_idmac_set_double_buffer(channel, ctx->double_buffering); 945 } 946 947 static int convert_start(struct ipu_image_convert_run *run, unsigned int tile) 948 { 949 struct ipu_image_convert_ctx *ctx = run->ctx; 950 struct ipu_image_convert_chan *chan = ctx->chan; 951 struct ipu_image_convert_priv *priv = chan->priv; 952 struct ipu_image_convert_image *s_image = &ctx->in; 953 struct ipu_image_convert_image *d_image = &ctx->out; 954 enum ipu_color_space src_cs, dest_cs; 955 unsigned int dst_tile = ctx->out_tile_map[tile]; 956 unsigned int dest_width, dest_height; 957 unsigned int col, row; 958 u32 rsc; 959 int ret; 960 961 dev_dbg(priv->ipu->dev, "%s: task %u: starting ctx %p run %p tile %u -> %u\n", 962 __func__, chan->ic_task, ctx, run, tile, dst_tile); 963 964 src_cs = ipu_pixelformat_to_colorspace(s_image->fmt->fourcc); 965 dest_cs = ipu_pixelformat_to_colorspace(d_image->fmt->fourcc); 966 967 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 968 /* swap width/height for resizer */ 969 dest_width = d_image->tile[dst_tile].height; 970 dest_height = d_image->tile[dst_tile].width; 971 } else { 972 dest_width = d_image->tile[dst_tile].width; 973 dest_height = d_image->tile[dst_tile].height; 974 } 975 976 row = tile / s_image->num_cols; 977 col = tile % s_image->num_cols; 978 979 rsc = (ctx->downsize_coeff_v << 30) | 980 (ctx->resize_coeffs_v[row] << 16) | 981 (ctx->downsize_coeff_h << 14) | 982 (ctx->resize_coeffs_h[col]); 983 984 dev_dbg(priv->ipu->dev, "%s: %ux%u -> %ux%u (rsc = 0x%x)\n", 985 __func__, s_image->tile[tile].width, 986 s_image->tile[tile].height, dest_width, dest_height, rsc); 987 988 /* setup the IC resizer and CSC */ 989 ret = ipu_ic_task_init_rsc(chan->ic, 990 s_image->tile[tile].width, 991 s_image->tile[tile].height, 992 dest_width, 993 dest_height, 994 src_cs, dest_cs, 995 rsc); 996 if (ret) { 997 dev_err(priv->ipu->dev, "ipu_ic_task_init failed, %d\n", ret); 998 return ret; 999 } 1000 1001 /* init the source MEM-->IC PP IDMAC channel */ 1002 init_idmac_channel(ctx, chan->in_chan, s_image, 1003 IPU_ROTATE_NONE, false, tile); 1004 1005 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1006 /* init the IC PP-->MEM IDMAC channel */ 1007 init_idmac_channel(ctx, chan->out_chan, d_image, 1008 IPU_ROTATE_NONE, true, tile); 1009 1010 /* init the MEM-->IC PP ROT IDMAC channel */ 1011 init_idmac_channel(ctx, chan->rotation_in_chan, d_image, 1012 ctx->rot_mode, true, tile); 1013 1014 /* init the destination IC PP ROT-->MEM IDMAC channel */ 1015 init_idmac_channel(ctx, chan->rotation_out_chan, d_image, 1016 IPU_ROTATE_NONE, false, tile); 1017 1018 /* now link IC PP-->MEM to MEM-->IC PP ROT */ 1019 ipu_idmac_link(chan->out_chan, chan->rotation_in_chan); 1020 } else { 1021 /* init the destination IC PP-->MEM IDMAC channel */ 1022 init_idmac_channel(ctx, chan->out_chan, d_image, 1023 ctx->rot_mode, false, tile); 1024 } 1025 1026 /* enable the IC */ 1027 ipu_ic_enable(chan->ic); 1028 1029 /* set buffers ready */ 1030 ipu_idmac_select_buffer(chan->in_chan, 0); 1031 ipu_idmac_select_buffer(chan->out_chan, 0); 1032 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1033 ipu_idmac_select_buffer(chan->rotation_out_chan, 0); 1034 if (ctx->double_buffering) { 1035 ipu_idmac_select_buffer(chan->in_chan, 1); 1036 ipu_idmac_select_buffer(chan->out_chan, 1); 1037 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1038 ipu_idmac_select_buffer(chan->rotation_out_chan, 1); 1039 } 1040 1041 /* enable the channels! */ 1042 ipu_idmac_enable_channel(chan->in_chan); 1043 ipu_idmac_enable_channel(chan->out_chan); 1044 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1045 ipu_idmac_enable_channel(chan->rotation_in_chan); 1046 ipu_idmac_enable_channel(chan->rotation_out_chan); 1047 } 1048 1049 ipu_ic_task_enable(chan->ic); 1050 1051 ipu_cpmem_dump(chan->in_chan); 1052 ipu_cpmem_dump(chan->out_chan); 1053 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1054 ipu_cpmem_dump(chan->rotation_in_chan); 1055 ipu_cpmem_dump(chan->rotation_out_chan); 1056 } 1057 1058 ipu_dump(priv->ipu); 1059 1060 return 0; 1061 } 1062 1063 /* hold irqlock when calling */ 1064 static int do_run(struct ipu_image_convert_run *run) 1065 { 1066 struct ipu_image_convert_ctx *ctx = run->ctx; 1067 struct ipu_image_convert_chan *chan = ctx->chan; 1068 1069 lockdep_assert_held(&chan->irqlock); 1070 1071 ctx->in.base.phys0 = run->in_phys; 1072 ctx->out.base.phys0 = run->out_phys; 1073 1074 ctx->cur_buf_num = 0; 1075 ctx->next_tile = 1; 1076 1077 /* remove run from pending_q and set as current */ 1078 list_del(&run->list); 1079 chan->current_run = run; 1080 1081 return convert_start(run, 0); 1082 } 1083 1084 /* hold irqlock when calling */ 1085 static void run_next(struct ipu_image_convert_chan *chan) 1086 { 1087 struct ipu_image_convert_priv *priv = chan->priv; 1088 struct ipu_image_convert_run *run, *tmp; 1089 int ret; 1090 1091 lockdep_assert_held(&chan->irqlock); 1092 1093 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 1094 /* skip contexts that are aborting */ 1095 if (run->ctx->aborting) { 1096 dev_dbg(priv->ipu->dev, 1097 "%s: task %u: skipping aborting ctx %p run %p\n", 1098 __func__, chan->ic_task, run->ctx, run); 1099 continue; 1100 } 1101 1102 ret = do_run(run); 1103 if (!ret) 1104 break; 1105 1106 /* 1107 * something went wrong with start, add the run 1108 * to done q and continue to the next run in the 1109 * pending q. 1110 */ 1111 run->status = ret; 1112 list_add_tail(&run->list, &chan->done_q); 1113 chan->current_run = NULL; 1114 } 1115 } 1116 1117 static void empty_done_q(struct ipu_image_convert_chan *chan) 1118 { 1119 struct ipu_image_convert_priv *priv = chan->priv; 1120 struct ipu_image_convert_run *run; 1121 unsigned long flags; 1122 1123 spin_lock_irqsave(&chan->irqlock, flags); 1124 1125 while (!list_empty(&chan->done_q)) { 1126 run = list_entry(chan->done_q.next, 1127 struct ipu_image_convert_run, 1128 list); 1129 1130 list_del(&run->list); 1131 1132 dev_dbg(priv->ipu->dev, 1133 "%s: task %u: completing ctx %p run %p with %d\n", 1134 __func__, chan->ic_task, run->ctx, run, run->status); 1135 1136 /* call the completion callback and free the run */ 1137 spin_unlock_irqrestore(&chan->irqlock, flags); 1138 run->ctx->complete(run, run->ctx->complete_context); 1139 spin_lock_irqsave(&chan->irqlock, flags); 1140 } 1141 1142 spin_unlock_irqrestore(&chan->irqlock, flags); 1143 } 1144 1145 /* 1146 * the bottom half thread clears out the done_q, calling the 1147 * completion handler for each. 1148 */ 1149 static irqreturn_t do_bh(int irq, void *dev_id) 1150 { 1151 struct ipu_image_convert_chan *chan = dev_id; 1152 struct ipu_image_convert_priv *priv = chan->priv; 1153 struct ipu_image_convert_ctx *ctx; 1154 unsigned long flags; 1155 1156 dev_dbg(priv->ipu->dev, "%s: task %u: enter\n", __func__, 1157 chan->ic_task); 1158 1159 empty_done_q(chan); 1160 1161 spin_lock_irqsave(&chan->irqlock, flags); 1162 1163 /* 1164 * the done_q is cleared out, signal any contexts 1165 * that are aborting that abort can complete. 1166 */ 1167 list_for_each_entry(ctx, &chan->ctx_list, list) { 1168 if (ctx->aborting) { 1169 dev_dbg(priv->ipu->dev, 1170 "%s: task %u: signaling abort for ctx %p\n", 1171 __func__, chan->ic_task, ctx); 1172 complete_all(&ctx->aborted); 1173 } 1174 } 1175 1176 spin_unlock_irqrestore(&chan->irqlock, flags); 1177 1178 dev_dbg(priv->ipu->dev, "%s: task %u: exit\n", __func__, 1179 chan->ic_task); 1180 1181 return IRQ_HANDLED; 1182 } 1183 1184 static bool ic_settings_changed(struct ipu_image_convert_ctx *ctx) 1185 { 1186 unsigned int cur_tile = ctx->next_tile - 1; 1187 unsigned int next_tile = ctx->next_tile; 1188 1189 if (ctx->resize_coeffs_h[cur_tile % ctx->in.num_cols] != 1190 ctx->resize_coeffs_h[next_tile % ctx->in.num_cols] || 1191 ctx->resize_coeffs_v[cur_tile / ctx->in.num_cols] != 1192 ctx->resize_coeffs_v[next_tile / ctx->in.num_cols] || 1193 ctx->in.tile[cur_tile].width != ctx->in.tile[next_tile].width || 1194 ctx->in.tile[cur_tile].height != ctx->in.tile[next_tile].height || 1195 ctx->out.tile[cur_tile].width != ctx->out.tile[next_tile].width || 1196 ctx->out.tile[cur_tile].height != ctx->out.tile[next_tile].height) 1197 return true; 1198 1199 return false; 1200 } 1201 1202 /* hold irqlock when calling */ 1203 static irqreturn_t do_irq(struct ipu_image_convert_run *run) 1204 { 1205 struct ipu_image_convert_ctx *ctx = run->ctx; 1206 struct ipu_image_convert_chan *chan = ctx->chan; 1207 struct ipu_image_tile *src_tile, *dst_tile; 1208 struct ipu_image_convert_image *s_image = &ctx->in; 1209 struct ipu_image_convert_image *d_image = &ctx->out; 1210 struct ipuv3_channel *outch; 1211 unsigned int dst_idx; 1212 1213 lockdep_assert_held(&chan->irqlock); 1214 1215 outch = ipu_rot_mode_is_irt(ctx->rot_mode) ? 1216 chan->rotation_out_chan : chan->out_chan; 1217 1218 /* 1219 * It is difficult to stop the channel DMA before the channels 1220 * enter the paused state. Without double-buffering the channels 1221 * are always in a paused state when the EOF irq occurs, so it 1222 * is safe to stop the channels now. For double-buffering we 1223 * just ignore the abort until the operation completes, when it 1224 * is safe to shut down. 1225 */ 1226 if (ctx->aborting && !ctx->double_buffering) { 1227 convert_stop(run); 1228 run->status = -EIO; 1229 goto done; 1230 } 1231 1232 if (ctx->next_tile == ctx->num_tiles) { 1233 /* 1234 * the conversion is complete 1235 */ 1236 convert_stop(run); 1237 run->status = 0; 1238 goto done; 1239 } 1240 1241 /* 1242 * not done, place the next tile buffers. 1243 */ 1244 if (!ctx->double_buffering) { 1245 if (ic_settings_changed(ctx)) { 1246 convert_stop(run); 1247 convert_start(run, ctx->next_tile); 1248 } else { 1249 src_tile = &s_image->tile[ctx->next_tile]; 1250 dst_idx = ctx->out_tile_map[ctx->next_tile]; 1251 dst_tile = &d_image->tile[dst_idx]; 1252 1253 ipu_cpmem_set_buffer(chan->in_chan, 0, 1254 s_image->base.phys0 + 1255 src_tile->offset); 1256 ipu_cpmem_set_buffer(outch, 0, 1257 d_image->base.phys0 + 1258 dst_tile->offset); 1259 if (s_image->fmt->planar) 1260 ipu_cpmem_set_uv_offset(chan->in_chan, 1261 src_tile->u_off, 1262 src_tile->v_off); 1263 if (d_image->fmt->planar) 1264 ipu_cpmem_set_uv_offset(outch, 1265 dst_tile->u_off, 1266 dst_tile->v_off); 1267 1268 ipu_idmac_select_buffer(chan->in_chan, 0); 1269 ipu_idmac_select_buffer(outch, 0); 1270 } 1271 } else if (ctx->next_tile < ctx->num_tiles - 1) { 1272 1273 src_tile = &s_image->tile[ctx->next_tile + 1]; 1274 dst_idx = ctx->out_tile_map[ctx->next_tile + 1]; 1275 dst_tile = &d_image->tile[dst_idx]; 1276 1277 ipu_cpmem_set_buffer(chan->in_chan, ctx->cur_buf_num, 1278 s_image->base.phys0 + src_tile->offset); 1279 ipu_cpmem_set_buffer(outch, ctx->cur_buf_num, 1280 d_image->base.phys0 + dst_tile->offset); 1281 1282 ipu_idmac_select_buffer(chan->in_chan, ctx->cur_buf_num); 1283 ipu_idmac_select_buffer(outch, ctx->cur_buf_num); 1284 1285 ctx->cur_buf_num ^= 1; 1286 } 1287 1288 ctx->next_tile++; 1289 return IRQ_HANDLED; 1290 done: 1291 list_add_tail(&run->list, &chan->done_q); 1292 chan->current_run = NULL; 1293 run_next(chan); 1294 return IRQ_WAKE_THREAD; 1295 } 1296 1297 static irqreturn_t norotate_irq(int irq, void *data) 1298 { 1299 struct ipu_image_convert_chan *chan = data; 1300 struct ipu_image_convert_ctx *ctx; 1301 struct ipu_image_convert_run *run; 1302 unsigned long flags; 1303 irqreturn_t ret; 1304 1305 spin_lock_irqsave(&chan->irqlock, flags); 1306 1307 /* get current run and its context */ 1308 run = chan->current_run; 1309 if (!run) { 1310 ret = IRQ_NONE; 1311 goto out; 1312 } 1313 1314 ctx = run->ctx; 1315 1316 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1317 /* this is a rotation operation, just ignore */ 1318 spin_unlock_irqrestore(&chan->irqlock, flags); 1319 return IRQ_HANDLED; 1320 } 1321 1322 ret = do_irq(run); 1323 out: 1324 spin_unlock_irqrestore(&chan->irqlock, flags); 1325 return ret; 1326 } 1327 1328 static irqreturn_t rotate_irq(int irq, void *data) 1329 { 1330 struct ipu_image_convert_chan *chan = data; 1331 struct ipu_image_convert_priv *priv = chan->priv; 1332 struct ipu_image_convert_ctx *ctx; 1333 struct ipu_image_convert_run *run; 1334 unsigned long flags; 1335 irqreturn_t ret; 1336 1337 spin_lock_irqsave(&chan->irqlock, flags); 1338 1339 /* get current run and its context */ 1340 run = chan->current_run; 1341 if (!run) { 1342 ret = IRQ_NONE; 1343 goto out; 1344 } 1345 1346 ctx = run->ctx; 1347 1348 if (!ipu_rot_mode_is_irt(ctx->rot_mode)) { 1349 /* this was NOT a rotation operation, shouldn't happen */ 1350 dev_err(priv->ipu->dev, "Unexpected rotation interrupt\n"); 1351 spin_unlock_irqrestore(&chan->irqlock, flags); 1352 return IRQ_HANDLED; 1353 } 1354 1355 ret = do_irq(run); 1356 out: 1357 spin_unlock_irqrestore(&chan->irqlock, flags); 1358 return ret; 1359 } 1360 1361 /* 1362 * try to force the completion of runs for this ctx. Called when 1363 * abort wait times out in ipu_image_convert_abort(). 1364 */ 1365 static void force_abort(struct ipu_image_convert_ctx *ctx) 1366 { 1367 struct ipu_image_convert_chan *chan = ctx->chan; 1368 struct ipu_image_convert_run *run; 1369 unsigned long flags; 1370 1371 spin_lock_irqsave(&chan->irqlock, flags); 1372 1373 run = chan->current_run; 1374 if (run && run->ctx == ctx) { 1375 convert_stop(run); 1376 run->status = -EIO; 1377 list_add_tail(&run->list, &chan->done_q); 1378 chan->current_run = NULL; 1379 run_next(chan); 1380 } 1381 1382 spin_unlock_irqrestore(&chan->irqlock, flags); 1383 1384 empty_done_q(chan); 1385 } 1386 1387 static void release_ipu_resources(struct ipu_image_convert_chan *chan) 1388 { 1389 if (chan->out_eof_irq >= 0) 1390 free_irq(chan->out_eof_irq, chan); 1391 if (chan->rot_out_eof_irq >= 0) 1392 free_irq(chan->rot_out_eof_irq, chan); 1393 1394 if (!IS_ERR_OR_NULL(chan->in_chan)) 1395 ipu_idmac_put(chan->in_chan); 1396 if (!IS_ERR_OR_NULL(chan->out_chan)) 1397 ipu_idmac_put(chan->out_chan); 1398 if (!IS_ERR_OR_NULL(chan->rotation_in_chan)) 1399 ipu_idmac_put(chan->rotation_in_chan); 1400 if (!IS_ERR_OR_NULL(chan->rotation_out_chan)) 1401 ipu_idmac_put(chan->rotation_out_chan); 1402 if (!IS_ERR_OR_NULL(chan->ic)) 1403 ipu_ic_put(chan->ic); 1404 1405 chan->in_chan = chan->out_chan = chan->rotation_in_chan = 1406 chan->rotation_out_chan = NULL; 1407 chan->out_eof_irq = chan->rot_out_eof_irq = -1; 1408 } 1409 1410 static int get_ipu_resources(struct ipu_image_convert_chan *chan) 1411 { 1412 const struct ipu_image_convert_dma_chan *dma = chan->dma_ch; 1413 struct ipu_image_convert_priv *priv = chan->priv; 1414 int ret; 1415 1416 /* get IC */ 1417 chan->ic = ipu_ic_get(priv->ipu, chan->ic_task); 1418 if (IS_ERR(chan->ic)) { 1419 dev_err(priv->ipu->dev, "could not acquire IC\n"); 1420 ret = PTR_ERR(chan->ic); 1421 goto err; 1422 } 1423 1424 /* get IDMAC channels */ 1425 chan->in_chan = ipu_idmac_get(priv->ipu, dma->in); 1426 chan->out_chan = ipu_idmac_get(priv->ipu, dma->out); 1427 if (IS_ERR(chan->in_chan) || IS_ERR(chan->out_chan)) { 1428 dev_err(priv->ipu->dev, "could not acquire idmac channels\n"); 1429 ret = -EBUSY; 1430 goto err; 1431 } 1432 1433 chan->rotation_in_chan = ipu_idmac_get(priv->ipu, dma->rot_in); 1434 chan->rotation_out_chan = ipu_idmac_get(priv->ipu, dma->rot_out); 1435 if (IS_ERR(chan->rotation_in_chan) || IS_ERR(chan->rotation_out_chan)) { 1436 dev_err(priv->ipu->dev, 1437 "could not acquire idmac rotation channels\n"); 1438 ret = -EBUSY; 1439 goto err; 1440 } 1441 1442 /* acquire the EOF interrupts */ 1443 chan->out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1444 chan->out_chan, 1445 IPU_IRQ_EOF); 1446 1447 ret = request_threaded_irq(chan->out_eof_irq, norotate_irq, do_bh, 1448 0, "ipu-ic", chan); 1449 if (ret < 0) { 1450 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1451 chan->out_eof_irq); 1452 chan->out_eof_irq = -1; 1453 goto err; 1454 } 1455 1456 chan->rot_out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1457 chan->rotation_out_chan, 1458 IPU_IRQ_EOF); 1459 1460 ret = request_threaded_irq(chan->rot_out_eof_irq, rotate_irq, do_bh, 1461 0, "ipu-ic", chan); 1462 if (ret < 0) { 1463 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1464 chan->rot_out_eof_irq); 1465 chan->rot_out_eof_irq = -1; 1466 goto err; 1467 } 1468 1469 return 0; 1470 err: 1471 release_ipu_resources(chan); 1472 return ret; 1473 } 1474 1475 static int fill_image(struct ipu_image_convert_ctx *ctx, 1476 struct ipu_image_convert_image *ic_image, 1477 struct ipu_image *image, 1478 enum ipu_image_convert_type type) 1479 { 1480 struct ipu_image_convert_priv *priv = ctx->chan->priv; 1481 1482 ic_image->base = *image; 1483 ic_image->type = type; 1484 1485 ic_image->fmt = get_format(image->pix.pixelformat); 1486 if (!ic_image->fmt) { 1487 dev_err(priv->ipu->dev, "pixelformat not supported for %s\n", 1488 type == IMAGE_CONVERT_OUT ? "Output" : "Input"); 1489 return -EINVAL; 1490 } 1491 1492 if (ic_image->fmt->planar) 1493 ic_image->stride = ic_image->base.pix.width; 1494 else 1495 ic_image->stride = ic_image->base.pix.bytesperline; 1496 1497 return 0; 1498 } 1499 1500 /* borrowed from drivers/media/v4l2-core/v4l2-common.c */ 1501 static unsigned int clamp_align(unsigned int x, unsigned int min, 1502 unsigned int max, unsigned int align) 1503 { 1504 /* Bits that must be zero to be aligned */ 1505 unsigned int mask = ~((1 << align) - 1); 1506 1507 /* Clamp to aligned min and max */ 1508 x = clamp(x, (min + ~mask) & mask, max & mask); 1509 1510 /* Round to nearest aligned value */ 1511 if (align) 1512 x = (x + (1 << (align - 1))) & mask; 1513 1514 return x; 1515 } 1516 1517 /* Adjusts input/output images to IPU restrictions */ 1518 void ipu_image_convert_adjust(struct ipu_image *in, struct ipu_image *out, 1519 enum ipu_rotate_mode rot_mode) 1520 { 1521 const struct ipu_image_pixfmt *infmt, *outfmt; 1522 unsigned int num_in_rows, num_in_cols; 1523 unsigned int num_out_rows, num_out_cols; 1524 u32 w_align, h_align; 1525 1526 infmt = get_format(in->pix.pixelformat); 1527 outfmt = get_format(out->pix.pixelformat); 1528 1529 /* set some default pixel formats if needed */ 1530 if (!infmt) { 1531 in->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1532 infmt = get_format(V4L2_PIX_FMT_RGB24); 1533 } 1534 if (!outfmt) { 1535 out->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1536 outfmt = get_format(V4L2_PIX_FMT_RGB24); 1537 } 1538 1539 /* image converter does not handle fields */ 1540 in->pix.field = out->pix.field = V4L2_FIELD_NONE; 1541 1542 /* resizer cannot downsize more than 4:1 */ 1543 if (ipu_rot_mode_is_irt(rot_mode)) { 1544 out->pix.height = max_t(__u32, out->pix.height, 1545 in->pix.width / 4); 1546 out->pix.width = max_t(__u32, out->pix.width, 1547 in->pix.height / 4); 1548 } else { 1549 out->pix.width = max_t(__u32, out->pix.width, 1550 in->pix.width / 4); 1551 out->pix.height = max_t(__u32, out->pix.height, 1552 in->pix.height / 4); 1553 } 1554 1555 /* get tiling rows/cols from output format */ 1556 num_out_rows = num_stripes(out->pix.height); 1557 num_out_cols = num_stripes(out->pix.width); 1558 if (ipu_rot_mode_is_irt(rot_mode)) { 1559 num_in_rows = num_out_cols; 1560 num_in_cols = num_out_rows; 1561 } else { 1562 num_in_rows = num_out_rows; 1563 num_in_cols = num_out_cols; 1564 } 1565 1566 /* align input width/height */ 1567 w_align = ilog2(tile_width_align(infmt) * num_in_cols); 1568 h_align = ilog2(tile_height_align(IMAGE_CONVERT_IN, rot_mode) * 1569 num_in_rows); 1570 in->pix.width = clamp_align(in->pix.width, MIN_W, MAX_W, w_align); 1571 in->pix.height = clamp_align(in->pix.height, MIN_H, MAX_H, h_align); 1572 1573 /* align output width/height */ 1574 w_align = ilog2(tile_width_align(outfmt) * num_out_cols); 1575 h_align = ilog2(tile_height_align(IMAGE_CONVERT_OUT, rot_mode) * 1576 num_out_rows); 1577 out->pix.width = clamp_align(out->pix.width, MIN_W, MAX_W, w_align); 1578 out->pix.height = clamp_align(out->pix.height, MIN_H, MAX_H, h_align); 1579 1580 /* set input/output strides and image sizes */ 1581 in->pix.bytesperline = (in->pix.width * infmt->bpp) >> 3; 1582 in->pix.sizeimage = in->pix.height * in->pix.bytesperline; 1583 out->pix.bytesperline = (out->pix.width * outfmt->bpp) >> 3; 1584 out->pix.sizeimage = out->pix.height * out->pix.bytesperline; 1585 } 1586 EXPORT_SYMBOL_GPL(ipu_image_convert_adjust); 1587 1588 /* 1589 * this is used by ipu_image_convert_prepare() to verify set input and 1590 * output images are valid before starting the conversion. Clients can 1591 * also call it before calling ipu_image_convert_prepare(). 1592 */ 1593 int ipu_image_convert_verify(struct ipu_image *in, struct ipu_image *out, 1594 enum ipu_rotate_mode rot_mode) 1595 { 1596 struct ipu_image testin, testout; 1597 1598 testin = *in; 1599 testout = *out; 1600 1601 ipu_image_convert_adjust(&testin, &testout, rot_mode); 1602 1603 if (testin.pix.width != in->pix.width || 1604 testin.pix.height != in->pix.height || 1605 testout.pix.width != out->pix.width || 1606 testout.pix.height != out->pix.height) 1607 return -EINVAL; 1608 1609 return 0; 1610 } 1611 EXPORT_SYMBOL_GPL(ipu_image_convert_verify); 1612 1613 /* 1614 * Call ipu_image_convert_prepare() to prepare for the conversion of 1615 * given images and rotation mode. Returns a new conversion context. 1616 */ 1617 struct ipu_image_convert_ctx * 1618 ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1619 struct ipu_image *in, struct ipu_image *out, 1620 enum ipu_rotate_mode rot_mode, 1621 ipu_image_convert_cb_t complete, 1622 void *complete_context) 1623 { 1624 struct ipu_image_convert_priv *priv = ipu->image_convert_priv; 1625 struct ipu_image_convert_image *s_image, *d_image; 1626 struct ipu_image_convert_chan *chan; 1627 struct ipu_image_convert_ctx *ctx; 1628 unsigned long flags; 1629 bool get_res; 1630 int ret; 1631 1632 if (!in || !out || !complete || 1633 (ic_task != IC_TASK_VIEWFINDER && 1634 ic_task != IC_TASK_POST_PROCESSOR)) 1635 return ERR_PTR(-EINVAL); 1636 1637 /* verify the in/out images before continuing */ 1638 ret = ipu_image_convert_verify(in, out, rot_mode); 1639 if (ret) { 1640 dev_err(priv->ipu->dev, "%s: in/out formats invalid\n", 1641 __func__); 1642 return ERR_PTR(ret); 1643 } 1644 1645 chan = &priv->chan[ic_task]; 1646 1647 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 1648 if (!ctx) 1649 return ERR_PTR(-ENOMEM); 1650 1651 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p\n", __func__, 1652 chan->ic_task, ctx); 1653 1654 ctx->chan = chan; 1655 init_completion(&ctx->aborted); 1656 1657 s_image = &ctx->in; 1658 d_image = &ctx->out; 1659 1660 /* set tiling and rotation */ 1661 d_image->num_rows = num_stripes(out->pix.height); 1662 d_image->num_cols = num_stripes(out->pix.width); 1663 if (ipu_rot_mode_is_irt(rot_mode)) { 1664 s_image->num_rows = d_image->num_cols; 1665 s_image->num_cols = d_image->num_rows; 1666 } else { 1667 s_image->num_rows = d_image->num_rows; 1668 s_image->num_cols = d_image->num_cols; 1669 } 1670 1671 ctx->num_tiles = d_image->num_cols * d_image->num_rows; 1672 ctx->rot_mode = rot_mode; 1673 1674 ret = fill_image(ctx, s_image, in, IMAGE_CONVERT_IN); 1675 if (ret) 1676 goto out_free; 1677 ret = fill_image(ctx, d_image, out, IMAGE_CONVERT_OUT); 1678 if (ret) 1679 goto out_free; 1680 1681 ret = calc_image_resize_coefficients(ctx, in, out); 1682 if (ret) 1683 goto out_free; 1684 1685 calc_tile_dimensions(ctx, s_image); 1686 ret = calc_tile_offsets(ctx, s_image); 1687 if (ret) 1688 goto out_free; 1689 1690 calc_tile_dimensions(ctx, d_image); 1691 ret = calc_tile_offsets(ctx, d_image); 1692 if (ret) 1693 goto out_free; 1694 1695 calc_out_tile_map(ctx); 1696 calc_tile_resize_coefficients(ctx); 1697 1698 dump_format(ctx, s_image); 1699 dump_format(ctx, d_image); 1700 1701 ctx->complete = complete; 1702 ctx->complete_context = complete_context; 1703 1704 /* 1705 * Can we use double-buffering for this operation? If there is 1706 * only one tile (the whole image can be converted in a single 1707 * operation) there's no point in using double-buffering. Also, 1708 * the IPU's IDMAC channels allow only a single U and V plane 1709 * offset shared between both buffers, but these offsets change 1710 * for every tile, and therefore would have to be updated for 1711 * each buffer which is not possible. So double-buffering is 1712 * impossible when either the source or destination images are 1713 * a planar format (YUV420, YUV422P, etc.). 1714 */ 1715 ctx->double_buffering = (ctx->num_tiles > 1 && 1716 !s_image->fmt->planar && 1717 !d_image->fmt->planar); 1718 1719 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1720 unsigned long intermediate_size = d_image->tile[0].size; 1721 unsigned int i; 1722 1723 for (i = 1; i < ctx->num_tiles; i++) { 1724 if (d_image->tile[i].size > intermediate_size) 1725 intermediate_size = d_image->tile[i].size; 1726 } 1727 1728 ret = alloc_dma_buf(priv, &ctx->rot_intermediate[0], 1729 intermediate_size); 1730 if (ret) 1731 goto out_free; 1732 if (ctx->double_buffering) { 1733 ret = alloc_dma_buf(priv, 1734 &ctx->rot_intermediate[1], 1735 intermediate_size); 1736 if (ret) 1737 goto out_free_dmabuf0; 1738 } 1739 } 1740 1741 spin_lock_irqsave(&chan->irqlock, flags); 1742 1743 get_res = list_empty(&chan->ctx_list); 1744 1745 list_add_tail(&ctx->list, &chan->ctx_list); 1746 1747 spin_unlock_irqrestore(&chan->irqlock, flags); 1748 1749 if (get_res) { 1750 ret = get_ipu_resources(chan); 1751 if (ret) 1752 goto out_free_dmabuf1; 1753 } 1754 1755 return ctx; 1756 1757 out_free_dmabuf1: 1758 free_dma_buf(priv, &ctx->rot_intermediate[1]); 1759 spin_lock_irqsave(&chan->irqlock, flags); 1760 list_del(&ctx->list); 1761 spin_unlock_irqrestore(&chan->irqlock, flags); 1762 out_free_dmabuf0: 1763 free_dma_buf(priv, &ctx->rot_intermediate[0]); 1764 out_free: 1765 kfree(ctx); 1766 return ERR_PTR(ret); 1767 } 1768 EXPORT_SYMBOL_GPL(ipu_image_convert_prepare); 1769 1770 /* 1771 * Carry out a single image conversion run. Only the physaddr's of the input 1772 * and output image buffers are needed. The conversion context must have 1773 * been created previously with ipu_image_convert_prepare(). 1774 */ 1775 int ipu_image_convert_queue(struct ipu_image_convert_run *run) 1776 { 1777 struct ipu_image_convert_chan *chan; 1778 struct ipu_image_convert_priv *priv; 1779 struct ipu_image_convert_ctx *ctx; 1780 unsigned long flags; 1781 int ret = 0; 1782 1783 if (!run || !run->ctx || !run->in_phys || !run->out_phys) 1784 return -EINVAL; 1785 1786 ctx = run->ctx; 1787 chan = ctx->chan; 1788 priv = chan->priv; 1789 1790 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p run %p\n", __func__, 1791 chan->ic_task, ctx, run); 1792 1793 INIT_LIST_HEAD(&run->list); 1794 1795 spin_lock_irqsave(&chan->irqlock, flags); 1796 1797 if (ctx->aborting) { 1798 ret = -EIO; 1799 goto unlock; 1800 } 1801 1802 list_add_tail(&run->list, &chan->pending_q); 1803 1804 if (!chan->current_run) { 1805 ret = do_run(run); 1806 if (ret) 1807 chan->current_run = NULL; 1808 } 1809 unlock: 1810 spin_unlock_irqrestore(&chan->irqlock, flags); 1811 return ret; 1812 } 1813 EXPORT_SYMBOL_GPL(ipu_image_convert_queue); 1814 1815 /* Abort any active or pending conversions for this context */ 1816 static void __ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 1817 { 1818 struct ipu_image_convert_chan *chan = ctx->chan; 1819 struct ipu_image_convert_priv *priv = chan->priv; 1820 struct ipu_image_convert_run *run, *active_run, *tmp; 1821 unsigned long flags; 1822 int run_count, ret; 1823 1824 spin_lock_irqsave(&chan->irqlock, flags); 1825 1826 /* move all remaining pending runs in this context to done_q */ 1827 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 1828 if (run->ctx != ctx) 1829 continue; 1830 run->status = -EIO; 1831 list_move_tail(&run->list, &chan->done_q); 1832 } 1833 1834 run_count = get_run_count(ctx, &chan->done_q); 1835 active_run = (chan->current_run && chan->current_run->ctx == ctx) ? 1836 chan->current_run : NULL; 1837 1838 if (active_run) 1839 reinit_completion(&ctx->aborted); 1840 1841 ctx->aborting = true; 1842 1843 spin_unlock_irqrestore(&chan->irqlock, flags); 1844 1845 if (!run_count && !active_run) { 1846 dev_dbg(priv->ipu->dev, 1847 "%s: task %u: no abort needed for ctx %p\n", 1848 __func__, chan->ic_task, ctx); 1849 return; 1850 } 1851 1852 if (!active_run) { 1853 empty_done_q(chan); 1854 return; 1855 } 1856 1857 dev_dbg(priv->ipu->dev, 1858 "%s: task %u: wait for completion: %d runs\n", 1859 __func__, chan->ic_task, run_count); 1860 1861 ret = wait_for_completion_timeout(&ctx->aborted, 1862 msecs_to_jiffies(10000)); 1863 if (ret == 0) { 1864 dev_warn(priv->ipu->dev, "%s: timeout\n", __func__); 1865 force_abort(ctx); 1866 } 1867 } 1868 1869 void ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 1870 { 1871 __ipu_image_convert_abort(ctx); 1872 ctx->aborting = false; 1873 } 1874 EXPORT_SYMBOL_GPL(ipu_image_convert_abort); 1875 1876 /* Unprepare image conversion context */ 1877 void ipu_image_convert_unprepare(struct ipu_image_convert_ctx *ctx) 1878 { 1879 struct ipu_image_convert_chan *chan = ctx->chan; 1880 struct ipu_image_convert_priv *priv = chan->priv; 1881 unsigned long flags; 1882 bool put_res; 1883 1884 /* make sure no runs are hanging around */ 1885 __ipu_image_convert_abort(ctx); 1886 1887 dev_dbg(priv->ipu->dev, "%s: task %u: removing ctx %p\n", __func__, 1888 chan->ic_task, ctx); 1889 1890 spin_lock_irqsave(&chan->irqlock, flags); 1891 1892 list_del(&ctx->list); 1893 1894 put_res = list_empty(&chan->ctx_list); 1895 1896 spin_unlock_irqrestore(&chan->irqlock, flags); 1897 1898 if (put_res) 1899 release_ipu_resources(chan); 1900 1901 free_dma_buf(priv, &ctx->rot_intermediate[1]); 1902 free_dma_buf(priv, &ctx->rot_intermediate[0]); 1903 1904 kfree(ctx); 1905 } 1906 EXPORT_SYMBOL_GPL(ipu_image_convert_unprepare); 1907 1908 /* 1909 * "Canned" asynchronous single image conversion. Allocates and returns 1910 * a new conversion run. On successful return the caller must free the 1911 * run and call ipu_image_convert_unprepare() after conversion completes. 1912 */ 1913 struct ipu_image_convert_run * 1914 ipu_image_convert(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1915 struct ipu_image *in, struct ipu_image *out, 1916 enum ipu_rotate_mode rot_mode, 1917 ipu_image_convert_cb_t complete, 1918 void *complete_context) 1919 { 1920 struct ipu_image_convert_ctx *ctx; 1921 struct ipu_image_convert_run *run; 1922 int ret; 1923 1924 ctx = ipu_image_convert_prepare(ipu, ic_task, in, out, rot_mode, 1925 complete, complete_context); 1926 if (IS_ERR(ctx)) 1927 return ERR_CAST(ctx); 1928 1929 run = kzalloc(sizeof(*run), GFP_KERNEL); 1930 if (!run) { 1931 ipu_image_convert_unprepare(ctx); 1932 return ERR_PTR(-ENOMEM); 1933 } 1934 1935 run->ctx = ctx; 1936 run->in_phys = in->phys0; 1937 run->out_phys = out->phys0; 1938 1939 ret = ipu_image_convert_queue(run); 1940 if (ret) { 1941 ipu_image_convert_unprepare(ctx); 1942 kfree(run); 1943 return ERR_PTR(ret); 1944 } 1945 1946 return run; 1947 } 1948 EXPORT_SYMBOL_GPL(ipu_image_convert); 1949 1950 /* "Canned" synchronous single image conversion */ 1951 static void image_convert_sync_complete(struct ipu_image_convert_run *run, 1952 void *data) 1953 { 1954 struct completion *comp = data; 1955 1956 complete(comp); 1957 } 1958 1959 int ipu_image_convert_sync(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1960 struct ipu_image *in, struct ipu_image *out, 1961 enum ipu_rotate_mode rot_mode) 1962 { 1963 struct ipu_image_convert_run *run; 1964 struct completion comp; 1965 int ret; 1966 1967 init_completion(&comp); 1968 1969 run = ipu_image_convert(ipu, ic_task, in, out, rot_mode, 1970 image_convert_sync_complete, &comp); 1971 if (IS_ERR(run)) 1972 return PTR_ERR(run); 1973 1974 ret = wait_for_completion_timeout(&comp, msecs_to_jiffies(10000)); 1975 ret = (ret == 0) ? -ETIMEDOUT : 0; 1976 1977 ipu_image_convert_unprepare(run->ctx); 1978 kfree(run); 1979 1980 return ret; 1981 } 1982 EXPORT_SYMBOL_GPL(ipu_image_convert_sync); 1983 1984 int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev) 1985 { 1986 struct ipu_image_convert_priv *priv; 1987 int i; 1988 1989 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1990 if (!priv) 1991 return -ENOMEM; 1992 1993 ipu->image_convert_priv = priv; 1994 priv->ipu = ipu; 1995 1996 for (i = 0; i < IC_NUM_TASKS; i++) { 1997 struct ipu_image_convert_chan *chan = &priv->chan[i]; 1998 1999 chan->ic_task = i; 2000 chan->priv = priv; 2001 chan->dma_ch = &image_convert_dma_chan[i]; 2002 chan->out_eof_irq = -1; 2003 chan->rot_out_eof_irq = -1; 2004 2005 spin_lock_init(&chan->irqlock); 2006 INIT_LIST_HEAD(&chan->ctx_list); 2007 INIT_LIST_HEAD(&chan->pending_q); 2008 INIT_LIST_HEAD(&chan->done_q); 2009 } 2010 2011 return 0; 2012 } 2013 2014 void ipu_image_convert_exit(struct ipu_soc *ipu) 2015 { 2016 } 2017