1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2012-2016 Mentor Graphics Inc. 4 * 5 * Queued image conversion support, with tiling and rotation. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/dma-mapping.h> 10 #include <video/imx-ipu-image-convert.h> 11 #include "ipu-prv.h" 12 13 /* 14 * The IC Resizer has a restriction that the output frame from the 15 * resizer must be 1024 or less in both width (pixels) and height 16 * (lines). 17 * 18 * The image converter attempts to split up a conversion when 19 * the desired output (converted) frame resolution exceeds the 20 * IC resizer limit of 1024 in either dimension. 21 * 22 * If either dimension of the output frame exceeds the limit, the 23 * dimension is split into 1, 2, or 4 equal stripes, for a maximum 24 * of 4*4 or 16 tiles. A conversion is then carried out for each 25 * tile (but taking care to pass the full frame stride length to 26 * the DMA channel's parameter memory!). IDMA double-buffering is used 27 * to convert each tile back-to-back when possible (see note below 28 * when double_buffering boolean is set). 29 * 30 * Note that the input frame must be split up into the same number 31 * of tiles as the output frame: 32 * 33 * +---------+-----+ 34 * +-----+---+ | A | B | 35 * | A | B | | | | 36 * +-----+---+ --> +---------+-----+ 37 * | C | D | | C | D | 38 * +-----+---+ | | | 39 * +---------+-----+ 40 * 41 * Clockwise 90° rotations are handled by first rescaling into a 42 * reusable temporary tile buffer and then rotating with the 8x8 43 * block rotator, writing to the correct destination: 44 * 45 * +-----+-----+ 46 * | | | 47 * +-----+---+ +---------+ | C | A | 48 * | A | B | | A,B, | | | | | 49 * +-----+---+ --> | C,D | | --> | | | 50 * | C | D | +---------+ +-----+-----+ 51 * +-----+---+ | D | B | 52 * | | | 53 * +-----+-----+ 54 * 55 * If the 8x8 block rotator is used, horizontal or vertical flipping 56 * is done during the rotation step, otherwise flipping is done 57 * during the scaling step. 58 * With rotation or flipping, tile order changes between input and 59 * output image. Tiles are numbered row major from top left to bottom 60 * right for both input and output image. 61 */ 62 63 #define MAX_STRIPES_W 4 64 #define MAX_STRIPES_H 4 65 #define MAX_TILES (MAX_STRIPES_W * MAX_STRIPES_H) 66 67 #define MIN_W 16 68 #define MIN_H 8 69 #define MAX_W 4096 70 #define MAX_H 4096 71 72 enum ipu_image_convert_type { 73 IMAGE_CONVERT_IN = 0, 74 IMAGE_CONVERT_OUT, 75 }; 76 77 struct ipu_image_convert_dma_buf { 78 void *virt; 79 dma_addr_t phys; 80 unsigned long len; 81 }; 82 83 struct ipu_image_convert_dma_chan { 84 int in; 85 int out; 86 int rot_in; 87 int rot_out; 88 int vdi_in_p; 89 int vdi_in; 90 int vdi_in_n; 91 }; 92 93 /* dimensions of one tile */ 94 struct ipu_image_tile { 95 u32 width; 96 u32 height; 97 u32 left; 98 u32 top; 99 /* size and strides are in bytes */ 100 u32 size; 101 u32 stride; 102 u32 rot_stride; 103 /* start Y or packed offset of this tile */ 104 u32 offset; 105 /* offset from start to tile in U plane, for planar formats */ 106 u32 u_off; 107 /* offset from start to tile in V plane, for planar formats */ 108 u32 v_off; 109 }; 110 111 struct ipu_image_convert_image { 112 struct ipu_image base; 113 enum ipu_image_convert_type type; 114 115 const struct ipu_image_pixfmt *fmt; 116 unsigned int stride; 117 118 /* # of rows (horizontal stripes) if dest height is > 1024 */ 119 unsigned int num_rows; 120 /* # of columns (vertical stripes) if dest width is > 1024 */ 121 unsigned int num_cols; 122 123 struct ipu_image_tile tile[MAX_TILES]; 124 }; 125 126 struct ipu_image_pixfmt { 127 u32 fourcc; /* V4L2 fourcc */ 128 int bpp; /* total bpp */ 129 int uv_width_dec; /* decimation in width for U/V planes */ 130 int uv_height_dec; /* decimation in height for U/V planes */ 131 bool planar; /* planar format */ 132 bool uv_swapped; /* U and V planes are swapped */ 133 bool uv_packed; /* partial planar (U and V in same plane) */ 134 }; 135 136 struct ipu_image_convert_ctx; 137 struct ipu_image_convert_chan; 138 struct ipu_image_convert_priv; 139 140 struct ipu_image_convert_ctx { 141 struct ipu_image_convert_chan *chan; 142 143 ipu_image_convert_cb_t complete; 144 void *complete_context; 145 146 /* Source/destination image data and rotation mode */ 147 struct ipu_image_convert_image in; 148 struct ipu_image_convert_image out; 149 struct ipu_ic_csc csc; 150 enum ipu_rotate_mode rot_mode; 151 u32 downsize_coeff_h; 152 u32 downsize_coeff_v; 153 u32 image_resize_coeff_h; 154 u32 image_resize_coeff_v; 155 u32 resize_coeffs_h[MAX_STRIPES_W]; 156 u32 resize_coeffs_v[MAX_STRIPES_H]; 157 158 /* intermediate buffer for rotation */ 159 struct ipu_image_convert_dma_buf rot_intermediate[2]; 160 161 /* current buffer number for double buffering */ 162 int cur_buf_num; 163 164 bool aborting; 165 struct completion aborted; 166 167 /* can we use double-buffering for this conversion operation? */ 168 bool double_buffering; 169 /* num_rows * num_cols */ 170 unsigned int num_tiles; 171 /* next tile to process */ 172 unsigned int next_tile; 173 /* where to place converted tile in dest image */ 174 unsigned int out_tile_map[MAX_TILES]; 175 176 struct list_head list; 177 }; 178 179 struct ipu_image_convert_chan { 180 struct ipu_image_convert_priv *priv; 181 182 enum ipu_ic_task ic_task; 183 const struct ipu_image_convert_dma_chan *dma_ch; 184 185 struct ipu_ic *ic; 186 struct ipuv3_channel *in_chan; 187 struct ipuv3_channel *out_chan; 188 struct ipuv3_channel *rotation_in_chan; 189 struct ipuv3_channel *rotation_out_chan; 190 191 /* the IPU end-of-frame irqs */ 192 int out_eof_irq; 193 int rot_out_eof_irq; 194 195 spinlock_t irqlock; 196 197 /* list of convert contexts */ 198 struct list_head ctx_list; 199 /* queue of conversion runs */ 200 struct list_head pending_q; 201 /* queue of completed runs */ 202 struct list_head done_q; 203 204 /* the current conversion run */ 205 struct ipu_image_convert_run *current_run; 206 }; 207 208 struct ipu_image_convert_priv { 209 struct ipu_image_convert_chan chan[IC_NUM_TASKS]; 210 struct ipu_soc *ipu; 211 }; 212 213 static const struct ipu_image_convert_dma_chan 214 image_convert_dma_chan[IC_NUM_TASKS] = { 215 [IC_TASK_VIEWFINDER] = { 216 .in = IPUV3_CHANNEL_MEM_IC_PRP_VF, 217 .out = IPUV3_CHANNEL_IC_PRP_VF_MEM, 218 .rot_in = IPUV3_CHANNEL_MEM_ROT_VF, 219 .rot_out = IPUV3_CHANNEL_ROT_VF_MEM, 220 .vdi_in_p = IPUV3_CHANNEL_MEM_VDI_PREV, 221 .vdi_in = IPUV3_CHANNEL_MEM_VDI_CUR, 222 .vdi_in_n = IPUV3_CHANNEL_MEM_VDI_NEXT, 223 }, 224 [IC_TASK_POST_PROCESSOR] = { 225 .in = IPUV3_CHANNEL_MEM_IC_PP, 226 .out = IPUV3_CHANNEL_IC_PP_MEM, 227 .rot_in = IPUV3_CHANNEL_MEM_ROT_PP, 228 .rot_out = IPUV3_CHANNEL_ROT_PP_MEM, 229 }, 230 }; 231 232 static const struct ipu_image_pixfmt image_convert_formats[] = { 233 { 234 .fourcc = V4L2_PIX_FMT_RGB565, 235 .bpp = 16, 236 }, { 237 .fourcc = V4L2_PIX_FMT_RGB24, 238 .bpp = 24, 239 }, { 240 .fourcc = V4L2_PIX_FMT_BGR24, 241 .bpp = 24, 242 }, { 243 .fourcc = V4L2_PIX_FMT_RGB32, 244 .bpp = 32, 245 }, { 246 .fourcc = V4L2_PIX_FMT_BGR32, 247 .bpp = 32, 248 }, { 249 .fourcc = V4L2_PIX_FMT_XRGB32, 250 .bpp = 32, 251 }, { 252 .fourcc = V4L2_PIX_FMT_XBGR32, 253 .bpp = 32, 254 }, { 255 .fourcc = V4L2_PIX_FMT_BGRX32, 256 .bpp = 32, 257 }, { 258 .fourcc = V4L2_PIX_FMT_RGBX32, 259 .bpp = 32, 260 }, { 261 .fourcc = V4L2_PIX_FMT_YUYV, 262 .bpp = 16, 263 .uv_width_dec = 2, 264 .uv_height_dec = 1, 265 }, { 266 .fourcc = V4L2_PIX_FMT_UYVY, 267 .bpp = 16, 268 .uv_width_dec = 2, 269 .uv_height_dec = 1, 270 }, { 271 .fourcc = V4L2_PIX_FMT_YUV420, 272 .bpp = 12, 273 .planar = true, 274 .uv_width_dec = 2, 275 .uv_height_dec = 2, 276 }, { 277 .fourcc = V4L2_PIX_FMT_YVU420, 278 .bpp = 12, 279 .planar = true, 280 .uv_width_dec = 2, 281 .uv_height_dec = 2, 282 .uv_swapped = true, 283 }, { 284 .fourcc = V4L2_PIX_FMT_NV12, 285 .bpp = 12, 286 .planar = true, 287 .uv_width_dec = 2, 288 .uv_height_dec = 2, 289 .uv_packed = true, 290 }, { 291 .fourcc = V4L2_PIX_FMT_YUV422P, 292 .bpp = 16, 293 .planar = true, 294 .uv_width_dec = 2, 295 .uv_height_dec = 1, 296 }, { 297 .fourcc = V4L2_PIX_FMT_NV16, 298 .bpp = 16, 299 .planar = true, 300 .uv_width_dec = 2, 301 .uv_height_dec = 1, 302 .uv_packed = true, 303 }, 304 }; 305 306 static const struct ipu_image_pixfmt *get_format(u32 fourcc) 307 { 308 const struct ipu_image_pixfmt *ret = NULL; 309 unsigned int i; 310 311 for (i = 0; i < ARRAY_SIZE(image_convert_formats); i++) { 312 if (image_convert_formats[i].fourcc == fourcc) { 313 ret = &image_convert_formats[i]; 314 break; 315 } 316 } 317 318 return ret; 319 } 320 321 static void dump_format(struct ipu_image_convert_ctx *ctx, 322 struct ipu_image_convert_image *ic_image) 323 { 324 struct ipu_image_convert_chan *chan = ctx->chan; 325 struct ipu_image_convert_priv *priv = chan->priv; 326 327 dev_dbg(priv->ipu->dev, 328 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles), %c%c%c%c\n", 329 chan->ic_task, ctx, 330 ic_image->type == IMAGE_CONVERT_OUT ? "Output" : "Input", 331 ic_image->base.pix.width, ic_image->base.pix.height, 332 ic_image->num_cols, ic_image->num_rows, 333 ic_image->fmt->fourcc & 0xff, 334 (ic_image->fmt->fourcc >> 8) & 0xff, 335 (ic_image->fmt->fourcc >> 16) & 0xff, 336 (ic_image->fmt->fourcc >> 24) & 0xff); 337 } 338 339 int ipu_image_convert_enum_format(int index, u32 *fourcc) 340 { 341 const struct ipu_image_pixfmt *fmt; 342 343 if (index >= (int)ARRAY_SIZE(image_convert_formats)) 344 return -EINVAL; 345 346 /* Format found */ 347 fmt = &image_convert_formats[index]; 348 *fourcc = fmt->fourcc; 349 return 0; 350 } 351 EXPORT_SYMBOL_GPL(ipu_image_convert_enum_format); 352 353 static void free_dma_buf(struct ipu_image_convert_priv *priv, 354 struct ipu_image_convert_dma_buf *buf) 355 { 356 if (buf->virt) 357 dma_free_coherent(priv->ipu->dev, 358 buf->len, buf->virt, buf->phys); 359 buf->virt = NULL; 360 buf->phys = 0; 361 } 362 363 static int alloc_dma_buf(struct ipu_image_convert_priv *priv, 364 struct ipu_image_convert_dma_buf *buf, 365 int size) 366 { 367 buf->len = PAGE_ALIGN(size); 368 buf->virt = dma_alloc_coherent(priv->ipu->dev, buf->len, &buf->phys, 369 GFP_DMA | GFP_KERNEL); 370 if (!buf->virt) { 371 dev_err(priv->ipu->dev, "failed to alloc dma buffer\n"); 372 return -ENOMEM; 373 } 374 375 return 0; 376 } 377 378 static inline int num_stripes(int dim) 379 { 380 return (dim - 1) / 1024 + 1; 381 } 382 383 /* 384 * Calculate downsizing coefficients, which are the same for all tiles, 385 * and initial bilinear resizing coefficients, which are used to find the 386 * best seam positions. 387 * Also determine the number of tiles necessary to guarantee that no tile 388 * is larger than 1024 pixels in either dimension at the output and between 389 * IC downsizing and main processing sections. 390 */ 391 static int calc_image_resize_coefficients(struct ipu_image_convert_ctx *ctx, 392 struct ipu_image *in, 393 struct ipu_image *out) 394 { 395 u32 downsized_width = in->rect.width; 396 u32 downsized_height = in->rect.height; 397 u32 downsize_coeff_v = 0; 398 u32 downsize_coeff_h = 0; 399 u32 resized_width = out->rect.width; 400 u32 resized_height = out->rect.height; 401 u32 resize_coeff_h; 402 u32 resize_coeff_v; 403 u32 cols; 404 u32 rows; 405 406 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 407 resized_width = out->rect.height; 408 resized_height = out->rect.width; 409 } 410 411 /* Do not let invalid input lead to an endless loop below */ 412 if (WARN_ON(resized_width == 0 || resized_height == 0)) 413 return -EINVAL; 414 415 while (downsized_width >= resized_width * 2) { 416 downsized_width >>= 1; 417 downsize_coeff_h++; 418 } 419 420 while (downsized_height >= resized_height * 2) { 421 downsized_height >>= 1; 422 downsize_coeff_v++; 423 } 424 425 /* 426 * Calculate the bilinear resizing coefficients that could be used if 427 * we were converting with a single tile. The bottom right output pixel 428 * should sample as close as possible to the bottom right input pixel 429 * out of the decimator, but not overshoot it: 430 */ 431 resize_coeff_h = 8192 * (downsized_width - 1) / (resized_width - 1); 432 resize_coeff_v = 8192 * (downsized_height - 1) / (resized_height - 1); 433 434 /* 435 * Both the output of the IC downsizing section before being passed to 436 * the IC main processing section and the final output of the IC main 437 * processing section must be <= 1024 pixels in both dimensions. 438 */ 439 cols = num_stripes(max_t(u32, downsized_width, resized_width)); 440 rows = num_stripes(max_t(u32, downsized_height, resized_height)); 441 442 dev_dbg(ctx->chan->priv->ipu->dev, 443 "%s: hscale: >>%u, *8192/%u vscale: >>%u, *8192/%u, %ux%u tiles\n", 444 __func__, downsize_coeff_h, resize_coeff_h, downsize_coeff_v, 445 resize_coeff_v, cols, rows); 446 447 if (downsize_coeff_h > 2 || downsize_coeff_v > 2 || 448 resize_coeff_h > 0x3fff || resize_coeff_v > 0x3fff) 449 return -EINVAL; 450 451 ctx->downsize_coeff_h = downsize_coeff_h; 452 ctx->downsize_coeff_v = downsize_coeff_v; 453 ctx->image_resize_coeff_h = resize_coeff_h; 454 ctx->image_resize_coeff_v = resize_coeff_v; 455 ctx->in.num_cols = cols; 456 ctx->in.num_rows = rows; 457 458 return 0; 459 } 460 461 #define round_closest(x, y) round_down((x) + (y)/2, (y)) 462 463 /* 464 * Find the best aligned seam position for the given column / row index. 465 * Rotation and image offsets are out of scope. 466 * 467 * @index: column / row index, used to calculate valid interval 468 * @in_edge: input right / bottom edge 469 * @out_edge: output right / bottom edge 470 * @in_align: input alignment, either horizontal 8-byte line start address 471 * alignment, or pixel alignment due to image format 472 * @out_align: output alignment, either horizontal 8-byte line start address 473 * alignment, or pixel alignment due to image format or rotator 474 * block size 475 * @in_burst: horizontal input burst size in case of horizontal flip 476 * @out_burst: horizontal output burst size or rotator block size 477 * @downsize_coeff: downsizing section coefficient 478 * @resize_coeff: main processing section resizing coefficient 479 * @_in_seam: aligned input seam position return value 480 * @_out_seam: aligned output seam position return value 481 */ 482 static void find_best_seam(struct ipu_image_convert_ctx *ctx, 483 unsigned int index, 484 unsigned int in_edge, 485 unsigned int out_edge, 486 unsigned int in_align, 487 unsigned int out_align, 488 unsigned int in_burst, 489 unsigned int out_burst, 490 unsigned int downsize_coeff, 491 unsigned int resize_coeff, 492 u32 *_in_seam, 493 u32 *_out_seam) 494 { 495 struct device *dev = ctx->chan->priv->ipu->dev; 496 unsigned int out_pos; 497 /* Input / output seam position candidates */ 498 unsigned int out_seam = 0; 499 unsigned int in_seam = 0; 500 unsigned int min_diff = UINT_MAX; 501 unsigned int out_start; 502 unsigned int out_end; 503 unsigned int in_start; 504 unsigned int in_end; 505 506 /* Start within 1024 pixels of the right / bottom edge */ 507 out_start = max_t(int, index * out_align, out_edge - 1024); 508 /* End before having to add more columns to the left / rows above */ 509 out_end = min_t(unsigned int, out_edge, index * 1024 + 1); 510 511 /* 512 * Limit input seam position to make sure that the downsized input tile 513 * to the right or bottom does not exceed 1024 pixels. 514 */ 515 in_start = max_t(int, index * in_align, 516 in_edge - (1024 << downsize_coeff)); 517 in_end = min_t(unsigned int, in_edge, 518 index * (1024 << downsize_coeff) + 1); 519 520 /* 521 * Output tiles must start at a multiple of 8 bytes horizontally and 522 * possibly at an even line horizontally depending on the pixel format. 523 * Only consider output aligned positions for the seam. 524 */ 525 out_start = round_up(out_start, out_align); 526 for (out_pos = out_start; out_pos < out_end; out_pos += out_align) { 527 unsigned int in_pos; 528 unsigned int in_pos_aligned; 529 unsigned int in_pos_rounded; 530 unsigned int abs_diff; 531 532 /* 533 * Tiles in the right row / bottom column may not be allowed to 534 * overshoot horizontally / vertically. out_burst may be the 535 * actual DMA burst size, or the rotator block size. 536 */ 537 if ((out_burst > 1) && (out_edge - out_pos) % out_burst) 538 continue; 539 540 /* 541 * Input sample position, corresponding to out_pos, 19.13 fixed 542 * point. 543 */ 544 in_pos = (out_pos * resize_coeff) << downsize_coeff; 545 /* 546 * The closest input sample position that we could actually 547 * start the input tile at, 19.13 fixed point. 548 */ 549 in_pos_aligned = round_closest(in_pos, 8192U * in_align); 550 /* Convert 19.13 fixed point to integer */ 551 in_pos_rounded = in_pos_aligned / 8192U; 552 553 if (in_pos_rounded < in_start) 554 continue; 555 if (in_pos_rounded >= in_end) 556 break; 557 558 if ((in_burst > 1) && 559 (in_edge - in_pos_rounded) % in_burst) 560 continue; 561 562 if (in_pos < in_pos_aligned) 563 abs_diff = in_pos_aligned - in_pos; 564 else 565 abs_diff = in_pos - in_pos_aligned; 566 567 if (abs_diff < min_diff) { 568 in_seam = in_pos_rounded; 569 out_seam = out_pos; 570 min_diff = abs_diff; 571 } 572 } 573 574 *_out_seam = out_seam; 575 *_in_seam = in_seam; 576 577 dev_dbg(dev, "%s: out_seam %u(%u) in [%u, %u], in_seam %u(%u) in [%u, %u] diff %u.%03u\n", 578 __func__, out_seam, out_align, out_start, out_end, 579 in_seam, in_align, in_start, in_end, min_diff / 8192, 580 DIV_ROUND_CLOSEST(min_diff % 8192 * 1000, 8192)); 581 } 582 583 /* 584 * Tile left edges are required to be aligned to multiples of 8 bytes 585 * by the IDMAC. 586 */ 587 static inline u32 tile_left_align(const struct ipu_image_pixfmt *fmt) 588 { 589 if (fmt->planar) 590 return fmt->uv_packed ? 8 : 8 * fmt->uv_width_dec; 591 else 592 return fmt->bpp == 32 ? 2 : fmt->bpp == 16 ? 4 : 8; 593 } 594 595 /* 596 * Tile top edge alignment is only limited by chroma subsampling. 597 */ 598 static inline u32 tile_top_align(const struct ipu_image_pixfmt *fmt) 599 { 600 return fmt->uv_height_dec > 1 ? 2 : 1; 601 } 602 603 static inline u32 tile_width_align(enum ipu_image_convert_type type, 604 const struct ipu_image_pixfmt *fmt, 605 enum ipu_rotate_mode rot_mode) 606 { 607 if (type == IMAGE_CONVERT_IN) { 608 /* 609 * The IC burst reads 8 pixels at a time. Reading beyond the 610 * end of the line is usually acceptable. Those pixels are 611 * ignored, unless the IC has to write the scaled line in 612 * reverse. 613 */ 614 return (!ipu_rot_mode_is_irt(rot_mode) && 615 (rot_mode & IPU_ROT_BIT_HFLIP)) ? 8 : 2; 616 } 617 618 /* 619 * Align to 16x16 pixel blocks for planar 4:2:0 chroma subsampled 620 * formats to guarantee 8-byte aligned line start addresses in the 621 * chroma planes when IRT is used. Align to 8x8 pixel IRT block size 622 * for all other formats. 623 */ 624 return (ipu_rot_mode_is_irt(rot_mode) && 625 fmt->planar && !fmt->uv_packed) ? 626 8 * fmt->uv_width_dec : 8; 627 } 628 629 static inline u32 tile_height_align(enum ipu_image_convert_type type, 630 const struct ipu_image_pixfmt *fmt, 631 enum ipu_rotate_mode rot_mode) 632 { 633 if (type == IMAGE_CONVERT_IN || !ipu_rot_mode_is_irt(rot_mode)) 634 return 2; 635 636 /* 637 * Align to 16x16 pixel blocks for planar 4:2:0 chroma subsampled 638 * formats to guarantee 8-byte aligned line start addresses in the 639 * chroma planes when IRT is used. Align to 8x8 pixel IRT block size 640 * for all other formats. 641 */ 642 return (fmt->planar && !fmt->uv_packed) ? 8 * fmt->uv_width_dec : 8; 643 } 644 645 /* 646 * Fill in left position and width and for all tiles in an input column, and 647 * for all corresponding output tiles. If the 90° rotator is used, the output 648 * tiles are in a row, and output tile top position and height are set. 649 */ 650 static void fill_tile_column(struct ipu_image_convert_ctx *ctx, 651 unsigned int col, 652 struct ipu_image_convert_image *in, 653 unsigned int in_left, unsigned int in_width, 654 struct ipu_image_convert_image *out, 655 unsigned int out_left, unsigned int out_width) 656 { 657 unsigned int row, tile_idx; 658 struct ipu_image_tile *in_tile, *out_tile; 659 660 for (row = 0; row < in->num_rows; row++) { 661 tile_idx = in->num_cols * row + col; 662 in_tile = &in->tile[tile_idx]; 663 out_tile = &out->tile[ctx->out_tile_map[tile_idx]]; 664 665 in_tile->left = in_left; 666 in_tile->width = in_width; 667 668 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 669 out_tile->top = out_left; 670 out_tile->height = out_width; 671 } else { 672 out_tile->left = out_left; 673 out_tile->width = out_width; 674 } 675 } 676 } 677 678 /* 679 * Fill in top position and height and for all tiles in an input row, and 680 * for all corresponding output tiles. If the 90° rotator is used, the output 681 * tiles are in a column, and output tile left position and width are set. 682 */ 683 static void fill_tile_row(struct ipu_image_convert_ctx *ctx, unsigned int row, 684 struct ipu_image_convert_image *in, 685 unsigned int in_top, unsigned int in_height, 686 struct ipu_image_convert_image *out, 687 unsigned int out_top, unsigned int out_height) 688 { 689 unsigned int col, tile_idx; 690 struct ipu_image_tile *in_tile, *out_tile; 691 692 for (col = 0; col < in->num_cols; col++) { 693 tile_idx = in->num_cols * row + col; 694 in_tile = &in->tile[tile_idx]; 695 out_tile = &out->tile[ctx->out_tile_map[tile_idx]]; 696 697 in_tile->top = in_top; 698 in_tile->height = in_height; 699 700 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 701 out_tile->left = out_top; 702 out_tile->width = out_height; 703 } else { 704 out_tile->top = out_top; 705 out_tile->height = out_height; 706 } 707 } 708 } 709 710 /* 711 * Find the best horizontal and vertical seam positions to split into tiles. 712 * Minimize the fractional part of the input sampling position for the 713 * top / left pixels of each tile. 714 */ 715 static void find_seams(struct ipu_image_convert_ctx *ctx, 716 struct ipu_image_convert_image *in, 717 struct ipu_image_convert_image *out) 718 { 719 struct device *dev = ctx->chan->priv->ipu->dev; 720 unsigned int resized_width = out->base.rect.width; 721 unsigned int resized_height = out->base.rect.height; 722 unsigned int col; 723 unsigned int row; 724 unsigned int in_left_align = tile_left_align(in->fmt); 725 unsigned int in_top_align = tile_top_align(in->fmt); 726 unsigned int out_left_align = tile_left_align(out->fmt); 727 unsigned int out_top_align = tile_top_align(out->fmt); 728 unsigned int out_width_align = tile_width_align(out->type, out->fmt, 729 ctx->rot_mode); 730 unsigned int out_height_align = tile_height_align(out->type, out->fmt, 731 ctx->rot_mode); 732 unsigned int in_right = in->base.rect.width; 733 unsigned int in_bottom = in->base.rect.height; 734 unsigned int out_right = out->base.rect.width; 735 unsigned int out_bottom = out->base.rect.height; 736 unsigned int flipped_out_left; 737 unsigned int flipped_out_top; 738 739 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 740 /* Switch width/height and align top left to IRT block size */ 741 resized_width = out->base.rect.height; 742 resized_height = out->base.rect.width; 743 out_left_align = out_height_align; 744 out_top_align = out_width_align; 745 out_width_align = out_left_align; 746 out_height_align = out_top_align; 747 out_right = out->base.rect.height; 748 out_bottom = out->base.rect.width; 749 } 750 751 for (col = in->num_cols - 1; col > 0; col--) { 752 bool allow_in_overshoot = ipu_rot_mode_is_irt(ctx->rot_mode) || 753 !(ctx->rot_mode & IPU_ROT_BIT_HFLIP); 754 bool allow_out_overshoot = (col < in->num_cols - 1) && 755 !(ctx->rot_mode & IPU_ROT_BIT_HFLIP); 756 unsigned int in_left; 757 unsigned int out_left; 758 759 /* 760 * Align input width to burst length if the scaling step flips 761 * horizontally. 762 */ 763 764 find_best_seam(ctx, col, 765 in_right, out_right, 766 in_left_align, out_left_align, 767 allow_in_overshoot ? 1 : 8 /* burst length */, 768 allow_out_overshoot ? 1 : out_width_align, 769 ctx->downsize_coeff_h, ctx->image_resize_coeff_h, 770 &in_left, &out_left); 771 772 if (ctx->rot_mode & IPU_ROT_BIT_HFLIP) 773 flipped_out_left = resized_width - out_right; 774 else 775 flipped_out_left = out_left; 776 777 fill_tile_column(ctx, col, in, in_left, in_right - in_left, 778 out, flipped_out_left, out_right - out_left); 779 780 dev_dbg(dev, "%s: col %u: %u, %u -> %u, %u\n", __func__, col, 781 in_left, in_right - in_left, 782 flipped_out_left, out_right - out_left); 783 784 in_right = in_left; 785 out_right = out_left; 786 } 787 788 flipped_out_left = (ctx->rot_mode & IPU_ROT_BIT_HFLIP) ? 789 resized_width - out_right : 0; 790 791 fill_tile_column(ctx, 0, in, 0, in_right, 792 out, flipped_out_left, out_right); 793 794 dev_dbg(dev, "%s: col 0: 0, %u -> %u, %u\n", __func__, 795 in_right, flipped_out_left, out_right); 796 797 for (row = in->num_rows - 1; row > 0; row--) { 798 bool allow_overshoot = row < in->num_rows - 1; 799 unsigned int in_top; 800 unsigned int out_top; 801 802 find_best_seam(ctx, row, 803 in_bottom, out_bottom, 804 in_top_align, out_top_align, 805 1, allow_overshoot ? 1 : out_height_align, 806 ctx->downsize_coeff_v, ctx->image_resize_coeff_v, 807 &in_top, &out_top); 808 809 if ((ctx->rot_mode & IPU_ROT_BIT_VFLIP) ^ 810 ipu_rot_mode_is_irt(ctx->rot_mode)) 811 flipped_out_top = resized_height - out_bottom; 812 else 813 flipped_out_top = out_top; 814 815 fill_tile_row(ctx, row, in, in_top, in_bottom - in_top, 816 out, flipped_out_top, out_bottom - out_top); 817 818 dev_dbg(dev, "%s: row %u: %u, %u -> %u, %u\n", __func__, row, 819 in_top, in_bottom - in_top, 820 flipped_out_top, out_bottom - out_top); 821 822 in_bottom = in_top; 823 out_bottom = out_top; 824 } 825 826 if ((ctx->rot_mode & IPU_ROT_BIT_VFLIP) ^ 827 ipu_rot_mode_is_irt(ctx->rot_mode)) 828 flipped_out_top = resized_height - out_bottom; 829 else 830 flipped_out_top = 0; 831 832 fill_tile_row(ctx, 0, in, 0, in_bottom, 833 out, flipped_out_top, out_bottom); 834 835 dev_dbg(dev, "%s: row 0: 0, %u -> %u, %u\n", __func__, 836 in_bottom, flipped_out_top, out_bottom); 837 } 838 839 static int calc_tile_dimensions(struct ipu_image_convert_ctx *ctx, 840 struct ipu_image_convert_image *image) 841 { 842 struct ipu_image_convert_chan *chan = ctx->chan; 843 struct ipu_image_convert_priv *priv = chan->priv; 844 unsigned int max_width = 1024; 845 unsigned int max_height = 1024; 846 unsigned int i; 847 848 if (image->type == IMAGE_CONVERT_IN) { 849 /* Up to 4096x4096 input tile size */ 850 max_width <<= ctx->downsize_coeff_h; 851 max_height <<= ctx->downsize_coeff_v; 852 } 853 854 for (i = 0; i < ctx->num_tiles; i++) { 855 struct ipu_image_tile *tile; 856 const unsigned int row = i / image->num_cols; 857 const unsigned int col = i % image->num_cols; 858 859 if (image->type == IMAGE_CONVERT_OUT) 860 tile = &image->tile[ctx->out_tile_map[i]]; 861 else 862 tile = &image->tile[i]; 863 864 tile->size = ((tile->height * image->fmt->bpp) >> 3) * 865 tile->width; 866 867 if (image->fmt->planar) { 868 tile->stride = tile->width; 869 tile->rot_stride = tile->height; 870 } else { 871 tile->stride = 872 (image->fmt->bpp * tile->width) >> 3; 873 tile->rot_stride = 874 (image->fmt->bpp * tile->height) >> 3; 875 } 876 877 dev_dbg(priv->ipu->dev, 878 "task %u: ctx %p: %s@[%u,%u]: %ux%u@%u,%u\n", 879 chan->ic_task, ctx, 880 image->type == IMAGE_CONVERT_IN ? "Input" : "Output", 881 row, col, 882 tile->width, tile->height, tile->left, tile->top); 883 884 if (!tile->width || tile->width > max_width || 885 !tile->height || tile->height > max_height) { 886 dev_err(priv->ipu->dev, "invalid %s tile size: %ux%u\n", 887 image->type == IMAGE_CONVERT_IN ? "input" : 888 "output", tile->width, tile->height); 889 return -EINVAL; 890 } 891 } 892 893 return 0; 894 } 895 896 /* 897 * Use the rotation transformation to find the tile coordinates 898 * (row, col) of a tile in the destination frame that corresponds 899 * to the given tile coordinates of a source frame. The destination 900 * coordinate is then converted to a tile index. 901 */ 902 static int transform_tile_index(struct ipu_image_convert_ctx *ctx, 903 int src_row, int src_col) 904 { 905 struct ipu_image_convert_chan *chan = ctx->chan; 906 struct ipu_image_convert_priv *priv = chan->priv; 907 struct ipu_image_convert_image *s_image = &ctx->in; 908 struct ipu_image_convert_image *d_image = &ctx->out; 909 int dst_row, dst_col; 910 911 /* with no rotation it's a 1:1 mapping */ 912 if (ctx->rot_mode == IPU_ROTATE_NONE) 913 return src_row * s_image->num_cols + src_col; 914 915 /* 916 * before doing the transform, first we have to translate 917 * source row,col for an origin in the center of s_image 918 */ 919 src_row = src_row * 2 - (s_image->num_rows - 1); 920 src_col = src_col * 2 - (s_image->num_cols - 1); 921 922 /* do the rotation transform */ 923 if (ctx->rot_mode & IPU_ROT_BIT_90) { 924 dst_col = -src_row; 925 dst_row = src_col; 926 } else { 927 dst_col = src_col; 928 dst_row = src_row; 929 } 930 931 /* apply flip */ 932 if (ctx->rot_mode & IPU_ROT_BIT_HFLIP) 933 dst_col = -dst_col; 934 if (ctx->rot_mode & IPU_ROT_BIT_VFLIP) 935 dst_row = -dst_row; 936 937 dev_dbg(priv->ipu->dev, "task %u: ctx %p: [%d,%d] --> [%d,%d]\n", 938 chan->ic_task, ctx, src_col, src_row, dst_col, dst_row); 939 940 /* 941 * finally translate dest row,col using an origin in upper 942 * left of d_image 943 */ 944 dst_row += d_image->num_rows - 1; 945 dst_col += d_image->num_cols - 1; 946 dst_row /= 2; 947 dst_col /= 2; 948 949 return dst_row * d_image->num_cols + dst_col; 950 } 951 952 /* 953 * Fill the out_tile_map[] with transformed destination tile indeces. 954 */ 955 static void calc_out_tile_map(struct ipu_image_convert_ctx *ctx) 956 { 957 struct ipu_image_convert_image *s_image = &ctx->in; 958 unsigned int row, col, tile = 0; 959 960 for (row = 0; row < s_image->num_rows; row++) { 961 for (col = 0; col < s_image->num_cols; col++) { 962 ctx->out_tile_map[tile] = 963 transform_tile_index(ctx, row, col); 964 tile++; 965 } 966 } 967 } 968 969 static int calc_tile_offsets_planar(struct ipu_image_convert_ctx *ctx, 970 struct ipu_image_convert_image *image) 971 { 972 struct ipu_image_convert_chan *chan = ctx->chan; 973 struct ipu_image_convert_priv *priv = chan->priv; 974 const struct ipu_image_pixfmt *fmt = image->fmt; 975 unsigned int row, col, tile = 0; 976 u32 H, top, y_stride, uv_stride; 977 u32 uv_row_off, uv_col_off, uv_off, u_off, v_off, tmp; 978 u32 y_row_off, y_col_off, y_off; 979 u32 y_size, uv_size; 980 981 /* setup some convenience vars */ 982 H = image->base.pix.height; 983 984 y_stride = image->stride; 985 uv_stride = y_stride / fmt->uv_width_dec; 986 if (fmt->uv_packed) 987 uv_stride *= 2; 988 989 y_size = H * y_stride; 990 uv_size = y_size / (fmt->uv_width_dec * fmt->uv_height_dec); 991 992 for (row = 0; row < image->num_rows; row++) { 993 top = image->tile[tile].top; 994 y_row_off = top * y_stride; 995 uv_row_off = (top * uv_stride) / fmt->uv_height_dec; 996 997 for (col = 0; col < image->num_cols; col++) { 998 y_col_off = image->tile[tile].left; 999 uv_col_off = y_col_off / fmt->uv_width_dec; 1000 if (fmt->uv_packed) 1001 uv_col_off *= 2; 1002 1003 y_off = y_row_off + y_col_off; 1004 uv_off = uv_row_off + uv_col_off; 1005 1006 u_off = y_size - y_off + uv_off; 1007 v_off = (fmt->uv_packed) ? 0 : u_off + uv_size; 1008 if (fmt->uv_swapped) { 1009 tmp = u_off; 1010 u_off = v_off; 1011 v_off = tmp; 1012 } 1013 1014 image->tile[tile].offset = y_off; 1015 image->tile[tile].u_off = u_off; 1016 image->tile[tile++].v_off = v_off; 1017 1018 if ((y_off & 0x7) || (u_off & 0x7) || (v_off & 0x7)) { 1019 dev_err(priv->ipu->dev, 1020 "task %u: ctx %p: %s@[%d,%d]: " 1021 "y_off %08x, u_off %08x, v_off %08x\n", 1022 chan->ic_task, ctx, 1023 image->type == IMAGE_CONVERT_IN ? 1024 "Input" : "Output", row, col, 1025 y_off, u_off, v_off); 1026 return -EINVAL; 1027 } 1028 } 1029 } 1030 1031 return 0; 1032 } 1033 1034 static int calc_tile_offsets_packed(struct ipu_image_convert_ctx *ctx, 1035 struct ipu_image_convert_image *image) 1036 { 1037 struct ipu_image_convert_chan *chan = ctx->chan; 1038 struct ipu_image_convert_priv *priv = chan->priv; 1039 const struct ipu_image_pixfmt *fmt = image->fmt; 1040 unsigned int row, col, tile = 0; 1041 u32 bpp, stride, offset; 1042 u32 row_off, col_off; 1043 1044 /* setup some convenience vars */ 1045 stride = image->stride; 1046 bpp = fmt->bpp; 1047 1048 for (row = 0; row < image->num_rows; row++) { 1049 row_off = image->tile[tile].top * stride; 1050 1051 for (col = 0; col < image->num_cols; col++) { 1052 col_off = (image->tile[tile].left * bpp) >> 3; 1053 1054 offset = row_off + col_off; 1055 1056 image->tile[tile].offset = offset; 1057 image->tile[tile].u_off = 0; 1058 image->tile[tile++].v_off = 0; 1059 1060 if (offset & 0x7) { 1061 dev_err(priv->ipu->dev, 1062 "task %u: ctx %p: %s@[%d,%d]: " 1063 "phys %08x\n", 1064 chan->ic_task, ctx, 1065 image->type == IMAGE_CONVERT_IN ? 1066 "Input" : "Output", row, col, 1067 row_off + col_off); 1068 return -EINVAL; 1069 } 1070 } 1071 } 1072 1073 return 0; 1074 } 1075 1076 static int calc_tile_offsets(struct ipu_image_convert_ctx *ctx, 1077 struct ipu_image_convert_image *image) 1078 { 1079 if (image->fmt->planar) 1080 return calc_tile_offsets_planar(ctx, image); 1081 1082 return calc_tile_offsets_packed(ctx, image); 1083 } 1084 1085 /* 1086 * Calculate the resizing ratio for the IC main processing section given input 1087 * size, fixed downsizing coefficient, and output size. 1088 * Either round to closest for the next tile's first pixel to minimize seams 1089 * and distortion (for all but right column / bottom row), or round down to 1090 * avoid sampling beyond the edges of the input image for this tile's last 1091 * pixel. 1092 * Returns the resizing coefficient, resizing ratio is 8192.0 / resize_coeff. 1093 */ 1094 static u32 calc_resize_coeff(u32 input_size, u32 downsize_coeff, 1095 u32 output_size, bool allow_overshoot) 1096 { 1097 u32 downsized = input_size >> downsize_coeff; 1098 1099 if (allow_overshoot) 1100 return DIV_ROUND_CLOSEST(8192 * downsized, output_size); 1101 else 1102 return 8192 * (downsized - 1) / (output_size - 1); 1103 } 1104 1105 /* 1106 * Slightly modify resize coefficients per tile to hide the bilinear 1107 * interpolator reset at tile borders, shifting the right / bottom edge 1108 * by up to a half input pixel. This removes noticeable seams between 1109 * tiles at higher upscaling factors. 1110 */ 1111 static void calc_tile_resize_coefficients(struct ipu_image_convert_ctx *ctx) 1112 { 1113 struct ipu_image_convert_chan *chan = ctx->chan; 1114 struct ipu_image_convert_priv *priv = chan->priv; 1115 struct ipu_image_tile *in_tile, *out_tile; 1116 unsigned int col, row, tile_idx; 1117 unsigned int last_output; 1118 1119 for (col = 0; col < ctx->in.num_cols; col++) { 1120 bool closest = (col < ctx->in.num_cols - 1) && 1121 !(ctx->rot_mode & IPU_ROT_BIT_HFLIP); 1122 u32 resized_width; 1123 u32 resize_coeff_h; 1124 1125 tile_idx = col; 1126 in_tile = &ctx->in.tile[tile_idx]; 1127 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 1128 1129 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1130 resized_width = out_tile->height; 1131 else 1132 resized_width = out_tile->width; 1133 1134 resize_coeff_h = calc_resize_coeff(in_tile->width, 1135 ctx->downsize_coeff_h, 1136 resized_width, closest); 1137 1138 dev_dbg(priv->ipu->dev, "%s: column %u hscale: *8192/%u\n", 1139 __func__, col, resize_coeff_h); 1140 1141 1142 for (row = 0; row < ctx->in.num_rows; row++) { 1143 tile_idx = row * ctx->in.num_cols + col; 1144 in_tile = &ctx->in.tile[tile_idx]; 1145 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 1146 1147 /* 1148 * With the horizontal scaling factor known, round up 1149 * resized width (output width or height) to burst size. 1150 */ 1151 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1152 out_tile->height = round_up(resized_width, 8); 1153 else 1154 out_tile->width = round_up(resized_width, 8); 1155 1156 /* 1157 * Calculate input width from the last accessed input 1158 * pixel given resized width and scaling coefficients. 1159 * Round up to burst size. 1160 */ 1161 last_output = round_up(resized_width, 8) - 1; 1162 if (closest) 1163 last_output++; 1164 in_tile->width = round_up( 1165 (DIV_ROUND_UP(last_output * resize_coeff_h, 1166 8192) + 1) 1167 << ctx->downsize_coeff_h, 8); 1168 } 1169 1170 ctx->resize_coeffs_h[col] = resize_coeff_h; 1171 } 1172 1173 for (row = 0; row < ctx->in.num_rows; row++) { 1174 bool closest = (row < ctx->in.num_rows - 1) && 1175 !(ctx->rot_mode & IPU_ROT_BIT_VFLIP); 1176 u32 resized_height; 1177 u32 resize_coeff_v; 1178 1179 tile_idx = row * ctx->in.num_cols; 1180 in_tile = &ctx->in.tile[tile_idx]; 1181 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 1182 1183 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1184 resized_height = out_tile->width; 1185 else 1186 resized_height = out_tile->height; 1187 1188 resize_coeff_v = calc_resize_coeff(in_tile->height, 1189 ctx->downsize_coeff_v, 1190 resized_height, closest); 1191 1192 dev_dbg(priv->ipu->dev, "%s: row %u vscale: *8192/%u\n", 1193 __func__, row, resize_coeff_v); 1194 1195 for (col = 0; col < ctx->in.num_cols; col++) { 1196 tile_idx = row * ctx->in.num_cols + col; 1197 in_tile = &ctx->in.tile[tile_idx]; 1198 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 1199 1200 /* 1201 * With the vertical scaling factor known, round up 1202 * resized height (output width or height) to IDMAC 1203 * limitations. 1204 */ 1205 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1206 out_tile->width = round_up(resized_height, 2); 1207 else 1208 out_tile->height = round_up(resized_height, 2); 1209 1210 /* 1211 * Calculate input width from the last accessed input 1212 * pixel given resized height and scaling coefficients. 1213 * Align to IDMAC restrictions. 1214 */ 1215 last_output = round_up(resized_height, 2) - 1; 1216 if (closest) 1217 last_output++; 1218 in_tile->height = round_up( 1219 (DIV_ROUND_UP(last_output * resize_coeff_v, 1220 8192) + 1) 1221 << ctx->downsize_coeff_v, 2); 1222 } 1223 1224 ctx->resize_coeffs_v[row] = resize_coeff_v; 1225 } 1226 } 1227 1228 /* 1229 * return the number of runs in given queue (pending_q or done_q) 1230 * for this context. hold irqlock when calling. 1231 */ 1232 static int get_run_count(struct ipu_image_convert_ctx *ctx, 1233 struct list_head *q) 1234 { 1235 struct ipu_image_convert_run *run; 1236 int count = 0; 1237 1238 lockdep_assert_held(&ctx->chan->irqlock); 1239 1240 list_for_each_entry(run, q, list) { 1241 if (run->ctx == ctx) 1242 count++; 1243 } 1244 1245 return count; 1246 } 1247 1248 static void convert_stop(struct ipu_image_convert_run *run) 1249 { 1250 struct ipu_image_convert_ctx *ctx = run->ctx; 1251 struct ipu_image_convert_chan *chan = ctx->chan; 1252 struct ipu_image_convert_priv *priv = chan->priv; 1253 1254 dev_dbg(priv->ipu->dev, "%s: task %u: stopping ctx %p run %p\n", 1255 __func__, chan->ic_task, ctx, run); 1256 1257 /* disable IC tasks and the channels */ 1258 ipu_ic_task_disable(chan->ic); 1259 ipu_idmac_disable_channel(chan->in_chan); 1260 ipu_idmac_disable_channel(chan->out_chan); 1261 1262 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1263 ipu_idmac_disable_channel(chan->rotation_in_chan); 1264 ipu_idmac_disable_channel(chan->rotation_out_chan); 1265 ipu_idmac_unlink(chan->out_chan, chan->rotation_in_chan); 1266 } 1267 1268 ipu_ic_disable(chan->ic); 1269 } 1270 1271 static void init_idmac_channel(struct ipu_image_convert_ctx *ctx, 1272 struct ipuv3_channel *channel, 1273 struct ipu_image_convert_image *image, 1274 enum ipu_rotate_mode rot_mode, 1275 bool rot_swap_width_height, 1276 unsigned int tile) 1277 { 1278 struct ipu_image_convert_chan *chan = ctx->chan; 1279 unsigned int burst_size; 1280 u32 width, height, stride; 1281 dma_addr_t addr0, addr1 = 0; 1282 struct ipu_image tile_image; 1283 unsigned int tile_idx[2]; 1284 1285 if (image->type == IMAGE_CONVERT_OUT) { 1286 tile_idx[0] = ctx->out_tile_map[tile]; 1287 tile_idx[1] = ctx->out_tile_map[1]; 1288 } else { 1289 tile_idx[0] = tile; 1290 tile_idx[1] = 1; 1291 } 1292 1293 if (rot_swap_width_height) { 1294 width = image->tile[tile_idx[0]].height; 1295 height = image->tile[tile_idx[0]].width; 1296 stride = image->tile[tile_idx[0]].rot_stride; 1297 addr0 = ctx->rot_intermediate[0].phys; 1298 if (ctx->double_buffering) 1299 addr1 = ctx->rot_intermediate[1].phys; 1300 } else { 1301 width = image->tile[tile_idx[0]].width; 1302 height = image->tile[tile_idx[0]].height; 1303 stride = image->stride; 1304 addr0 = image->base.phys0 + 1305 image->tile[tile_idx[0]].offset; 1306 if (ctx->double_buffering) 1307 addr1 = image->base.phys0 + 1308 image->tile[tile_idx[1]].offset; 1309 } 1310 1311 ipu_cpmem_zero(channel); 1312 1313 memset(&tile_image, 0, sizeof(tile_image)); 1314 tile_image.pix.width = tile_image.rect.width = width; 1315 tile_image.pix.height = tile_image.rect.height = height; 1316 tile_image.pix.bytesperline = stride; 1317 tile_image.pix.pixelformat = image->fmt->fourcc; 1318 tile_image.phys0 = addr0; 1319 tile_image.phys1 = addr1; 1320 if (image->fmt->planar && !rot_swap_width_height) { 1321 tile_image.u_offset = image->tile[tile_idx[0]].u_off; 1322 tile_image.v_offset = image->tile[tile_idx[0]].v_off; 1323 } 1324 1325 ipu_cpmem_set_image(channel, &tile_image); 1326 1327 if (rot_mode) 1328 ipu_cpmem_set_rotation(channel, rot_mode); 1329 1330 /* 1331 * Skip writing U and V components to odd rows in the output 1332 * channels for planar 4:2:0. 1333 */ 1334 if ((channel == chan->out_chan || 1335 channel == chan->rotation_out_chan) && 1336 image->fmt->planar && image->fmt->uv_height_dec == 2) 1337 ipu_cpmem_skip_odd_chroma_rows(channel); 1338 1339 if (channel == chan->rotation_in_chan || 1340 channel == chan->rotation_out_chan) { 1341 burst_size = 8; 1342 ipu_cpmem_set_block_mode(channel); 1343 } else 1344 burst_size = (width % 16) ? 8 : 16; 1345 1346 ipu_cpmem_set_burstsize(channel, burst_size); 1347 1348 ipu_ic_task_idma_init(chan->ic, channel, width, height, 1349 burst_size, rot_mode); 1350 1351 /* 1352 * Setting a non-zero AXI ID collides with the PRG AXI snooping, so 1353 * only do this when there is no PRG present. 1354 */ 1355 if (!channel->ipu->prg_priv) 1356 ipu_cpmem_set_axi_id(channel, 1); 1357 1358 ipu_idmac_set_double_buffer(channel, ctx->double_buffering); 1359 } 1360 1361 static int convert_start(struct ipu_image_convert_run *run, unsigned int tile) 1362 { 1363 struct ipu_image_convert_ctx *ctx = run->ctx; 1364 struct ipu_image_convert_chan *chan = ctx->chan; 1365 struct ipu_image_convert_priv *priv = chan->priv; 1366 struct ipu_image_convert_image *s_image = &ctx->in; 1367 struct ipu_image_convert_image *d_image = &ctx->out; 1368 unsigned int dst_tile = ctx->out_tile_map[tile]; 1369 unsigned int dest_width, dest_height; 1370 unsigned int col, row; 1371 u32 rsc; 1372 int ret; 1373 1374 dev_dbg(priv->ipu->dev, "%s: task %u: starting ctx %p run %p tile %u -> %u\n", 1375 __func__, chan->ic_task, ctx, run, tile, dst_tile); 1376 1377 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1378 /* swap width/height for resizer */ 1379 dest_width = d_image->tile[dst_tile].height; 1380 dest_height = d_image->tile[dst_tile].width; 1381 } else { 1382 dest_width = d_image->tile[dst_tile].width; 1383 dest_height = d_image->tile[dst_tile].height; 1384 } 1385 1386 row = tile / s_image->num_cols; 1387 col = tile % s_image->num_cols; 1388 1389 rsc = (ctx->downsize_coeff_v << 30) | 1390 (ctx->resize_coeffs_v[row] << 16) | 1391 (ctx->downsize_coeff_h << 14) | 1392 (ctx->resize_coeffs_h[col]); 1393 1394 dev_dbg(priv->ipu->dev, "%s: %ux%u -> %ux%u (rsc = 0x%x)\n", 1395 __func__, s_image->tile[tile].width, 1396 s_image->tile[tile].height, dest_width, dest_height, rsc); 1397 1398 /* setup the IC resizer and CSC */ 1399 ret = ipu_ic_task_init_rsc(chan->ic, &ctx->csc, 1400 s_image->tile[tile].width, 1401 s_image->tile[tile].height, 1402 dest_width, 1403 dest_height, 1404 rsc); 1405 if (ret) { 1406 dev_err(priv->ipu->dev, "ipu_ic_task_init failed, %d\n", ret); 1407 return ret; 1408 } 1409 1410 /* init the source MEM-->IC PP IDMAC channel */ 1411 init_idmac_channel(ctx, chan->in_chan, s_image, 1412 IPU_ROTATE_NONE, false, tile); 1413 1414 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1415 /* init the IC PP-->MEM IDMAC channel */ 1416 init_idmac_channel(ctx, chan->out_chan, d_image, 1417 IPU_ROTATE_NONE, true, tile); 1418 1419 /* init the MEM-->IC PP ROT IDMAC channel */ 1420 init_idmac_channel(ctx, chan->rotation_in_chan, d_image, 1421 ctx->rot_mode, true, tile); 1422 1423 /* init the destination IC PP ROT-->MEM IDMAC channel */ 1424 init_idmac_channel(ctx, chan->rotation_out_chan, d_image, 1425 IPU_ROTATE_NONE, false, tile); 1426 1427 /* now link IC PP-->MEM to MEM-->IC PP ROT */ 1428 ipu_idmac_link(chan->out_chan, chan->rotation_in_chan); 1429 } else { 1430 /* init the destination IC PP-->MEM IDMAC channel */ 1431 init_idmac_channel(ctx, chan->out_chan, d_image, 1432 ctx->rot_mode, false, tile); 1433 } 1434 1435 /* enable the IC */ 1436 ipu_ic_enable(chan->ic); 1437 1438 /* set buffers ready */ 1439 ipu_idmac_select_buffer(chan->in_chan, 0); 1440 ipu_idmac_select_buffer(chan->out_chan, 0); 1441 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1442 ipu_idmac_select_buffer(chan->rotation_out_chan, 0); 1443 if (ctx->double_buffering) { 1444 ipu_idmac_select_buffer(chan->in_chan, 1); 1445 ipu_idmac_select_buffer(chan->out_chan, 1); 1446 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1447 ipu_idmac_select_buffer(chan->rotation_out_chan, 1); 1448 } 1449 1450 /* enable the channels! */ 1451 ipu_idmac_enable_channel(chan->in_chan); 1452 ipu_idmac_enable_channel(chan->out_chan); 1453 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1454 ipu_idmac_enable_channel(chan->rotation_in_chan); 1455 ipu_idmac_enable_channel(chan->rotation_out_chan); 1456 } 1457 1458 ipu_ic_task_enable(chan->ic); 1459 1460 ipu_cpmem_dump(chan->in_chan); 1461 ipu_cpmem_dump(chan->out_chan); 1462 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1463 ipu_cpmem_dump(chan->rotation_in_chan); 1464 ipu_cpmem_dump(chan->rotation_out_chan); 1465 } 1466 1467 ipu_dump(priv->ipu); 1468 1469 return 0; 1470 } 1471 1472 /* hold irqlock when calling */ 1473 static int do_run(struct ipu_image_convert_run *run) 1474 { 1475 struct ipu_image_convert_ctx *ctx = run->ctx; 1476 struct ipu_image_convert_chan *chan = ctx->chan; 1477 1478 lockdep_assert_held(&chan->irqlock); 1479 1480 ctx->in.base.phys0 = run->in_phys; 1481 ctx->out.base.phys0 = run->out_phys; 1482 1483 ctx->cur_buf_num = 0; 1484 ctx->next_tile = 1; 1485 1486 /* remove run from pending_q and set as current */ 1487 list_del(&run->list); 1488 chan->current_run = run; 1489 1490 return convert_start(run, 0); 1491 } 1492 1493 /* hold irqlock when calling */ 1494 static void run_next(struct ipu_image_convert_chan *chan) 1495 { 1496 struct ipu_image_convert_priv *priv = chan->priv; 1497 struct ipu_image_convert_run *run, *tmp; 1498 int ret; 1499 1500 lockdep_assert_held(&chan->irqlock); 1501 1502 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 1503 /* skip contexts that are aborting */ 1504 if (run->ctx->aborting) { 1505 dev_dbg(priv->ipu->dev, 1506 "%s: task %u: skipping aborting ctx %p run %p\n", 1507 __func__, chan->ic_task, run->ctx, run); 1508 continue; 1509 } 1510 1511 ret = do_run(run); 1512 if (!ret) 1513 break; 1514 1515 /* 1516 * something went wrong with start, add the run 1517 * to done q and continue to the next run in the 1518 * pending q. 1519 */ 1520 run->status = ret; 1521 list_add_tail(&run->list, &chan->done_q); 1522 chan->current_run = NULL; 1523 } 1524 } 1525 1526 static void empty_done_q(struct ipu_image_convert_chan *chan) 1527 { 1528 struct ipu_image_convert_priv *priv = chan->priv; 1529 struct ipu_image_convert_run *run; 1530 unsigned long flags; 1531 1532 spin_lock_irqsave(&chan->irqlock, flags); 1533 1534 while (!list_empty(&chan->done_q)) { 1535 run = list_entry(chan->done_q.next, 1536 struct ipu_image_convert_run, 1537 list); 1538 1539 list_del(&run->list); 1540 1541 dev_dbg(priv->ipu->dev, 1542 "%s: task %u: completing ctx %p run %p with %d\n", 1543 __func__, chan->ic_task, run->ctx, run, run->status); 1544 1545 /* call the completion callback and free the run */ 1546 spin_unlock_irqrestore(&chan->irqlock, flags); 1547 run->ctx->complete(run, run->ctx->complete_context); 1548 spin_lock_irqsave(&chan->irqlock, flags); 1549 } 1550 1551 spin_unlock_irqrestore(&chan->irqlock, flags); 1552 } 1553 1554 /* 1555 * the bottom half thread clears out the done_q, calling the 1556 * completion handler for each. 1557 */ 1558 static irqreturn_t do_bh(int irq, void *dev_id) 1559 { 1560 struct ipu_image_convert_chan *chan = dev_id; 1561 struct ipu_image_convert_priv *priv = chan->priv; 1562 struct ipu_image_convert_ctx *ctx; 1563 unsigned long flags; 1564 1565 dev_dbg(priv->ipu->dev, "%s: task %u: enter\n", __func__, 1566 chan->ic_task); 1567 1568 empty_done_q(chan); 1569 1570 spin_lock_irqsave(&chan->irqlock, flags); 1571 1572 /* 1573 * the done_q is cleared out, signal any contexts 1574 * that are aborting that abort can complete. 1575 */ 1576 list_for_each_entry(ctx, &chan->ctx_list, list) { 1577 if (ctx->aborting) { 1578 dev_dbg(priv->ipu->dev, 1579 "%s: task %u: signaling abort for ctx %p\n", 1580 __func__, chan->ic_task, ctx); 1581 complete_all(&ctx->aborted); 1582 } 1583 } 1584 1585 spin_unlock_irqrestore(&chan->irqlock, flags); 1586 1587 dev_dbg(priv->ipu->dev, "%s: task %u: exit\n", __func__, 1588 chan->ic_task); 1589 1590 return IRQ_HANDLED; 1591 } 1592 1593 static bool ic_settings_changed(struct ipu_image_convert_ctx *ctx) 1594 { 1595 unsigned int cur_tile = ctx->next_tile - 1; 1596 unsigned int next_tile = ctx->next_tile; 1597 1598 if (ctx->resize_coeffs_h[cur_tile % ctx->in.num_cols] != 1599 ctx->resize_coeffs_h[next_tile % ctx->in.num_cols] || 1600 ctx->resize_coeffs_v[cur_tile / ctx->in.num_cols] != 1601 ctx->resize_coeffs_v[next_tile / ctx->in.num_cols] || 1602 ctx->in.tile[cur_tile].width != ctx->in.tile[next_tile].width || 1603 ctx->in.tile[cur_tile].height != ctx->in.tile[next_tile].height || 1604 ctx->out.tile[cur_tile].width != ctx->out.tile[next_tile].width || 1605 ctx->out.tile[cur_tile].height != ctx->out.tile[next_tile].height) 1606 return true; 1607 1608 return false; 1609 } 1610 1611 /* hold irqlock when calling */ 1612 static irqreturn_t do_irq(struct ipu_image_convert_run *run) 1613 { 1614 struct ipu_image_convert_ctx *ctx = run->ctx; 1615 struct ipu_image_convert_chan *chan = ctx->chan; 1616 struct ipu_image_tile *src_tile, *dst_tile; 1617 struct ipu_image_convert_image *s_image = &ctx->in; 1618 struct ipu_image_convert_image *d_image = &ctx->out; 1619 struct ipuv3_channel *outch; 1620 unsigned int dst_idx; 1621 1622 lockdep_assert_held(&chan->irqlock); 1623 1624 outch = ipu_rot_mode_is_irt(ctx->rot_mode) ? 1625 chan->rotation_out_chan : chan->out_chan; 1626 1627 /* 1628 * It is difficult to stop the channel DMA before the channels 1629 * enter the paused state. Without double-buffering the channels 1630 * are always in a paused state when the EOF irq occurs, so it 1631 * is safe to stop the channels now. For double-buffering we 1632 * just ignore the abort until the operation completes, when it 1633 * is safe to shut down. 1634 */ 1635 if (ctx->aborting && !ctx->double_buffering) { 1636 convert_stop(run); 1637 run->status = -EIO; 1638 goto done; 1639 } 1640 1641 if (ctx->next_tile == ctx->num_tiles) { 1642 /* 1643 * the conversion is complete 1644 */ 1645 convert_stop(run); 1646 run->status = 0; 1647 goto done; 1648 } 1649 1650 /* 1651 * not done, place the next tile buffers. 1652 */ 1653 if (!ctx->double_buffering) { 1654 if (ic_settings_changed(ctx)) { 1655 convert_stop(run); 1656 convert_start(run, ctx->next_tile); 1657 } else { 1658 src_tile = &s_image->tile[ctx->next_tile]; 1659 dst_idx = ctx->out_tile_map[ctx->next_tile]; 1660 dst_tile = &d_image->tile[dst_idx]; 1661 1662 ipu_cpmem_set_buffer(chan->in_chan, 0, 1663 s_image->base.phys0 + 1664 src_tile->offset); 1665 ipu_cpmem_set_buffer(outch, 0, 1666 d_image->base.phys0 + 1667 dst_tile->offset); 1668 if (s_image->fmt->planar) 1669 ipu_cpmem_set_uv_offset(chan->in_chan, 1670 src_tile->u_off, 1671 src_tile->v_off); 1672 if (d_image->fmt->planar) 1673 ipu_cpmem_set_uv_offset(outch, 1674 dst_tile->u_off, 1675 dst_tile->v_off); 1676 1677 ipu_idmac_select_buffer(chan->in_chan, 0); 1678 ipu_idmac_select_buffer(outch, 0); 1679 } 1680 } else if (ctx->next_tile < ctx->num_tiles - 1) { 1681 1682 src_tile = &s_image->tile[ctx->next_tile + 1]; 1683 dst_idx = ctx->out_tile_map[ctx->next_tile + 1]; 1684 dst_tile = &d_image->tile[dst_idx]; 1685 1686 ipu_cpmem_set_buffer(chan->in_chan, ctx->cur_buf_num, 1687 s_image->base.phys0 + src_tile->offset); 1688 ipu_cpmem_set_buffer(outch, ctx->cur_buf_num, 1689 d_image->base.phys0 + dst_tile->offset); 1690 1691 ipu_idmac_select_buffer(chan->in_chan, ctx->cur_buf_num); 1692 ipu_idmac_select_buffer(outch, ctx->cur_buf_num); 1693 1694 ctx->cur_buf_num ^= 1; 1695 } 1696 1697 ctx->next_tile++; 1698 return IRQ_HANDLED; 1699 done: 1700 list_add_tail(&run->list, &chan->done_q); 1701 chan->current_run = NULL; 1702 run_next(chan); 1703 return IRQ_WAKE_THREAD; 1704 } 1705 1706 static irqreturn_t norotate_irq(int irq, void *data) 1707 { 1708 struct ipu_image_convert_chan *chan = data; 1709 struct ipu_image_convert_ctx *ctx; 1710 struct ipu_image_convert_run *run; 1711 unsigned long flags; 1712 irqreturn_t ret; 1713 1714 spin_lock_irqsave(&chan->irqlock, flags); 1715 1716 /* get current run and its context */ 1717 run = chan->current_run; 1718 if (!run) { 1719 ret = IRQ_NONE; 1720 goto out; 1721 } 1722 1723 ctx = run->ctx; 1724 1725 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1726 /* this is a rotation operation, just ignore */ 1727 spin_unlock_irqrestore(&chan->irqlock, flags); 1728 return IRQ_HANDLED; 1729 } 1730 1731 ret = do_irq(run); 1732 out: 1733 spin_unlock_irqrestore(&chan->irqlock, flags); 1734 return ret; 1735 } 1736 1737 static irqreturn_t rotate_irq(int irq, void *data) 1738 { 1739 struct ipu_image_convert_chan *chan = data; 1740 struct ipu_image_convert_priv *priv = chan->priv; 1741 struct ipu_image_convert_ctx *ctx; 1742 struct ipu_image_convert_run *run; 1743 unsigned long flags; 1744 irqreturn_t ret; 1745 1746 spin_lock_irqsave(&chan->irqlock, flags); 1747 1748 /* get current run and its context */ 1749 run = chan->current_run; 1750 if (!run) { 1751 ret = IRQ_NONE; 1752 goto out; 1753 } 1754 1755 ctx = run->ctx; 1756 1757 if (!ipu_rot_mode_is_irt(ctx->rot_mode)) { 1758 /* this was NOT a rotation operation, shouldn't happen */ 1759 dev_err(priv->ipu->dev, "Unexpected rotation interrupt\n"); 1760 spin_unlock_irqrestore(&chan->irqlock, flags); 1761 return IRQ_HANDLED; 1762 } 1763 1764 ret = do_irq(run); 1765 out: 1766 spin_unlock_irqrestore(&chan->irqlock, flags); 1767 return ret; 1768 } 1769 1770 /* 1771 * try to force the completion of runs for this ctx. Called when 1772 * abort wait times out in ipu_image_convert_abort(). 1773 */ 1774 static void force_abort(struct ipu_image_convert_ctx *ctx) 1775 { 1776 struct ipu_image_convert_chan *chan = ctx->chan; 1777 struct ipu_image_convert_run *run; 1778 unsigned long flags; 1779 1780 spin_lock_irqsave(&chan->irqlock, flags); 1781 1782 run = chan->current_run; 1783 if (run && run->ctx == ctx) { 1784 convert_stop(run); 1785 run->status = -EIO; 1786 list_add_tail(&run->list, &chan->done_q); 1787 chan->current_run = NULL; 1788 run_next(chan); 1789 } 1790 1791 spin_unlock_irqrestore(&chan->irqlock, flags); 1792 1793 empty_done_q(chan); 1794 } 1795 1796 static void release_ipu_resources(struct ipu_image_convert_chan *chan) 1797 { 1798 if (chan->out_eof_irq >= 0) 1799 free_irq(chan->out_eof_irq, chan); 1800 if (chan->rot_out_eof_irq >= 0) 1801 free_irq(chan->rot_out_eof_irq, chan); 1802 1803 if (!IS_ERR_OR_NULL(chan->in_chan)) 1804 ipu_idmac_put(chan->in_chan); 1805 if (!IS_ERR_OR_NULL(chan->out_chan)) 1806 ipu_idmac_put(chan->out_chan); 1807 if (!IS_ERR_OR_NULL(chan->rotation_in_chan)) 1808 ipu_idmac_put(chan->rotation_in_chan); 1809 if (!IS_ERR_OR_NULL(chan->rotation_out_chan)) 1810 ipu_idmac_put(chan->rotation_out_chan); 1811 if (!IS_ERR_OR_NULL(chan->ic)) 1812 ipu_ic_put(chan->ic); 1813 1814 chan->in_chan = chan->out_chan = chan->rotation_in_chan = 1815 chan->rotation_out_chan = NULL; 1816 chan->out_eof_irq = chan->rot_out_eof_irq = -1; 1817 } 1818 1819 static int get_ipu_resources(struct ipu_image_convert_chan *chan) 1820 { 1821 const struct ipu_image_convert_dma_chan *dma = chan->dma_ch; 1822 struct ipu_image_convert_priv *priv = chan->priv; 1823 int ret; 1824 1825 /* get IC */ 1826 chan->ic = ipu_ic_get(priv->ipu, chan->ic_task); 1827 if (IS_ERR(chan->ic)) { 1828 dev_err(priv->ipu->dev, "could not acquire IC\n"); 1829 ret = PTR_ERR(chan->ic); 1830 goto err; 1831 } 1832 1833 /* get IDMAC channels */ 1834 chan->in_chan = ipu_idmac_get(priv->ipu, dma->in); 1835 chan->out_chan = ipu_idmac_get(priv->ipu, dma->out); 1836 if (IS_ERR(chan->in_chan) || IS_ERR(chan->out_chan)) { 1837 dev_err(priv->ipu->dev, "could not acquire idmac channels\n"); 1838 ret = -EBUSY; 1839 goto err; 1840 } 1841 1842 chan->rotation_in_chan = ipu_idmac_get(priv->ipu, dma->rot_in); 1843 chan->rotation_out_chan = ipu_idmac_get(priv->ipu, dma->rot_out); 1844 if (IS_ERR(chan->rotation_in_chan) || IS_ERR(chan->rotation_out_chan)) { 1845 dev_err(priv->ipu->dev, 1846 "could not acquire idmac rotation channels\n"); 1847 ret = -EBUSY; 1848 goto err; 1849 } 1850 1851 /* acquire the EOF interrupts */ 1852 chan->out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1853 chan->out_chan, 1854 IPU_IRQ_EOF); 1855 1856 ret = request_threaded_irq(chan->out_eof_irq, norotate_irq, do_bh, 1857 0, "ipu-ic", chan); 1858 if (ret < 0) { 1859 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1860 chan->out_eof_irq); 1861 chan->out_eof_irq = -1; 1862 goto err; 1863 } 1864 1865 chan->rot_out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1866 chan->rotation_out_chan, 1867 IPU_IRQ_EOF); 1868 1869 ret = request_threaded_irq(chan->rot_out_eof_irq, rotate_irq, do_bh, 1870 0, "ipu-ic", chan); 1871 if (ret < 0) { 1872 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1873 chan->rot_out_eof_irq); 1874 chan->rot_out_eof_irq = -1; 1875 goto err; 1876 } 1877 1878 return 0; 1879 err: 1880 release_ipu_resources(chan); 1881 return ret; 1882 } 1883 1884 static int fill_image(struct ipu_image_convert_ctx *ctx, 1885 struct ipu_image_convert_image *ic_image, 1886 struct ipu_image *image, 1887 enum ipu_image_convert_type type) 1888 { 1889 struct ipu_image_convert_priv *priv = ctx->chan->priv; 1890 1891 ic_image->base = *image; 1892 ic_image->type = type; 1893 1894 ic_image->fmt = get_format(image->pix.pixelformat); 1895 if (!ic_image->fmt) { 1896 dev_err(priv->ipu->dev, "pixelformat not supported for %s\n", 1897 type == IMAGE_CONVERT_OUT ? "Output" : "Input"); 1898 return -EINVAL; 1899 } 1900 1901 if (ic_image->fmt->planar) 1902 ic_image->stride = ic_image->base.pix.width; 1903 else 1904 ic_image->stride = ic_image->base.pix.bytesperline; 1905 1906 return 0; 1907 } 1908 1909 /* borrowed from drivers/media/v4l2-core/v4l2-common.c */ 1910 static unsigned int clamp_align(unsigned int x, unsigned int min, 1911 unsigned int max, unsigned int align) 1912 { 1913 /* Bits that must be zero to be aligned */ 1914 unsigned int mask = ~((1 << align) - 1); 1915 1916 /* Clamp to aligned min and max */ 1917 x = clamp(x, (min + ~mask) & mask, max & mask); 1918 1919 /* Round to nearest aligned value */ 1920 if (align) 1921 x = (x + (1 << (align - 1))) & mask; 1922 1923 return x; 1924 } 1925 1926 /* Adjusts input/output images to IPU restrictions */ 1927 void ipu_image_convert_adjust(struct ipu_image *in, struct ipu_image *out, 1928 enum ipu_rotate_mode rot_mode) 1929 { 1930 const struct ipu_image_pixfmt *infmt, *outfmt; 1931 u32 w_align_out, h_align_out; 1932 u32 w_align_in, h_align_in; 1933 1934 infmt = get_format(in->pix.pixelformat); 1935 outfmt = get_format(out->pix.pixelformat); 1936 1937 /* set some default pixel formats if needed */ 1938 if (!infmt) { 1939 in->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1940 infmt = get_format(V4L2_PIX_FMT_RGB24); 1941 } 1942 if (!outfmt) { 1943 out->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1944 outfmt = get_format(V4L2_PIX_FMT_RGB24); 1945 } 1946 1947 /* image converter does not handle fields */ 1948 in->pix.field = out->pix.field = V4L2_FIELD_NONE; 1949 1950 /* resizer cannot downsize more than 4:1 */ 1951 if (ipu_rot_mode_is_irt(rot_mode)) { 1952 out->pix.height = max_t(__u32, out->pix.height, 1953 in->pix.width / 4); 1954 out->pix.width = max_t(__u32, out->pix.width, 1955 in->pix.height / 4); 1956 } else { 1957 out->pix.width = max_t(__u32, out->pix.width, 1958 in->pix.width / 4); 1959 out->pix.height = max_t(__u32, out->pix.height, 1960 in->pix.height / 4); 1961 } 1962 1963 /* align input width/height */ 1964 w_align_in = ilog2(tile_width_align(IMAGE_CONVERT_IN, infmt, 1965 rot_mode)); 1966 h_align_in = ilog2(tile_height_align(IMAGE_CONVERT_IN, infmt, 1967 rot_mode)); 1968 in->pix.width = clamp_align(in->pix.width, MIN_W, MAX_W, 1969 w_align_in); 1970 in->pix.height = clamp_align(in->pix.height, MIN_H, MAX_H, 1971 h_align_in); 1972 1973 /* align output width/height */ 1974 w_align_out = ilog2(tile_width_align(IMAGE_CONVERT_OUT, outfmt, 1975 rot_mode)); 1976 h_align_out = ilog2(tile_height_align(IMAGE_CONVERT_OUT, outfmt, 1977 rot_mode)); 1978 out->pix.width = clamp_align(out->pix.width, MIN_W, MAX_W, 1979 w_align_out); 1980 out->pix.height = clamp_align(out->pix.height, MIN_H, MAX_H, 1981 h_align_out); 1982 1983 /* set input/output strides and image sizes */ 1984 in->pix.bytesperline = infmt->planar ? 1985 clamp_align(in->pix.width, 2 << w_align_in, MAX_W, 1986 w_align_in) : 1987 clamp_align((in->pix.width * infmt->bpp) >> 3, 1988 ((2 << w_align_in) * infmt->bpp) >> 3, 1989 (MAX_W * infmt->bpp) >> 3, 1990 w_align_in); 1991 in->pix.sizeimage = infmt->planar ? 1992 (in->pix.height * in->pix.bytesperline * infmt->bpp) >> 3 : 1993 in->pix.height * in->pix.bytesperline; 1994 out->pix.bytesperline = outfmt->planar ? out->pix.width : 1995 (out->pix.width * outfmt->bpp) >> 3; 1996 out->pix.sizeimage = outfmt->planar ? 1997 (out->pix.height * out->pix.bytesperline * outfmt->bpp) >> 3 : 1998 out->pix.height * out->pix.bytesperline; 1999 } 2000 EXPORT_SYMBOL_GPL(ipu_image_convert_adjust); 2001 2002 /* 2003 * this is used by ipu_image_convert_prepare() to verify set input and 2004 * output images are valid before starting the conversion. Clients can 2005 * also call it before calling ipu_image_convert_prepare(). 2006 */ 2007 int ipu_image_convert_verify(struct ipu_image *in, struct ipu_image *out, 2008 enum ipu_rotate_mode rot_mode) 2009 { 2010 struct ipu_image testin, testout; 2011 2012 testin = *in; 2013 testout = *out; 2014 2015 ipu_image_convert_adjust(&testin, &testout, rot_mode); 2016 2017 if (testin.pix.width != in->pix.width || 2018 testin.pix.height != in->pix.height || 2019 testout.pix.width != out->pix.width || 2020 testout.pix.height != out->pix.height) 2021 return -EINVAL; 2022 2023 return 0; 2024 } 2025 EXPORT_SYMBOL_GPL(ipu_image_convert_verify); 2026 2027 /* 2028 * Call ipu_image_convert_prepare() to prepare for the conversion of 2029 * given images and rotation mode. Returns a new conversion context. 2030 */ 2031 struct ipu_image_convert_ctx * 2032 ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 2033 struct ipu_image *in, struct ipu_image *out, 2034 enum ipu_rotate_mode rot_mode, 2035 ipu_image_convert_cb_t complete, 2036 void *complete_context) 2037 { 2038 struct ipu_image_convert_priv *priv = ipu->image_convert_priv; 2039 struct ipu_image_convert_image *s_image, *d_image; 2040 struct ipu_image_convert_chan *chan; 2041 struct ipu_image_convert_ctx *ctx; 2042 unsigned long flags; 2043 unsigned int i; 2044 bool get_res; 2045 int ret; 2046 2047 if (!in || !out || !complete || 2048 (ic_task != IC_TASK_VIEWFINDER && 2049 ic_task != IC_TASK_POST_PROCESSOR)) 2050 return ERR_PTR(-EINVAL); 2051 2052 /* verify the in/out images before continuing */ 2053 ret = ipu_image_convert_verify(in, out, rot_mode); 2054 if (ret) { 2055 dev_err(priv->ipu->dev, "%s: in/out formats invalid\n", 2056 __func__); 2057 return ERR_PTR(ret); 2058 } 2059 2060 chan = &priv->chan[ic_task]; 2061 2062 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 2063 if (!ctx) 2064 return ERR_PTR(-ENOMEM); 2065 2066 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p\n", __func__, 2067 chan->ic_task, ctx); 2068 2069 ctx->chan = chan; 2070 init_completion(&ctx->aborted); 2071 2072 ctx->rot_mode = rot_mode; 2073 2074 /* Sets ctx->in.num_rows/cols as well */ 2075 ret = calc_image_resize_coefficients(ctx, in, out); 2076 if (ret) 2077 goto out_free; 2078 2079 s_image = &ctx->in; 2080 d_image = &ctx->out; 2081 2082 /* set tiling and rotation */ 2083 if (ipu_rot_mode_is_irt(rot_mode)) { 2084 d_image->num_rows = s_image->num_cols; 2085 d_image->num_cols = s_image->num_rows; 2086 } else { 2087 d_image->num_rows = s_image->num_rows; 2088 d_image->num_cols = s_image->num_cols; 2089 } 2090 2091 ctx->num_tiles = d_image->num_cols * d_image->num_rows; 2092 2093 ret = fill_image(ctx, s_image, in, IMAGE_CONVERT_IN); 2094 if (ret) 2095 goto out_free; 2096 ret = fill_image(ctx, d_image, out, IMAGE_CONVERT_OUT); 2097 if (ret) 2098 goto out_free; 2099 2100 calc_out_tile_map(ctx); 2101 2102 find_seams(ctx, s_image, d_image); 2103 2104 ret = calc_tile_dimensions(ctx, s_image); 2105 if (ret) 2106 goto out_free; 2107 2108 ret = calc_tile_offsets(ctx, s_image); 2109 if (ret) 2110 goto out_free; 2111 2112 calc_tile_dimensions(ctx, d_image); 2113 ret = calc_tile_offsets(ctx, d_image); 2114 if (ret) 2115 goto out_free; 2116 2117 calc_tile_resize_coefficients(ctx); 2118 2119 ret = ipu_ic_calc_csc(&ctx->csc, 2120 s_image->base.pix.ycbcr_enc, 2121 s_image->base.pix.quantization, 2122 ipu_pixelformat_to_colorspace(s_image->fmt->fourcc), 2123 d_image->base.pix.ycbcr_enc, 2124 d_image->base.pix.quantization, 2125 ipu_pixelformat_to_colorspace(d_image->fmt->fourcc)); 2126 if (ret) 2127 goto out_free; 2128 2129 dump_format(ctx, s_image); 2130 dump_format(ctx, d_image); 2131 2132 ctx->complete = complete; 2133 ctx->complete_context = complete_context; 2134 2135 /* 2136 * Can we use double-buffering for this operation? If there is 2137 * only one tile (the whole image can be converted in a single 2138 * operation) there's no point in using double-buffering. Also, 2139 * the IPU's IDMAC channels allow only a single U and V plane 2140 * offset shared between both buffers, but these offsets change 2141 * for every tile, and therefore would have to be updated for 2142 * each buffer which is not possible. So double-buffering is 2143 * impossible when either the source or destination images are 2144 * a planar format (YUV420, YUV422P, etc.). Further, differently 2145 * sized tiles or different resizing coefficients per tile 2146 * prevent double-buffering as well. 2147 */ 2148 ctx->double_buffering = (ctx->num_tiles > 1 && 2149 !s_image->fmt->planar && 2150 !d_image->fmt->planar); 2151 for (i = 1; i < ctx->num_tiles; i++) { 2152 if (ctx->in.tile[i].width != ctx->in.tile[0].width || 2153 ctx->in.tile[i].height != ctx->in.tile[0].height || 2154 ctx->out.tile[i].width != ctx->out.tile[0].width || 2155 ctx->out.tile[i].height != ctx->out.tile[0].height) { 2156 ctx->double_buffering = false; 2157 break; 2158 } 2159 } 2160 for (i = 1; i < ctx->in.num_cols; i++) { 2161 if (ctx->resize_coeffs_h[i] != ctx->resize_coeffs_h[0]) { 2162 ctx->double_buffering = false; 2163 break; 2164 } 2165 } 2166 for (i = 1; i < ctx->in.num_rows; i++) { 2167 if (ctx->resize_coeffs_v[i] != ctx->resize_coeffs_v[0]) { 2168 ctx->double_buffering = false; 2169 break; 2170 } 2171 } 2172 2173 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 2174 unsigned long intermediate_size = d_image->tile[0].size; 2175 2176 for (i = 1; i < ctx->num_tiles; i++) { 2177 if (d_image->tile[i].size > intermediate_size) 2178 intermediate_size = d_image->tile[i].size; 2179 } 2180 2181 ret = alloc_dma_buf(priv, &ctx->rot_intermediate[0], 2182 intermediate_size); 2183 if (ret) 2184 goto out_free; 2185 if (ctx->double_buffering) { 2186 ret = alloc_dma_buf(priv, 2187 &ctx->rot_intermediate[1], 2188 intermediate_size); 2189 if (ret) 2190 goto out_free_dmabuf0; 2191 } 2192 } 2193 2194 spin_lock_irqsave(&chan->irqlock, flags); 2195 2196 get_res = list_empty(&chan->ctx_list); 2197 2198 list_add_tail(&ctx->list, &chan->ctx_list); 2199 2200 spin_unlock_irqrestore(&chan->irqlock, flags); 2201 2202 if (get_res) { 2203 ret = get_ipu_resources(chan); 2204 if (ret) 2205 goto out_free_dmabuf1; 2206 } 2207 2208 return ctx; 2209 2210 out_free_dmabuf1: 2211 free_dma_buf(priv, &ctx->rot_intermediate[1]); 2212 spin_lock_irqsave(&chan->irqlock, flags); 2213 list_del(&ctx->list); 2214 spin_unlock_irqrestore(&chan->irqlock, flags); 2215 out_free_dmabuf0: 2216 free_dma_buf(priv, &ctx->rot_intermediate[0]); 2217 out_free: 2218 kfree(ctx); 2219 return ERR_PTR(ret); 2220 } 2221 EXPORT_SYMBOL_GPL(ipu_image_convert_prepare); 2222 2223 /* 2224 * Carry out a single image conversion run. Only the physaddr's of the input 2225 * and output image buffers are needed. The conversion context must have 2226 * been created previously with ipu_image_convert_prepare(). 2227 */ 2228 int ipu_image_convert_queue(struct ipu_image_convert_run *run) 2229 { 2230 struct ipu_image_convert_chan *chan; 2231 struct ipu_image_convert_priv *priv; 2232 struct ipu_image_convert_ctx *ctx; 2233 unsigned long flags; 2234 int ret = 0; 2235 2236 if (!run || !run->ctx || !run->in_phys || !run->out_phys) 2237 return -EINVAL; 2238 2239 ctx = run->ctx; 2240 chan = ctx->chan; 2241 priv = chan->priv; 2242 2243 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p run %p\n", __func__, 2244 chan->ic_task, ctx, run); 2245 2246 INIT_LIST_HEAD(&run->list); 2247 2248 spin_lock_irqsave(&chan->irqlock, flags); 2249 2250 if (ctx->aborting) { 2251 ret = -EIO; 2252 goto unlock; 2253 } 2254 2255 list_add_tail(&run->list, &chan->pending_q); 2256 2257 if (!chan->current_run) { 2258 ret = do_run(run); 2259 if (ret) 2260 chan->current_run = NULL; 2261 } 2262 unlock: 2263 spin_unlock_irqrestore(&chan->irqlock, flags); 2264 return ret; 2265 } 2266 EXPORT_SYMBOL_GPL(ipu_image_convert_queue); 2267 2268 /* Abort any active or pending conversions for this context */ 2269 static void __ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 2270 { 2271 struct ipu_image_convert_chan *chan = ctx->chan; 2272 struct ipu_image_convert_priv *priv = chan->priv; 2273 struct ipu_image_convert_run *run, *active_run, *tmp; 2274 unsigned long flags; 2275 int run_count, ret; 2276 2277 spin_lock_irqsave(&chan->irqlock, flags); 2278 2279 /* move all remaining pending runs in this context to done_q */ 2280 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 2281 if (run->ctx != ctx) 2282 continue; 2283 run->status = -EIO; 2284 list_move_tail(&run->list, &chan->done_q); 2285 } 2286 2287 run_count = get_run_count(ctx, &chan->done_q); 2288 active_run = (chan->current_run && chan->current_run->ctx == ctx) ? 2289 chan->current_run : NULL; 2290 2291 if (active_run) 2292 reinit_completion(&ctx->aborted); 2293 2294 ctx->aborting = true; 2295 2296 spin_unlock_irqrestore(&chan->irqlock, flags); 2297 2298 if (!run_count && !active_run) { 2299 dev_dbg(priv->ipu->dev, 2300 "%s: task %u: no abort needed for ctx %p\n", 2301 __func__, chan->ic_task, ctx); 2302 return; 2303 } 2304 2305 if (!active_run) { 2306 empty_done_q(chan); 2307 return; 2308 } 2309 2310 dev_dbg(priv->ipu->dev, 2311 "%s: task %u: wait for completion: %d runs\n", 2312 __func__, chan->ic_task, run_count); 2313 2314 ret = wait_for_completion_timeout(&ctx->aborted, 2315 msecs_to_jiffies(10000)); 2316 if (ret == 0) { 2317 dev_warn(priv->ipu->dev, "%s: timeout\n", __func__); 2318 force_abort(ctx); 2319 } 2320 } 2321 2322 void ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 2323 { 2324 __ipu_image_convert_abort(ctx); 2325 ctx->aborting = false; 2326 } 2327 EXPORT_SYMBOL_GPL(ipu_image_convert_abort); 2328 2329 /* Unprepare image conversion context */ 2330 void ipu_image_convert_unprepare(struct ipu_image_convert_ctx *ctx) 2331 { 2332 struct ipu_image_convert_chan *chan = ctx->chan; 2333 struct ipu_image_convert_priv *priv = chan->priv; 2334 unsigned long flags; 2335 bool put_res; 2336 2337 /* make sure no runs are hanging around */ 2338 __ipu_image_convert_abort(ctx); 2339 2340 dev_dbg(priv->ipu->dev, "%s: task %u: removing ctx %p\n", __func__, 2341 chan->ic_task, ctx); 2342 2343 spin_lock_irqsave(&chan->irqlock, flags); 2344 2345 list_del(&ctx->list); 2346 2347 put_res = list_empty(&chan->ctx_list); 2348 2349 spin_unlock_irqrestore(&chan->irqlock, flags); 2350 2351 if (put_res) 2352 release_ipu_resources(chan); 2353 2354 free_dma_buf(priv, &ctx->rot_intermediate[1]); 2355 free_dma_buf(priv, &ctx->rot_intermediate[0]); 2356 2357 kfree(ctx); 2358 } 2359 EXPORT_SYMBOL_GPL(ipu_image_convert_unprepare); 2360 2361 /* 2362 * "Canned" asynchronous single image conversion. Allocates and returns 2363 * a new conversion run. On successful return the caller must free the 2364 * run and call ipu_image_convert_unprepare() after conversion completes. 2365 */ 2366 struct ipu_image_convert_run * 2367 ipu_image_convert(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 2368 struct ipu_image *in, struct ipu_image *out, 2369 enum ipu_rotate_mode rot_mode, 2370 ipu_image_convert_cb_t complete, 2371 void *complete_context) 2372 { 2373 struct ipu_image_convert_ctx *ctx; 2374 struct ipu_image_convert_run *run; 2375 int ret; 2376 2377 ctx = ipu_image_convert_prepare(ipu, ic_task, in, out, rot_mode, 2378 complete, complete_context); 2379 if (IS_ERR(ctx)) 2380 return ERR_CAST(ctx); 2381 2382 run = kzalloc(sizeof(*run), GFP_KERNEL); 2383 if (!run) { 2384 ipu_image_convert_unprepare(ctx); 2385 return ERR_PTR(-ENOMEM); 2386 } 2387 2388 run->ctx = ctx; 2389 run->in_phys = in->phys0; 2390 run->out_phys = out->phys0; 2391 2392 ret = ipu_image_convert_queue(run); 2393 if (ret) { 2394 ipu_image_convert_unprepare(ctx); 2395 kfree(run); 2396 return ERR_PTR(ret); 2397 } 2398 2399 return run; 2400 } 2401 EXPORT_SYMBOL_GPL(ipu_image_convert); 2402 2403 /* "Canned" synchronous single image conversion */ 2404 static void image_convert_sync_complete(struct ipu_image_convert_run *run, 2405 void *data) 2406 { 2407 struct completion *comp = data; 2408 2409 complete(comp); 2410 } 2411 2412 int ipu_image_convert_sync(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 2413 struct ipu_image *in, struct ipu_image *out, 2414 enum ipu_rotate_mode rot_mode) 2415 { 2416 struct ipu_image_convert_run *run; 2417 struct completion comp; 2418 int ret; 2419 2420 init_completion(&comp); 2421 2422 run = ipu_image_convert(ipu, ic_task, in, out, rot_mode, 2423 image_convert_sync_complete, &comp); 2424 if (IS_ERR(run)) 2425 return PTR_ERR(run); 2426 2427 ret = wait_for_completion_timeout(&comp, msecs_to_jiffies(10000)); 2428 ret = (ret == 0) ? -ETIMEDOUT : 0; 2429 2430 ipu_image_convert_unprepare(run->ctx); 2431 kfree(run); 2432 2433 return ret; 2434 } 2435 EXPORT_SYMBOL_GPL(ipu_image_convert_sync); 2436 2437 int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev) 2438 { 2439 struct ipu_image_convert_priv *priv; 2440 int i; 2441 2442 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 2443 if (!priv) 2444 return -ENOMEM; 2445 2446 ipu->image_convert_priv = priv; 2447 priv->ipu = ipu; 2448 2449 for (i = 0; i < IC_NUM_TASKS; i++) { 2450 struct ipu_image_convert_chan *chan = &priv->chan[i]; 2451 2452 chan->ic_task = i; 2453 chan->priv = priv; 2454 chan->dma_ch = &image_convert_dma_chan[i]; 2455 chan->out_eof_irq = -1; 2456 chan->rot_out_eof_irq = -1; 2457 2458 spin_lock_init(&chan->irqlock); 2459 INIT_LIST_HEAD(&chan->ctx_list); 2460 INIT_LIST_HEAD(&chan->pending_q); 2461 INIT_LIST_HEAD(&chan->done_q); 2462 } 2463 2464 return 0; 2465 } 2466 2467 void ipu_image_convert_exit(struct ipu_soc *ipu) 2468 { 2469 } 2470