1 /* 2 * Copyright (C) 2012-2016 Mentor Graphics Inc. 3 * 4 * Queued image conversion support, with tiling and rotation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include <linux/interrupt.h> 18 #include <linux/dma-mapping.h> 19 #include <video/imx-ipu-image-convert.h> 20 #include "ipu-prv.h" 21 22 /* 23 * The IC Resizer has a restriction that the output frame from the 24 * resizer must be 1024 or less in both width (pixels) and height 25 * (lines). 26 * 27 * The image converter attempts to split up a conversion when 28 * the desired output (converted) frame resolution exceeds the 29 * IC resizer limit of 1024 in either dimension. 30 * 31 * If either dimension of the output frame exceeds the limit, the 32 * dimension is split into 1, 2, or 4 equal stripes, for a maximum 33 * of 4*4 or 16 tiles. A conversion is then carried out for each 34 * tile (but taking care to pass the full frame stride length to 35 * the DMA channel's parameter memory!). IDMA double-buffering is used 36 * to convert each tile back-to-back when possible (see note below 37 * when double_buffering boolean is set). 38 * 39 * Note that the input frame must be split up into the same number 40 * of tiles as the output frame. 41 * 42 * FIXME: at this point there is no attempt to deal with visible seams 43 * at the tile boundaries when upscaling. The seams are caused by a reset 44 * of the bilinear upscale interpolation when starting a new tile. The 45 * seams are barely visible for small upscale factors, but become 46 * increasingly visible as the upscale factor gets larger, since more 47 * interpolated pixels get thrown out at the tile boundaries. A possilble 48 * fix might be to overlap tiles of different sizes, but this must be done 49 * while also maintaining the IDMAC dma buffer address alignment and 8x8 IRT 50 * alignment restrictions of each tile. 51 */ 52 53 #define MAX_STRIPES_W 4 54 #define MAX_STRIPES_H 4 55 #define MAX_TILES (MAX_STRIPES_W * MAX_STRIPES_H) 56 57 #define MIN_W 16 58 #define MIN_H 8 59 #define MAX_W 4096 60 #define MAX_H 4096 61 62 enum ipu_image_convert_type { 63 IMAGE_CONVERT_IN = 0, 64 IMAGE_CONVERT_OUT, 65 }; 66 67 struct ipu_image_convert_dma_buf { 68 void *virt; 69 dma_addr_t phys; 70 unsigned long len; 71 }; 72 73 struct ipu_image_convert_dma_chan { 74 int in; 75 int out; 76 int rot_in; 77 int rot_out; 78 int vdi_in_p; 79 int vdi_in; 80 int vdi_in_n; 81 }; 82 83 /* dimensions of one tile */ 84 struct ipu_image_tile { 85 u32 width; 86 u32 height; 87 /* size and strides are in bytes */ 88 u32 size; 89 u32 stride; 90 u32 rot_stride; 91 /* start Y or packed offset of this tile */ 92 u32 offset; 93 /* offset from start to tile in U plane, for planar formats */ 94 u32 u_off; 95 /* offset from start to tile in V plane, for planar formats */ 96 u32 v_off; 97 }; 98 99 struct ipu_image_convert_image { 100 struct ipu_image base; 101 enum ipu_image_convert_type type; 102 103 const struct ipu_image_pixfmt *fmt; 104 unsigned int stride; 105 106 /* # of rows (horizontal stripes) if dest height is > 1024 */ 107 unsigned int num_rows; 108 /* # of columns (vertical stripes) if dest width is > 1024 */ 109 unsigned int num_cols; 110 111 struct ipu_image_tile tile[MAX_TILES]; 112 }; 113 114 struct ipu_image_pixfmt { 115 u32 fourcc; /* V4L2 fourcc */ 116 int bpp; /* total bpp */ 117 int uv_width_dec; /* decimation in width for U/V planes */ 118 int uv_height_dec; /* decimation in height for U/V planes */ 119 bool planar; /* planar format */ 120 bool uv_swapped; /* U and V planes are swapped */ 121 bool uv_packed; /* partial planar (U and V in same plane) */ 122 }; 123 124 struct ipu_image_convert_ctx; 125 struct ipu_image_convert_chan; 126 struct ipu_image_convert_priv; 127 128 struct ipu_image_convert_ctx { 129 struct ipu_image_convert_chan *chan; 130 131 ipu_image_convert_cb_t complete; 132 void *complete_context; 133 134 /* Source/destination image data and rotation mode */ 135 struct ipu_image_convert_image in; 136 struct ipu_image_convert_image out; 137 enum ipu_rotate_mode rot_mode; 138 u32 downsize_coeff_h; 139 u32 downsize_coeff_v; 140 u32 image_resize_coeff_h; 141 u32 image_resize_coeff_v; 142 u32 resize_coeffs_h[MAX_STRIPES_W]; 143 u32 resize_coeffs_v[MAX_STRIPES_H]; 144 145 /* intermediate buffer for rotation */ 146 struct ipu_image_convert_dma_buf rot_intermediate[2]; 147 148 /* current buffer number for double buffering */ 149 int cur_buf_num; 150 151 bool aborting; 152 struct completion aborted; 153 154 /* can we use double-buffering for this conversion operation? */ 155 bool double_buffering; 156 /* num_rows * num_cols */ 157 unsigned int num_tiles; 158 /* next tile to process */ 159 unsigned int next_tile; 160 /* where to place converted tile in dest image */ 161 unsigned int out_tile_map[MAX_TILES]; 162 163 struct list_head list; 164 }; 165 166 struct ipu_image_convert_chan { 167 struct ipu_image_convert_priv *priv; 168 169 enum ipu_ic_task ic_task; 170 const struct ipu_image_convert_dma_chan *dma_ch; 171 172 struct ipu_ic *ic; 173 struct ipuv3_channel *in_chan; 174 struct ipuv3_channel *out_chan; 175 struct ipuv3_channel *rotation_in_chan; 176 struct ipuv3_channel *rotation_out_chan; 177 178 /* the IPU end-of-frame irqs */ 179 int out_eof_irq; 180 int rot_out_eof_irq; 181 182 spinlock_t irqlock; 183 184 /* list of convert contexts */ 185 struct list_head ctx_list; 186 /* queue of conversion runs */ 187 struct list_head pending_q; 188 /* queue of completed runs */ 189 struct list_head done_q; 190 191 /* the current conversion run */ 192 struct ipu_image_convert_run *current_run; 193 }; 194 195 struct ipu_image_convert_priv { 196 struct ipu_image_convert_chan chan[IC_NUM_TASKS]; 197 struct ipu_soc *ipu; 198 }; 199 200 static const struct ipu_image_convert_dma_chan 201 image_convert_dma_chan[IC_NUM_TASKS] = { 202 [IC_TASK_VIEWFINDER] = { 203 .in = IPUV3_CHANNEL_MEM_IC_PRP_VF, 204 .out = IPUV3_CHANNEL_IC_PRP_VF_MEM, 205 .rot_in = IPUV3_CHANNEL_MEM_ROT_VF, 206 .rot_out = IPUV3_CHANNEL_ROT_VF_MEM, 207 .vdi_in_p = IPUV3_CHANNEL_MEM_VDI_PREV, 208 .vdi_in = IPUV3_CHANNEL_MEM_VDI_CUR, 209 .vdi_in_n = IPUV3_CHANNEL_MEM_VDI_NEXT, 210 }, 211 [IC_TASK_POST_PROCESSOR] = { 212 .in = IPUV3_CHANNEL_MEM_IC_PP, 213 .out = IPUV3_CHANNEL_IC_PP_MEM, 214 .rot_in = IPUV3_CHANNEL_MEM_ROT_PP, 215 .rot_out = IPUV3_CHANNEL_ROT_PP_MEM, 216 }, 217 }; 218 219 static const struct ipu_image_pixfmt image_convert_formats[] = { 220 { 221 .fourcc = V4L2_PIX_FMT_RGB565, 222 .bpp = 16, 223 }, { 224 .fourcc = V4L2_PIX_FMT_RGB24, 225 .bpp = 24, 226 }, { 227 .fourcc = V4L2_PIX_FMT_BGR24, 228 .bpp = 24, 229 }, { 230 .fourcc = V4L2_PIX_FMT_RGB32, 231 .bpp = 32, 232 }, { 233 .fourcc = V4L2_PIX_FMT_BGR32, 234 .bpp = 32, 235 }, { 236 .fourcc = V4L2_PIX_FMT_XRGB32, 237 .bpp = 32, 238 }, { 239 .fourcc = V4L2_PIX_FMT_XBGR32, 240 .bpp = 32, 241 }, { 242 .fourcc = V4L2_PIX_FMT_YUYV, 243 .bpp = 16, 244 .uv_width_dec = 2, 245 .uv_height_dec = 1, 246 }, { 247 .fourcc = V4L2_PIX_FMT_UYVY, 248 .bpp = 16, 249 .uv_width_dec = 2, 250 .uv_height_dec = 1, 251 }, { 252 .fourcc = V4L2_PIX_FMT_YUV420, 253 .bpp = 12, 254 .planar = true, 255 .uv_width_dec = 2, 256 .uv_height_dec = 2, 257 }, { 258 .fourcc = V4L2_PIX_FMT_YVU420, 259 .bpp = 12, 260 .planar = true, 261 .uv_width_dec = 2, 262 .uv_height_dec = 2, 263 .uv_swapped = true, 264 }, { 265 .fourcc = V4L2_PIX_FMT_NV12, 266 .bpp = 12, 267 .planar = true, 268 .uv_width_dec = 2, 269 .uv_height_dec = 2, 270 .uv_packed = true, 271 }, { 272 .fourcc = V4L2_PIX_FMT_YUV422P, 273 .bpp = 16, 274 .planar = true, 275 .uv_width_dec = 2, 276 .uv_height_dec = 1, 277 }, { 278 .fourcc = V4L2_PIX_FMT_NV16, 279 .bpp = 16, 280 .planar = true, 281 .uv_width_dec = 2, 282 .uv_height_dec = 1, 283 .uv_packed = true, 284 }, 285 }; 286 287 static const struct ipu_image_pixfmt *get_format(u32 fourcc) 288 { 289 const struct ipu_image_pixfmt *ret = NULL; 290 unsigned int i; 291 292 for (i = 0; i < ARRAY_SIZE(image_convert_formats); i++) { 293 if (image_convert_formats[i].fourcc == fourcc) { 294 ret = &image_convert_formats[i]; 295 break; 296 } 297 } 298 299 return ret; 300 } 301 302 static void dump_format(struct ipu_image_convert_ctx *ctx, 303 struct ipu_image_convert_image *ic_image) 304 { 305 struct ipu_image_convert_chan *chan = ctx->chan; 306 struct ipu_image_convert_priv *priv = chan->priv; 307 308 dev_dbg(priv->ipu->dev, 309 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles of size %dx%d), %c%c%c%c\n", 310 chan->ic_task, ctx, 311 ic_image->type == IMAGE_CONVERT_OUT ? "Output" : "Input", 312 ic_image->base.pix.width, ic_image->base.pix.height, 313 ic_image->num_cols, ic_image->num_rows, 314 ic_image->tile[0].width, ic_image->tile[0].height, 315 ic_image->fmt->fourcc & 0xff, 316 (ic_image->fmt->fourcc >> 8) & 0xff, 317 (ic_image->fmt->fourcc >> 16) & 0xff, 318 (ic_image->fmt->fourcc >> 24) & 0xff); 319 } 320 321 int ipu_image_convert_enum_format(int index, u32 *fourcc) 322 { 323 const struct ipu_image_pixfmt *fmt; 324 325 if (index >= (int)ARRAY_SIZE(image_convert_formats)) 326 return -EINVAL; 327 328 /* Format found */ 329 fmt = &image_convert_formats[index]; 330 *fourcc = fmt->fourcc; 331 return 0; 332 } 333 EXPORT_SYMBOL_GPL(ipu_image_convert_enum_format); 334 335 static void free_dma_buf(struct ipu_image_convert_priv *priv, 336 struct ipu_image_convert_dma_buf *buf) 337 { 338 if (buf->virt) 339 dma_free_coherent(priv->ipu->dev, 340 buf->len, buf->virt, buf->phys); 341 buf->virt = NULL; 342 buf->phys = 0; 343 } 344 345 static int alloc_dma_buf(struct ipu_image_convert_priv *priv, 346 struct ipu_image_convert_dma_buf *buf, 347 int size) 348 { 349 buf->len = PAGE_ALIGN(size); 350 buf->virt = dma_alloc_coherent(priv->ipu->dev, buf->len, &buf->phys, 351 GFP_DMA | GFP_KERNEL); 352 if (!buf->virt) { 353 dev_err(priv->ipu->dev, "failed to alloc dma buffer\n"); 354 return -ENOMEM; 355 } 356 357 return 0; 358 } 359 360 static inline int num_stripes(int dim) 361 { 362 if (dim <= 1024) 363 return 1; 364 else if (dim <= 2048) 365 return 2; 366 else 367 return 4; 368 } 369 370 /* 371 * Calculate downsizing coefficients, which are the same for all tiles, 372 * and bilinear resizing coefficients, which are used to find the best 373 * seam positions. 374 */ 375 static int calc_image_resize_coefficients(struct ipu_image_convert_ctx *ctx, 376 struct ipu_image *in, 377 struct ipu_image *out) 378 { 379 u32 downsized_width = in->rect.width; 380 u32 downsized_height = in->rect.height; 381 u32 downsize_coeff_v = 0; 382 u32 downsize_coeff_h = 0; 383 u32 resized_width = out->rect.width; 384 u32 resized_height = out->rect.height; 385 u32 resize_coeff_h; 386 u32 resize_coeff_v; 387 388 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 389 resized_width = out->rect.height; 390 resized_height = out->rect.width; 391 } 392 393 /* Do not let invalid input lead to an endless loop below */ 394 if (WARN_ON(resized_width == 0 || resized_height == 0)) 395 return -EINVAL; 396 397 while (downsized_width >= resized_width * 2) { 398 downsized_width >>= 1; 399 downsize_coeff_h++; 400 } 401 402 while (downsized_height >= resized_height * 2) { 403 downsized_height >>= 1; 404 downsize_coeff_v++; 405 } 406 407 /* 408 * Calculate the bilinear resizing coefficients that could be used if 409 * we were converting with a single tile. The bottom right output pixel 410 * should sample as close as possible to the bottom right input pixel 411 * out of the decimator, but not overshoot it: 412 */ 413 resize_coeff_h = 8192 * (downsized_width - 1) / (resized_width - 1); 414 resize_coeff_v = 8192 * (downsized_height - 1) / (resized_height - 1); 415 416 dev_dbg(ctx->chan->priv->ipu->dev, 417 "%s: hscale: >>%u, *8192/%u vscale: >>%u, *8192/%u, %ux%u tiles\n", 418 __func__, downsize_coeff_h, resize_coeff_h, downsize_coeff_v, 419 resize_coeff_v, ctx->in.num_cols, ctx->in.num_rows); 420 421 if (downsize_coeff_h > 2 || downsize_coeff_v > 2 || 422 resize_coeff_h > 0x3fff || resize_coeff_v > 0x3fff) 423 return -EINVAL; 424 425 ctx->downsize_coeff_h = downsize_coeff_h; 426 ctx->downsize_coeff_v = downsize_coeff_v; 427 ctx->image_resize_coeff_h = resize_coeff_h; 428 ctx->image_resize_coeff_v = resize_coeff_v; 429 430 return 0; 431 } 432 433 static void calc_tile_dimensions(struct ipu_image_convert_ctx *ctx, 434 struct ipu_image_convert_image *image) 435 { 436 int i; 437 438 for (i = 0; i < ctx->num_tiles; i++) { 439 struct ipu_image_tile *tile = &image->tile[i]; 440 441 tile->height = image->base.pix.height / image->num_rows; 442 tile->width = image->base.pix.width / image->num_cols; 443 tile->size = ((tile->height * image->fmt->bpp) >> 3) * 444 tile->width; 445 446 if (image->fmt->planar) { 447 tile->stride = tile->width; 448 tile->rot_stride = tile->height; 449 } else { 450 tile->stride = 451 (image->fmt->bpp * tile->width) >> 3; 452 tile->rot_stride = 453 (image->fmt->bpp * tile->height) >> 3; 454 } 455 } 456 } 457 458 /* 459 * Use the rotation transformation to find the tile coordinates 460 * (row, col) of a tile in the destination frame that corresponds 461 * to the given tile coordinates of a source frame. The destination 462 * coordinate is then converted to a tile index. 463 */ 464 static int transform_tile_index(struct ipu_image_convert_ctx *ctx, 465 int src_row, int src_col) 466 { 467 struct ipu_image_convert_chan *chan = ctx->chan; 468 struct ipu_image_convert_priv *priv = chan->priv; 469 struct ipu_image_convert_image *s_image = &ctx->in; 470 struct ipu_image_convert_image *d_image = &ctx->out; 471 int dst_row, dst_col; 472 473 /* with no rotation it's a 1:1 mapping */ 474 if (ctx->rot_mode == IPU_ROTATE_NONE) 475 return src_row * s_image->num_cols + src_col; 476 477 /* 478 * before doing the transform, first we have to translate 479 * source row,col for an origin in the center of s_image 480 */ 481 src_row = src_row * 2 - (s_image->num_rows - 1); 482 src_col = src_col * 2 - (s_image->num_cols - 1); 483 484 /* do the rotation transform */ 485 if (ctx->rot_mode & IPU_ROT_BIT_90) { 486 dst_col = -src_row; 487 dst_row = src_col; 488 } else { 489 dst_col = src_col; 490 dst_row = src_row; 491 } 492 493 /* apply flip */ 494 if (ctx->rot_mode & IPU_ROT_BIT_HFLIP) 495 dst_col = -dst_col; 496 if (ctx->rot_mode & IPU_ROT_BIT_VFLIP) 497 dst_row = -dst_row; 498 499 dev_dbg(priv->ipu->dev, "task %u: ctx %p: [%d,%d] --> [%d,%d]\n", 500 chan->ic_task, ctx, src_col, src_row, dst_col, dst_row); 501 502 /* 503 * finally translate dest row,col using an origin in upper 504 * left of d_image 505 */ 506 dst_row += d_image->num_rows - 1; 507 dst_col += d_image->num_cols - 1; 508 dst_row /= 2; 509 dst_col /= 2; 510 511 return dst_row * d_image->num_cols + dst_col; 512 } 513 514 /* 515 * Fill the out_tile_map[] with transformed destination tile indeces. 516 */ 517 static void calc_out_tile_map(struct ipu_image_convert_ctx *ctx) 518 { 519 struct ipu_image_convert_image *s_image = &ctx->in; 520 unsigned int row, col, tile = 0; 521 522 for (row = 0; row < s_image->num_rows; row++) { 523 for (col = 0; col < s_image->num_cols; col++) { 524 ctx->out_tile_map[tile] = 525 transform_tile_index(ctx, row, col); 526 tile++; 527 } 528 } 529 } 530 531 static int calc_tile_offsets_planar(struct ipu_image_convert_ctx *ctx, 532 struct ipu_image_convert_image *image) 533 { 534 struct ipu_image_convert_chan *chan = ctx->chan; 535 struct ipu_image_convert_priv *priv = chan->priv; 536 const struct ipu_image_pixfmt *fmt = image->fmt; 537 unsigned int row, col, tile = 0; 538 u32 H, w, h, y_stride, uv_stride; 539 u32 uv_row_off, uv_col_off, uv_off, u_off, v_off, tmp; 540 u32 y_row_off, y_col_off, y_off; 541 u32 y_size, uv_size; 542 543 /* setup some convenience vars */ 544 H = image->base.pix.height; 545 546 y_stride = image->stride; 547 uv_stride = y_stride / fmt->uv_width_dec; 548 if (fmt->uv_packed) 549 uv_stride *= 2; 550 551 y_size = H * y_stride; 552 uv_size = y_size / (fmt->uv_width_dec * fmt->uv_height_dec); 553 554 for (row = 0; row < image->num_rows; row++) { 555 w = image->tile[tile].width; 556 h = image->tile[tile].height; 557 y_row_off = row * h * y_stride; 558 uv_row_off = (row * h * uv_stride) / fmt->uv_height_dec; 559 560 for (col = 0; col < image->num_cols; col++) { 561 y_col_off = col * w; 562 uv_col_off = y_col_off / fmt->uv_width_dec; 563 if (fmt->uv_packed) 564 uv_col_off *= 2; 565 566 y_off = y_row_off + y_col_off; 567 uv_off = uv_row_off + uv_col_off; 568 569 u_off = y_size - y_off + uv_off; 570 v_off = (fmt->uv_packed) ? 0 : u_off + uv_size; 571 if (fmt->uv_swapped) { 572 tmp = u_off; 573 u_off = v_off; 574 v_off = tmp; 575 } 576 577 image->tile[tile].offset = y_off; 578 image->tile[tile].u_off = u_off; 579 image->tile[tile++].v_off = v_off; 580 581 if ((y_off & 0x7) || (u_off & 0x7) || (v_off & 0x7)) { 582 dev_err(priv->ipu->dev, 583 "task %u: ctx %p: %s@[%d,%d]: " 584 "y_off %08x, u_off %08x, v_off %08x\n", 585 chan->ic_task, ctx, 586 image->type == IMAGE_CONVERT_IN ? 587 "Input" : "Output", row, col, 588 y_off, u_off, v_off); 589 return -EINVAL; 590 } 591 } 592 } 593 594 return 0; 595 } 596 597 static int calc_tile_offsets_packed(struct ipu_image_convert_ctx *ctx, 598 struct ipu_image_convert_image *image) 599 { 600 struct ipu_image_convert_chan *chan = ctx->chan; 601 struct ipu_image_convert_priv *priv = chan->priv; 602 const struct ipu_image_pixfmt *fmt = image->fmt; 603 unsigned int row, col, tile = 0; 604 u32 w, h, bpp, stride, offset; 605 u32 row_off, col_off; 606 607 /* setup some convenience vars */ 608 stride = image->stride; 609 bpp = fmt->bpp; 610 611 for (row = 0; row < image->num_rows; row++) { 612 w = image->tile[tile].width; 613 h = image->tile[tile].height; 614 row_off = row * h * stride; 615 616 for (col = 0; col < image->num_cols; col++) { 617 col_off = (col * w * bpp) >> 3; 618 619 offset = row_off + col_off; 620 621 image->tile[tile].offset = offset; 622 image->tile[tile].u_off = 0; 623 image->tile[tile++].v_off = 0; 624 625 if (offset & 0x7) { 626 dev_err(priv->ipu->dev, 627 "task %u: ctx %p: %s@[%d,%d]: " 628 "phys %08x\n", 629 chan->ic_task, ctx, 630 image->type == IMAGE_CONVERT_IN ? 631 "Input" : "Output", row, col, 632 row_off + col_off); 633 return -EINVAL; 634 } 635 } 636 } 637 638 return 0; 639 } 640 641 static int calc_tile_offsets(struct ipu_image_convert_ctx *ctx, 642 struct ipu_image_convert_image *image) 643 { 644 if (image->fmt->planar) 645 return calc_tile_offsets_planar(ctx, image); 646 647 return calc_tile_offsets_packed(ctx, image); 648 } 649 650 /* 651 * Calculate the resizing ratio for the IC main processing section given input 652 * size, fixed downsizing coefficient, and output size. 653 * Either round to closest for the next tile's first pixel to minimize seams 654 * and distortion (for all but right column / bottom row), or round down to 655 * avoid sampling beyond the edges of the input image for this tile's last 656 * pixel. 657 * Returns the resizing coefficient, resizing ratio is 8192.0 / resize_coeff. 658 */ 659 static u32 calc_resize_coeff(u32 input_size, u32 downsize_coeff, 660 u32 output_size, bool allow_overshoot) 661 { 662 u32 downsized = input_size >> downsize_coeff; 663 664 if (allow_overshoot) 665 return DIV_ROUND_CLOSEST(8192 * downsized, output_size); 666 else 667 return 8192 * (downsized - 1) / (output_size - 1); 668 } 669 670 /* 671 * Slightly modify resize coefficients per tile to hide the bilinear 672 * interpolator reset at tile borders, shifting the right / bottom edge 673 * by up to a half input pixel. This removes noticeable seams between 674 * tiles at higher upscaling factors. 675 */ 676 static void calc_tile_resize_coefficients(struct ipu_image_convert_ctx *ctx) 677 { 678 struct ipu_image_convert_chan *chan = ctx->chan; 679 struct ipu_image_convert_priv *priv = chan->priv; 680 struct ipu_image_tile *in_tile, *out_tile; 681 unsigned int col, row, tile_idx; 682 unsigned int last_output; 683 684 for (col = 0; col < ctx->in.num_cols; col++) { 685 bool closest = (col < ctx->in.num_cols - 1) && 686 !(ctx->rot_mode & IPU_ROT_BIT_HFLIP); 687 u32 resized_width; 688 u32 resize_coeff_h; 689 690 tile_idx = col; 691 in_tile = &ctx->in.tile[tile_idx]; 692 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 693 694 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 695 resized_width = out_tile->height; 696 else 697 resized_width = out_tile->width; 698 699 resize_coeff_h = calc_resize_coeff(in_tile->width, 700 ctx->downsize_coeff_h, 701 resized_width, closest); 702 703 dev_dbg(priv->ipu->dev, "%s: column %u hscale: *8192/%u\n", 704 __func__, col, resize_coeff_h); 705 706 707 for (row = 0; row < ctx->in.num_rows; row++) { 708 tile_idx = row * ctx->in.num_cols + col; 709 in_tile = &ctx->in.tile[tile_idx]; 710 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 711 712 /* 713 * With the horizontal scaling factor known, round up 714 * resized width (output width or height) to burst size. 715 */ 716 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 717 out_tile->height = round_up(resized_width, 8); 718 else 719 out_tile->width = round_up(resized_width, 8); 720 721 /* 722 * Calculate input width from the last accessed input 723 * pixel given resized width and scaling coefficients. 724 * Round up to burst size. 725 */ 726 last_output = round_up(resized_width, 8) - 1; 727 if (closest) 728 last_output++; 729 in_tile->width = round_up( 730 (DIV_ROUND_UP(last_output * resize_coeff_h, 731 8192) + 1) 732 << ctx->downsize_coeff_h, 8); 733 } 734 735 ctx->resize_coeffs_h[col] = resize_coeff_h; 736 } 737 738 for (row = 0; row < ctx->in.num_rows; row++) { 739 bool closest = (row < ctx->in.num_rows - 1) && 740 !(ctx->rot_mode & IPU_ROT_BIT_VFLIP); 741 u32 resized_height; 742 u32 resize_coeff_v; 743 744 tile_idx = row * ctx->in.num_cols; 745 in_tile = &ctx->in.tile[tile_idx]; 746 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 747 748 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 749 resized_height = out_tile->width; 750 else 751 resized_height = out_tile->height; 752 753 resize_coeff_v = calc_resize_coeff(in_tile->height, 754 ctx->downsize_coeff_v, 755 resized_height, closest); 756 757 dev_dbg(priv->ipu->dev, "%s: row %u vscale: *8192/%u\n", 758 __func__, row, resize_coeff_v); 759 760 for (col = 0; col < ctx->in.num_cols; col++) { 761 tile_idx = row * ctx->in.num_cols + col; 762 in_tile = &ctx->in.tile[tile_idx]; 763 out_tile = &ctx->out.tile[ctx->out_tile_map[tile_idx]]; 764 765 /* 766 * With the vertical scaling factor known, round up 767 * resized height (output width or height) to IDMAC 768 * limitations. 769 */ 770 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 771 out_tile->width = round_up(resized_height, 2); 772 else 773 out_tile->height = round_up(resized_height, 2); 774 775 /* 776 * Calculate input width from the last accessed input 777 * pixel given resized height and scaling coefficients. 778 * Align to IDMAC restrictions. 779 */ 780 last_output = round_up(resized_height, 2) - 1; 781 if (closest) 782 last_output++; 783 in_tile->height = round_up( 784 (DIV_ROUND_UP(last_output * resize_coeff_v, 785 8192) + 1) 786 << ctx->downsize_coeff_v, 2); 787 } 788 789 ctx->resize_coeffs_v[row] = resize_coeff_v; 790 } 791 } 792 793 /* 794 * return the number of runs in given queue (pending_q or done_q) 795 * for this context. hold irqlock when calling. 796 */ 797 static int get_run_count(struct ipu_image_convert_ctx *ctx, 798 struct list_head *q) 799 { 800 struct ipu_image_convert_run *run; 801 int count = 0; 802 803 lockdep_assert_held(&ctx->chan->irqlock); 804 805 list_for_each_entry(run, q, list) { 806 if (run->ctx == ctx) 807 count++; 808 } 809 810 return count; 811 } 812 813 static void convert_stop(struct ipu_image_convert_run *run) 814 { 815 struct ipu_image_convert_ctx *ctx = run->ctx; 816 struct ipu_image_convert_chan *chan = ctx->chan; 817 struct ipu_image_convert_priv *priv = chan->priv; 818 819 dev_dbg(priv->ipu->dev, "%s: task %u: stopping ctx %p run %p\n", 820 __func__, chan->ic_task, ctx, run); 821 822 /* disable IC tasks and the channels */ 823 ipu_ic_task_disable(chan->ic); 824 ipu_idmac_disable_channel(chan->in_chan); 825 ipu_idmac_disable_channel(chan->out_chan); 826 827 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 828 ipu_idmac_disable_channel(chan->rotation_in_chan); 829 ipu_idmac_disable_channel(chan->rotation_out_chan); 830 ipu_idmac_unlink(chan->out_chan, chan->rotation_in_chan); 831 } 832 833 ipu_ic_disable(chan->ic); 834 } 835 836 static void init_idmac_channel(struct ipu_image_convert_ctx *ctx, 837 struct ipuv3_channel *channel, 838 struct ipu_image_convert_image *image, 839 enum ipu_rotate_mode rot_mode, 840 bool rot_swap_width_height, 841 unsigned int tile) 842 { 843 struct ipu_image_convert_chan *chan = ctx->chan; 844 unsigned int burst_size; 845 u32 width, height, stride; 846 dma_addr_t addr0, addr1 = 0; 847 struct ipu_image tile_image; 848 unsigned int tile_idx[2]; 849 850 if (image->type == IMAGE_CONVERT_OUT) { 851 tile_idx[0] = ctx->out_tile_map[tile]; 852 tile_idx[1] = ctx->out_tile_map[1]; 853 } else { 854 tile_idx[0] = tile; 855 tile_idx[1] = 1; 856 } 857 858 if (rot_swap_width_height) { 859 width = image->tile[tile_idx[0]].height; 860 height = image->tile[tile_idx[0]].width; 861 stride = image->tile[tile_idx[0]].rot_stride; 862 addr0 = ctx->rot_intermediate[0].phys; 863 if (ctx->double_buffering) 864 addr1 = ctx->rot_intermediate[1].phys; 865 } else { 866 width = image->tile[tile_idx[0]].width; 867 height = image->tile[tile_idx[0]].height; 868 stride = image->stride; 869 addr0 = image->base.phys0 + 870 image->tile[tile_idx[0]].offset; 871 if (ctx->double_buffering) 872 addr1 = image->base.phys0 + 873 image->tile[tile_idx[1]].offset; 874 } 875 876 ipu_cpmem_zero(channel); 877 878 memset(&tile_image, 0, sizeof(tile_image)); 879 tile_image.pix.width = tile_image.rect.width = width; 880 tile_image.pix.height = tile_image.rect.height = height; 881 tile_image.pix.bytesperline = stride; 882 tile_image.pix.pixelformat = image->fmt->fourcc; 883 tile_image.phys0 = addr0; 884 tile_image.phys1 = addr1; 885 if (image->fmt->planar && !rot_swap_width_height) { 886 tile_image.u_offset = image->tile[tile_idx[0]].u_off; 887 tile_image.v_offset = image->tile[tile_idx[0]].v_off; 888 } 889 890 ipu_cpmem_set_image(channel, &tile_image); 891 892 if (rot_mode) 893 ipu_cpmem_set_rotation(channel, rot_mode); 894 895 if (channel == chan->rotation_in_chan || 896 channel == chan->rotation_out_chan) { 897 burst_size = 8; 898 ipu_cpmem_set_block_mode(channel); 899 } else 900 burst_size = (width % 16) ? 8 : 16; 901 902 ipu_cpmem_set_burstsize(channel, burst_size); 903 904 ipu_ic_task_idma_init(chan->ic, channel, width, height, 905 burst_size, rot_mode); 906 907 /* 908 * Setting a non-zero AXI ID collides with the PRG AXI snooping, so 909 * only do this when there is no PRG present. 910 */ 911 if (!channel->ipu->prg_priv) 912 ipu_cpmem_set_axi_id(channel, 1); 913 914 ipu_idmac_set_double_buffer(channel, ctx->double_buffering); 915 } 916 917 static int convert_start(struct ipu_image_convert_run *run, unsigned int tile) 918 { 919 struct ipu_image_convert_ctx *ctx = run->ctx; 920 struct ipu_image_convert_chan *chan = ctx->chan; 921 struct ipu_image_convert_priv *priv = chan->priv; 922 struct ipu_image_convert_image *s_image = &ctx->in; 923 struct ipu_image_convert_image *d_image = &ctx->out; 924 enum ipu_color_space src_cs, dest_cs; 925 unsigned int dst_tile = ctx->out_tile_map[tile]; 926 unsigned int dest_width, dest_height; 927 unsigned int col, row; 928 u32 rsc; 929 int ret; 930 931 dev_dbg(priv->ipu->dev, "%s: task %u: starting ctx %p run %p tile %u -> %u\n", 932 __func__, chan->ic_task, ctx, run, tile, dst_tile); 933 934 src_cs = ipu_pixelformat_to_colorspace(s_image->fmt->fourcc); 935 dest_cs = ipu_pixelformat_to_colorspace(d_image->fmt->fourcc); 936 937 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 938 /* swap width/height for resizer */ 939 dest_width = d_image->tile[dst_tile].height; 940 dest_height = d_image->tile[dst_tile].width; 941 } else { 942 dest_width = d_image->tile[dst_tile].width; 943 dest_height = d_image->tile[dst_tile].height; 944 } 945 946 row = tile / s_image->num_cols; 947 col = tile % s_image->num_cols; 948 949 rsc = (ctx->downsize_coeff_v << 30) | 950 (ctx->resize_coeffs_v[row] << 16) | 951 (ctx->downsize_coeff_h << 14) | 952 (ctx->resize_coeffs_h[col]); 953 954 dev_dbg(priv->ipu->dev, "%s: %ux%u -> %ux%u (rsc = 0x%x)\n", 955 __func__, s_image->tile[tile].width, 956 s_image->tile[tile].height, dest_width, dest_height, rsc); 957 958 /* setup the IC resizer and CSC */ 959 ret = ipu_ic_task_init_rsc(chan->ic, 960 s_image->tile[tile].width, 961 s_image->tile[tile].height, 962 dest_width, 963 dest_height, 964 src_cs, dest_cs, 965 rsc); 966 if (ret) { 967 dev_err(priv->ipu->dev, "ipu_ic_task_init failed, %d\n", ret); 968 return ret; 969 } 970 971 /* init the source MEM-->IC PP IDMAC channel */ 972 init_idmac_channel(ctx, chan->in_chan, s_image, 973 IPU_ROTATE_NONE, false, tile); 974 975 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 976 /* init the IC PP-->MEM IDMAC channel */ 977 init_idmac_channel(ctx, chan->out_chan, d_image, 978 IPU_ROTATE_NONE, true, tile); 979 980 /* init the MEM-->IC PP ROT IDMAC channel */ 981 init_idmac_channel(ctx, chan->rotation_in_chan, d_image, 982 ctx->rot_mode, true, tile); 983 984 /* init the destination IC PP ROT-->MEM IDMAC channel */ 985 init_idmac_channel(ctx, chan->rotation_out_chan, d_image, 986 IPU_ROTATE_NONE, false, tile); 987 988 /* now link IC PP-->MEM to MEM-->IC PP ROT */ 989 ipu_idmac_link(chan->out_chan, chan->rotation_in_chan); 990 } else { 991 /* init the destination IC PP-->MEM IDMAC channel */ 992 init_idmac_channel(ctx, chan->out_chan, d_image, 993 ctx->rot_mode, false, tile); 994 } 995 996 /* enable the IC */ 997 ipu_ic_enable(chan->ic); 998 999 /* set buffers ready */ 1000 ipu_idmac_select_buffer(chan->in_chan, 0); 1001 ipu_idmac_select_buffer(chan->out_chan, 0); 1002 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1003 ipu_idmac_select_buffer(chan->rotation_out_chan, 0); 1004 if (ctx->double_buffering) { 1005 ipu_idmac_select_buffer(chan->in_chan, 1); 1006 ipu_idmac_select_buffer(chan->out_chan, 1); 1007 if (ipu_rot_mode_is_irt(ctx->rot_mode)) 1008 ipu_idmac_select_buffer(chan->rotation_out_chan, 1); 1009 } 1010 1011 /* enable the channels! */ 1012 ipu_idmac_enable_channel(chan->in_chan); 1013 ipu_idmac_enable_channel(chan->out_chan); 1014 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1015 ipu_idmac_enable_channel(chan->rotation_in_chan); 1016 ipu_idmac_enable_channel(chan->rotation_out_chan); 1017 } 1018 1019 ipu_ic_task_enable(chan->ic); 1020 1021 ipu_cpmem_dump(chan->in_chan); 1022 ipu_cpmem_dump(chan->out_chan); 1023 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1024 ipu_cpmem_dump(chan->rotation_in_chan); 1025 ipu_cpmem_dump(chan->rotation_out_chan); 1026 } 1027 1028 ipu_dump(priv->ipu); 1029 1030 return 0; 1031 } 1032 1033 /* hold irqlock when calling */ 1034 static int do_run(struct ipu_image_convert_run *run) 1035 { 1036 struct ipu_image_convert_ctx *ctx = run->ctx; 1037 struct ipu_image_convert_chan *chan = ctx->chan; 1038 1039 lockdep_assert_held(&chan->irqlock); 1040 1041 ctx->in.base.phys0 = run->in_phys; 1042 ctx->out.base.phys0 = run->out_phys; 1043 1044 ctx->cur_buf_num = 0; 1045 ctx->next_tile = 1; 1046 1047 /* remove run from pending_q and set as current */ 1048 list_del(&run->list); 1049 chan->current_run = run; 1050 1051 return convert_start(run, 0); 1052 } 1053 1054 /* hold irqlock when calling */ 1055 static void run_next(struct ipu_image_convert_chan *chan) 1056 { 1057 struct ipu_image_convert_priv *priv = chan->priv; 1058 struct ipu_image_convert_run *run, *tmp; 1059 int ret; 1060 1061 lockdep_assert_held(&chan->irqlock); 1062 1063 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 1064 /* skip contexts that are aborting */ 1065 if (run->ctx->aborting) { 1066 dev_dbg(priv->ipu->dev, 1067 "%s: task %u: skipping aborting ctx %p run %p\n", 1068 __func__, chan->ic_task, run->ctx, run); 1069 continue; 1070 } 1071 1072 ret = do_run(run); 1073 if (!ret) 1074 break; 1075 1076 /* 1077 * something went wrong with start, add the run 1078 * to done q and continue to the next run in the 1079 * pending q. 1080 */ 1081 run->status = ret; 1082 list_add_tail(&run->list, &chan->done_q); 1083 chan->current_run = NULL; 1084 } 1085 } 1086 1087 static void empty_done_q(struct ipu_image_convert_chan *chan) 1088 { 1089 struct ipu_image_convert_priv *priv = chan->priv; 1090 struct ipu_image_convert_run *run; 1091 unsigned long flags; 1092 1093 spin_lock_irqsave(&chan->irqlock, flags); 1094 1095 while (!list_empty(&chan->done_q)) { 1096 run = list_entry(chan->done_q.next, 1097 struct ipu_image_convert_run, 1098 list); 1099 1100 list_del(&run->list); 1101 1102 dev_dbg(priv->ipu->dev, 1103 "%s: task %u: completing ctx %p run %p with %d\n", 1104 __func__, chan->ic_task, run->ctx, run, run->status); 1105 1106 /* call the completion callback and free the run */ 1107 spin_unlock_irqrestore(&chan->irqlock, flags); 1108 run->ctx->complete(run, run->ctx->complete_context); 1109 spin_lock_irqsave(&chan->irqlock, flags); 1110 } 1111 1112 spin_unlock_irqrestore(&chan->irqlock, flags); 1113 } 1114 1115 /* 1116 * the bottom half thread clears out the done_q, calling the 1117 * completion handler for each. 1118 */ 1119 static irqreturn_t do_bh(int irq, void *dev_id) 1120 { 1121 struct ipu_image_convert_chan *chan = dev_id; 1122 struct ipu_image_convert_priv *priv = chan->priv; 1123 struct ipu_image_convert_ctx *ctx; 1124 unsigned long flags; 1125 1126 dev_dbg(priv->ipu->dev, "%s: task %u: enter\n", __func__, 1127 chan->ic_task); 1128 1129 empty_done_q(chan); 1130 1131 spin_lock_irqsave(&chan->irqlock, flags); 1132 1133 /* 1134 * the done_q is cleared out, signal any contexts 1135 * that are aborting that abort can complete. 1136 */ 1137 list_for_each_entry(ctx, &chan->ctx_list, list) { 1138 if (ctx->aborting) { 1139 dev_dbg(priv->ipu->dev, 1140 "%s: task %u: signaling abort for ctx %p\n", 1141 __func__, chan->ic_task, ctx); 1142 complete_all(&ctx->aborted); 1143 } 1144 } 1145 1146 spin_unlock_irqrestore(&chan->irqlock, flags); 1147 1148 dev_dbg(priv->ipu->dev, "%s: task %u: exit\n", __func__, 1149 chan->ic_task); 1150 1151 return IRQ_HANDLED; 1152 } 1153 1154 static bool ic_settings_changed(struct ipu_image_convert_ctx *ctx) 1155 { 1156 unsigned int cur_tile = ctx->next_tile - 1; 1157 unsigned int next_tile = ctx->next_tile; 1158 1159 if (ctx->resize_coeffs_h[cur_tile % ctx->in.num_cols] != 1160 ctx->resize_coeffs_h[next_tile % ctx->in.num_cols] || 1161 ctx->resize_coeffs_v[cur_tile / ctx->in.num_cols] != 1162 ctx->resize_coeffs_v[next_tile / ctx->in.num_cols] || 1163 ctx->in.tile[cur_tile].width != ctx->in.tile[next_tile].width || 1164 ctx->in.tile[cur_tile].height != ctx->in.tile[next_tile].height || 1165 ctx->out.tile[cur_tile].width != ctx->out.tile[next_tile].width || 1166 ctx->out.tile[cur_tile].height != ctx->out.tile[next_tile].height) 1167 return true; 1168 1169 return false; 1170 } 1171 1172 /* hold irqlock when calling */ 1173 static irqreturn_t do_irq(struct ipu_image_convert_run *run) 1174 { 1175 struct ipu_image_convert_ctx *ctx = run->ctx; 1176 struct ipu_image_convert_chan *chan = ctx->chan; 1177 struct ipu_image_tile *src_tile, *dst_tile; 1178 struct ipu_image_convert_image *s_image = &ctx->in; 1179 struct ipu_image_convert_image *d_image = &ctx->out; 1180 struct ipuv3_channel *outch; 1181 unsigned int dst_idx; 1182 1183 lockdep_assert_held(&chan->irqlock); 1184 1185 outch = ipu_rot_mode_is_irt(ctx->rot_mode) ? 1186 chan->rotation_out_chan : chan->out_chan; 1187 1188 /* 1189 * It is difficult to stop the channel DMA before the channels 1190 * enter the paused state. Without double-buffering the channels 1191 * are always in a paused state when the EOF irq occurs, so it 1192 * is safe to stop the channels now. For double-buffering we 1193 * just ignore the abort until the operation completes, when it 1194 * is safe to shut down. 1195 */ 1196 if (ctx->aborting && !ctx->double_buffering) { 1197 convert_stop(run); 1198 run->status = -EIO; 1199 goto done; 1200 } 1201 1202 if (ctx->next_tile == ctx->num_tiles) { 1203 /* 1204 * the conversion is complete 1205 */ 1206 convert_stop(run); 1207 run->status = 0; 1208 goto done; 1209 } 1210 1211 /* 1212 * not done, place the next tile buffers. 1213 */ 1214 if (!ctx->double_buffering) { 1215 if (ic_settings_changed(ctx)) { 1216 convert_stop(run); 1217 convert_start(run, ctx->next_tile); 1218 } else { 1219 src_tile = &s_image->tile[ctx->next_tile]; 1220 dst_idx = ctx->out_tile_map[ctx->next_tile]; 1221 dst_tile = &d_image->tile[dst_idx]; 1222 1223 ipu_cpmem_set_buffer(chan->in_chan, 0, 1224 s_image->base.phys0 + 1225 src_tile->offset); 1226 ipu_cpmem_set_buffer(outch, 0, 1227 d_image->base.phys0 + 1228 dst_tile->offset); 1229 if (s_image->fmt->planar) 1230 ipu_cpmem_set_uv_offset(chan->in_chan, 1231 src_tile->u_off, 1232 src_tile->v_off); 1233 if (d_image->fmt->planar) 1234 ipu_cpmem_set_uv_offset(outch, 1235 dst_tile->u_off, 1236 dst_tile->v_off); 1237 1238 ipu_idmac_select_buffer(chan->in_chan, 0); 1239 ipu_idmac_select_buffer(outch, 0); 1240 } 1241 } else if (ctx->next_tile < ctx->num_tiles - 1) { 1242 1243 src_tile = &s_image->tile[ctx->next_tile + 1]; 1244 dst_idx = ctx->out_tile_map[ctx->next_tile + 1]; 1245 dst_tile = &d_image->tile[dst_idx]; 1246 1247 ipu_cpmem_set_buffer(chan->in_chan, ctx->cur_buf_num, 1248 s_image->base.phys0 + src_tile->offset); 1249 ipu_cpmem_set_buffer(outch, ctx->cur_buf_num, 1250 d_image->base.phys0 + dst_tile->offset); 1251 1252 ipu_idmac_select_buffer(chan->in_chan, ctx->cur_buf_num); 1253 ipu_idmac_select_buffer(outch, ctx->cur_buf_num); 1254 1255 ctx->cur_buf_num ^= 1; 1256 } 1257 1258 ctx->next_tile++; 1259 return IRQ_HANDLED; 1260 done: 1261 list_add_tail(&run->list, &chan->done_q); 1262 chan->current_run = NULL; 1263 run_next(chan); 1264 return IRQ_WAKE_THREAD; 1265 } 1266 1267 static irqreturn_t norotate_irq(int irq, void *data) 1268 { 1269 struct ipu_image_convert_chan *chan = data; 1270 struct ipu_image_convert_ctx *ctx; 1271 struct ipu_image_convert_run *run; 1272 unsigned long flags; 1273 irqreturn_t ret; 1274 1275 spin_lock_irqsave(&chan->irqlock, flags); 1276 1277 /* get current run and its context */ 1278 run = chan->current_run; 1279 if (!run) { 1280 ret = IRQ_NONE; 1281 goto out; 1282 } 1283 1284 ctx = run->ctx; 1285 1286 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1287 /* this is a rotation operation, just ignore */ 1288 spin_unlock_irqrestore(&chan->irqlock, flags); 1289 return IRQ_HANDLED; 1290 } 1291 1292 ret = do_irq(run); 1293 out: 1294 spin_unlock_irqrestore(&chan->irqlock, flags); 1295 return ret; 1296 } 1297 1298 static irqreturn_t rotate_irq(int irq, void *data) 1299 { 1300 struct ipu_image_convert_chan *chan = data; 1301 struct ipu_image_convert_priv *priv = chan->priv; 1302 struct ipu_image_convert_ctx *ctx; 1303 struct ipu_image_convert_run *run; 1304 unsigned long flags; 1305 irqreturn_t ret; 1306 1307 spin_lock_irqsave(&chan->irqlock, flags); 1308 1309 /* get current run and its context */ 1310 run = chan->current_run; 1311 if (!run) { 1312 ret = IRQ_NONE; 1313 goto out; 1314 } 1315 1316 ctx = run->ctx; 1317 1318 if (!ipu_rot_mode_is_irt(ctx->rot_mode)) { 1319 /* this was NOT a rotation operation, shouldn't happen */ 1320 dev_err(priv->ipu->dev, "Unexpected rotation interrupt\n"); 1321 spin_unlock_irqrestore(&chan->irqlock, flags); 1322 return IRQ_HANDLED; 1323 } 1324 1325 ret = do_irq(run); 1326 out: 1327 spin_unlock_irqrestore(&chan->irqlock, flags); 1328 return ret; 1329 } 1330 1331 /* 1332 * try to force the completion of runs for this ctx. Called when 1333 * abort wait times out in ipu_image_convert_abort(). 1334 */ 1335 static void force_abort(struct ipu_image_convert_ctx *ctx) 1336 { 1337 struct ipu_image_convert_chan *chan = ctx->chan; 1338 struct ipu_image_convert_run *run; 1339 unsigned long flags; 1340 1341 spin_lock_irqsave(&chan->irqlock, flags); 1342 1343 run = chan->current_run; 1344 if (run && run->ctx == ctx) { 1345 convert_stop(run); 1346 run->status = -EIO; 1347 list_add_tail(&run->list, &chan->done_q); 1348 chan->current_run = NULL; 1349 run_next(chan); 1350 } 1351 1352 spin_unlock_irqrestore(&chan->irqlock, flags); 1353 1354 empty_done_q(chan); 1355 } 1356 1357 static void release_ipu_resources(struct ipu_image_convert_chan *chan) 1358 { 1359 if (chan->out_eof_irq >= 0) 1360 free_irq(chan->out_eof_irq, chan); 1361 if (chan->rot_out_eof_irq >= 0) 1362 free_irq(chan->rot_out_eof_irq, chan); 1363 1364 if (!IS_ERR_OR_NULL(chan->in_chan)) 1365 ipu_idmac_put(chan->in_chan); 1366 if (!IS_ERR_OR_NULL(chan->out_chan)) 1367 ipu_idmac_put(chan->out_chan); 1368 if (!IS_ERR_OR_NULL(chan->rotation_in_chan)) 1369 ipu_idmac_put(chan->rotation_in_chan); 1370 if (!IS_ERR_OR_NULL(chan->rotation_out_chan)) 1371 ipu_idmac_put(chan->rotation_out_chan); 1372 if (!IS_ERR_OR_NULL(chan->ic)) 1373 ipu_ic_put(chan->ic); 1374 1375 chan->in_chan = chan->out_chan = chan->rotation_in_chan = 1376 chan->rotation_out_chan = NULL; 1377 chan->out_eof_irq = chan->rot_out_eof_irq = -1; 1378 } 1379 1380 static int get_ipu_resources(struct ipu_image_convert_chan *chan) 1381 { 1382 const struct ipu_image_convert_dma_chan *dma = chan->dma_ch; 1383 struct ipu_image_convert_priv *priv = chan->priv; 1384 int ret; 1385 1386 /* get IC */ 1387 chan->ic = ipu_ic_get(priv->ipu, chan->ic_task); 1388 if (IS_ERR(chan->ic)) { 1389 dev_err(priv->ipu->dev, "could not acquire IC\n"); 1390 ret = PTR_ERR(chan->ic); 1391 goto err; 1392 } 1393 1394 /* get IDMAC channels */ 1395 chan->in_chan = ipu_idmac_get(priv->ipu, dma->in); 1396 chan->out_chan = ipu_idmac_get(priv->ipu, dma->out); 1397 if (IS_ERR(chan->in_chan) || IS_ERR(chan->out_chan)) { 1398 dev_err(priv->ipu->dev, "could not acquire idmac channels\n"); 1399 ret = -EBUSY; 1400 goto err; 1401 } 1402 1403 chan->rotation_in_chan = ipu_idmac_get(priv->ipu, dma->rot_in); 1404 chan->rotation_out_chan = ipu_idmac_get(priv->ipu, dma->rot_out); 1405 if (IS_ERR(chan->rotation_in_chan) || IS_ERR(chan->rotation_out_chan)) { 1406 dev_err(priv->ipu->dev, 1407 "could not acquire idmac rotation channels\n"); 1408 ret = -EBUSY; 1409 goto err; 1410 } 1411 1412 /* acquire the EOF interrupts */ 1413 chan->out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1414 chan->out_chan, 1415 IPU_IRQ_EOF); 1416 1417 ret = request_threaded_irq(chan->out_eof_irq, norotate_irq, do_bh, 1418 0, "ipu-ic", chan); 1419 if (ret < 0) { 1420 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1421 chan->out_eof_irq); 1422 chan->out_eof_irq = -1; 1423 goto err; 1424 } 1425 1426 chan->rot_out_eof_irq = ipu_idmac_channel_irq(priv->ipu, 1427 chan->rotation_out_chan, 1428 IPU_IRQ_EOF); 1429 1430 ret = request_threaded_irq(chan->rot_out_eof_irq, rotate_irq, do_bh, 1431 0, "ipu-ic", chan); 1432 if (ret < 0) { 1433 dev_err(priv->ipu->dev, "could not acquire irq %d\n", 1434 chan->rot_out_eof_irq); 1435 chan->rot_out_eof_irq = -1; 1436 goto err; 1437 } 1438 1439 return 0; 1440 err: 1441 release_ipu_resources(chan); 1442 return ret; 1443 } 1444 1445 static int fill_image(struct ipu_image_convert_ctx *ctx, 1446 struct ipu_image_convert_image *ic_image, 1447 struct ipu_image *image, 1448 enum ipu_image_convert_type type) 1449 { 1450 struct ipu_image_convert_priv *priv = ctx->chan->priv; 1451 1452 ic_image->base = *image; 1453 ic_image->type = type; 1454 1455 ic_image->fmt = get_format(image->pix.pixelformat); 1456 if (!ic_image->fmt) { 1457 dev_err(priv->ipu->dev, "pixelformat not supported for %s\n", 1458 type == IMAGE_CONVERT_OUT ? "Output" : "Input"); 1459 return -EINVAL; 1460 } 1461 1462 if (ic_image->fmt->planar) 1463 ic_image->stride = ic_image->base.pix.width; 1464 else 1465 ic_image->stride = ic_image->base.pix.bytesperline; 1466 1467 calc_tile_dimensions(ctx, ic_image); 1468 1469 return calc_tile_offsets(ctx, ic_image); 1470 } 1471 1472 /* borrowed from drivers/media/v4l2-core/v4l2-common.c */ 1473 static unsigned int clamp_align(unsigned int x, unsigned int min, 1474 unsigned int max, unsigned int align) 1475 { 1476 /* Bits that must be zero to be aligned */ 1477 unsigned int mask = ~((1 << align) - 1); 1478 1479 /* Clamp to aligned min and max */ 1480 x = clamp(x, (min + ~mask) & mask, max & mask); 1481 1482 /* Round to nearest aligned value */ 1483 if (align) 1484 x = (x + (1 << (align - 1))) & mask; 1485 1486 return x; 1487 } 1488 1489 /* 1490 * We have to adjust the tile width such that the tile physaddrs and 1491 * U and V plane offsets are multiples of 8 bytes as required by 1492 * the IPU DMA Controller. For the planar formats, this corresponds 1493 * to a pixel alignment of 16 (but use a more formal equation since 1494 * the variables are available). For all the packed formats, 8 is 1495 * good enough. 1496 */ 1497 static inline u32 tile_width_align(const struct ipu_image_pixfmt *fmt) 1498 { 1499 return fmt->planar ? 8 * fmt->uv_width_dec : 8; 1500 } 1501 1502 /* 1503 * For tile height alignment, we have to ensure that the output tile 1504 * heights are multiples of 8 lines if the IRT is required by the 1505 * given rotation mode (the IRT performs rotations on 8x8 blocks 1506 * at a time). If the IRT is not used, or for input image tiles, 1507 * 2 lines are good enough. 1508 */ 1509 static inline u32 tile_height_align(enum ipu_image_convert_type type, 1510 enum ipu_rotate_mode rot_mode) 1511 { 1512 return (type == IMAGE_CONVERT_OUT && 1513 ipu_rot_mode_is_irt(rot_mode)) ? 8 : 2; 1514 } 1515 1516 /* Adjusts input/output images to IPU restrictions */ 1517 void ipu_image_convert_adjust(struct ipu_image *in, struct ipu_image *out, 1518 enum ipu_rotate_mode rot_mode) 1519 { 1520 const struct ipu_image_pixfmt *infmt, *outfmt; 1521 unsigned int num_in_rows, num_in_cols; 1522 unsigned int num_out_rows, num_out_cols; 1523 u32 w_align, h_align; 1524 1525 infmt = get_format(in->pix.pixelformat); 1526 outfmt = get_format(out->pix.pixelformat); 1527 1528 /* set some default pixel formats if needed */ 1529 if (!infmt) { 1530 in->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1531 infmt = get_format(V4L2_PIX_FMT_RGB24); 1532 } 1533 if (!outfmt) { 1534 out->pix.pixelformat = V4L2_PIX_FMT_RGB24; 1535 outfmt = get_format(V4L2_PIX_FMT_RGB24); 1536 } 1537 1538 /* image converter does not handle fields */ 1539 in->pix.field = out->pix.field = V4L2_FIELD_NONE; 1540 1541 /* resizer cannot downsize more than 4:1 */ 1542 if (ipu_rot_mode_is_irt(rot_mode)) { 1543 out->pix.height = max_t(__u32, out->pix.height, 1544 in->pix.width / 4); 1545 out->pix.width = max_t(__u32, out->pix.width, 1546 in->pix.height / 4); 1547 } else { 1548 out->pix.width = max_t(__u32, out->pix.width, 1549 in->pix.width / 4); 1550 out->pix.height = max_t(__u32, out->pix.height, 1551 in->pix.height / 4); 1552 } 1553 1554 /* get tiling rows/cols from output format */ 1555 num_out_rows = num_stripes(out->pix.height); 1556 num_out_cols = num_stripes(out->pix.width); 1557 if (ipu_rot_mode_is_irt(rot_mode)) { 1558 num_in_rows = num_out_cols; 1559 num_in_cols = num_out_rows; 1560 } else { 1561 num_in_rows = num_out_rows; 1562 num_in_cols = num_out_cols; 1563 } 1564 1565 /* align input width/height */ 1566 w_align = ilog2(tile_width_align(infmt) * num_in_cols); 1567 h_align = ilog2(tile_height_align(IMAGE_CONVERT_IN, rot_mode) * 1568 num_in_rows); 1569 in->pix.width = clamp_align(in->pix.width, MIN_W, MAX_W, w_align); 1570 in->pix.height = clamp_align(in->pix.height, MIN_H, MAX_H, h_align); 1571 1572 /* align output width/height */ 1573 w_align = ilog2(tile_width_align(outfmt) * num_out_cols); 1574 h_align = ilog2(tile_height_align(IMAGE_CONVERT_OUT, rot_mode) * 1575 num_out_rows); 1576 out->pix.width = clamp_align(out->pix.width, MIN_W, MAX_W, w_align); 1577 out->pix.height = clamp_align(out->pix.height, MIN_H, MAX_H, h_align); 1578 1579 /* set input/output strides and image sizes */ 1580 in->pix.bytesperline = (in->pix.width * infmt->bpp) >> 3; 1581 in->pix.sizeimage = in->pix.height * in->pix.bytesperline; 1582 out->pix.bytesperline = (out->pix.width * outfmt->bpp) >> 3; 1583 out->pix.sizeimage = out->pix.height * out->pix.bytesperline; 1584 } 1585 EXPORT_SYMBOL_GPL(ipu_image_convert_adjust); 1586 1587 /* 1588 * this is used by ipu_image_convert_prepare() to verify set input and 1589 * output images are valid before starting the conversion. Clients can 1590 * also call it before calling ipu_image_convert_prepare(). 1591 */ 1592 int ipu_image_convert_verify(struct ipu_image *in, struct ipu_image *out, 1593 enum ipu_rotate_mode rot_mode) 1594 { 1595 struct ipu_image testin, testout; 1596 1597 testin = *in; 1598 testout = *out; 1599 1600 ipu_image_convert_adjust(&testin, &testout, rot_mode); 1601 1602 if (testin.pix.width != in->pix.width || 1603 testin.pix.height != in->pix.height || 1604 testout.pix.width != out->pix.width || 1605 testout.pix.height != out->pix.height) 1606 return -EINVAL; 1607 1608 return 0; 1609 } 1610 EXPORT_SYMBOL_GPL(ipu_image_convert_verify); 1611 1612 /* 1613 * Call ipu_image_convert_prepare() to prepare for the conversion of 1614 * given images and rotation mode. Returns a new conversion context. 1615 */ 1616 struct ipu_image_convert_ctx * 1617 ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1618 struct ipu_image *in, struct ipu_image *out, 1619 enum ipu_rotate_mode rot_mode, 1620 ipu_image_convert_cb_t complete, 1621 void *complete_context) 1622 { 1623 struct ipu_image_convert_priv *priv = ipu->image_convert_priv; 1624 struct ipu_image_convert_image *s_image, *d_image; 1625 struct ipu_image_convert_chan *chan; 1626 struct ipu_image_convert_ctx *ctx; 1627 unsigned long flags; 1628 bool get_res; 1629 int ret; 1630 1631 if (!in || !out || !complete || 1632 (ic_task != IC_TASK_VIEWFINDER && 1633 ic_task != IC_TASK_POST_PROCESSOR)) 1634 return ERR_PTR(-EINVAL); 1635 1636 /* verify the in/out images before continuing */ 1637 ret = ipu_image_convert_verify(in, out, rot_mode); 1638 if (ret) { 1639 dev_err(priv->ipu->dev, "%s: in/out formats invalid\n", 1640 __func__); 1641 return ERR_PTR(ret); 1642 } 1643 1644 chan = &priv->chan[ic_task]; 1645 1646 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 1647 if (!ctx) 1648 return ERR_PTR(-ENOMEM); 1649 1650 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p\n", __func__, 1651 chan->ic_task, ctx); 1652 1653 ctx->chan = chan; 1654 init_completion(&ctx->aborted); 1655 1656 s_image = &ctx->in; 1657 d_image = &ctx->out; 1658 1659 /* set tiling and rotation */ 1660 d_image->num_rows = num_stripes(out->pix.height); 1661 d_image->num_cols = num_stripes(out->pix.width); 1662 if (ipu_rot_mode_is_irt(rot_mode)) { 1663 s_image->num_rows = d_image->num_cols; 1664 s_image->num_cols = d_image->num_rows; 1665 } else { 1666 s_image->num_rows = d_image->num_rows; 1667 s_image->num_cols = d_image->num_cols; 1668 } 1669 1670 ctx->num_tiles = d_image->num_cols * d_image->num_rows; 1671 ctx->rot_mode = rot_mode; 1672 1673 ret = calc_image_resize_coefficients(ctx, in, out); 1674 if (ret) 1675 goto out_free; 1676 1677 ret = fill_image(ctx, s_image, in, IMAGE_CONVERT_IN); 1678 if (ret) 1679 goto out_free; 1680 ret = fill_image(ctx, d_image, out, IMAGE_CONVERT_OUT); 1681 if (ret) 1682 goto out_free; 1683 1684 calc_out_tile_map(ctx); 1685 calc_tile_resize_coefficients(ctx); 1686 1687 dump_format(ctx, s_image); 1688 dump_format(ctx, d_image); 1689 1690 ctx->complete = complete; 1691 ctx->complete_context = complete_context; 1692 1693 /* 1694 * Can we use double-buffering for this operation? If there is 1695 * only one tile (the whole image can be converted in a single 1696 * operation) there's no point in using double-buffering. Also, 1697 * the IPU's IDMAC channels allow only a single U and V plane 1698 * offset shared between both buffers, but these offsets change 1699 * for every tile, and therefore would have to be updated for 1700 * each buffer which is not possible. So double-buffering is 1701 * impossible when either the source or destination images are 1702 * a planar format (YUV420, YUV422P, etc.). 1703 */ 1704 ctx->double_buffering = (ctx->num_tiles > 1 && 1705 !s_image->fmt->planar && 1706 !d_image->fmt->planar); 1707 1708 if (ipu_rot_mode_is_irt(ctx->rot_mode)) { 1709 unsigned long intermediate_size = d_image->tile[0].size; 1710 unsigned int i; 1711 1712 for (i = 1; i < ctx->num_tiles; i++) { 1713 if (d_image->tile[i].size > intermediate_size) 1714 intermediate_size = d_image->tile[i].size; 1715 } 1716 1717 ret = alloc_dma_buf(priv, &ctx->rot_intermediate[0], 1718 intermediate_size); 1719 if (ret) 1720 goto out_free; 1721 if (ctx->double_buffering) { 1722 ret = alloc_dma_buf(priv, 1723 &ctx->rot_intermediate[1], 1724 intermediate_size); 1725 if (ret) 1726 goto out_free_dmabuf0; 1727 } 1728 } 1729 1730 spin_lock_irqsave(&chan->irqlock, flags); 1731 1732 get_res = list_empty(&chan->ctx_list); 1733 1734 list_add_tail(&ctx->list, &chan->ctx_list); 1735 1736 spin_unlock_irqrestore(&chan->irqlock, flags); 1737 1738 if (get_res) { 1739 ret = get_ipu_resources(chan); 1740 if (ret) 1741 goto out_free_dmabuf1; 1742 } 1743 1744 return ctx; 1745 1746 out_free_dmabuf1: 1747 free_dma_buf(priv, &ctx->rot_intermediate[1]); 1748 spin_lock_irqsave(&chan->irqlock, flags); 1749 list_del(&ctx->list); 1750 spin_unlock_irqrestore(&chan->irqlock, flags); 1751 out_free_dmabuf0: 1752 free_dma_buf(priv, &ctx->rot_intermediate[0]); 1753 out_free: 1754 kfree(ctx); 1755 return ERR_PTR(ret); 1756 } 1757 EXPORT_SYMBOL_GPL(ipu_image_convert_prepare); 1758 1759 /* 1760 * Carry out a single image conversion run. Only the physaddr's of the input 1761 * and output image buffers are needed. The conversion context must have 1762 * been created previously with ipu_image_convert_prepare(). 1763 */ 1764 int ipu_image_convert_queue(struct ipu_image_convert_run *run) 1765 { 1766 struct ipu_image_convert_chan *chan; 1767 struct ipu_image_convert_priv *priv; 1768 struct ipu_image_convert_ctx *ctx; 1769 unsigned long flags; 1770 int ret = 0; 1771 1772 if (!run || !run->ctx || !run->in_phys || !run->out_phys) 1773 return -EINVAL; 1774 1775 ctx = run->ctx; 1776 chan = ctx->chan; 1777 priv = chan->priv; 1778 1779 dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p run %p\n", __func__, 1780 chan->ic_task, ctx, run); 1781 1782 INIT_LIST_HEAD(&run->list); 1783 1784 spin_lock_irqsave(&chan->irqlock, flags); 1785 1786 if (ctx->aborting) { 1787 ret = -EIO; 1788 goto unlock; 1789 } 1790 1791 list_add_tail(&run->list, &chan->pending_q); 1792 1793 if (!chan->current_run) { 1794 ret = do_run(run); 1795 if (ret) 1796 chan->current_run = NULL; 1797 } 1798 unlock: 1799 spin_unlock_irqrestore(&chan->irqlock, flags); 1800 return ret; 1801 } 1802 EXPORT_SYMBOL_GPL(ipu_image_convert_queue); 1803 1804 /* Abort any active or pending conversions for this context */ 1805 static void __ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 1806 { 1807 struct ipu_image_convert_chan *chan = ctx->chan; 1808 struct ipu_image_convert_priv *priv = chan->priv; 1809 struct ipu_image_convert_run *run, *active_run, *tmp; 1810 unsigned long flags; 1811 int run_count, ret; 1812 1813 spin_lock_irqsave(&chan->irqlock, flags); 1814 1815 /* move all remaining pending runs in this context to done_q */ 1816 list_for_each_entry_safe(run, tmp, &chan->pending_q, list) { 1817 if (run->ctx != ctx) 1818 continue; 1819 run->status = -EIO; 1820 list_move_tail(&run->list, &chan->done_q); 1821 } 1822 1823 run_count = get_run_count(ctx, &chan->done_q); 1824 active_run = (chan->current_run && chan->current_run->ctx == ctx) ? 1825 chan->current_run : NULL; 1826 1827 if (active_run) 1828 reinit_completion(&ctx->aborted); 1829 1830 ctx->aborting = true; 1831 1832 spin_unlock_irqrestore(&chan->irqlock, flags); 1833 1834 if (!run_count && !active_run) { 1835 dev_dbg(priv->ipu->dev, 1836 "%s: task %u: no abort needed for ctx %p\n", 1837 __func__, chan->ic_task, ctx); 1838 return; 1839 } 1840 1841 if (!active_run) { 1842 empty_done_q(chan); 1843 return; 1844 } 1845 1846 dev_dbg(priv->ipu->dev, 1847 "%s: task %u: wait for completion: %d runs\n", 1848 __func__, chan->ic_task, run_count); 1849 1850 ret = wait_for_completion_timeout(&ctx->aborted, 1851 msecs_to_jiffies(10000)); 1852 if (ret == 0) { 1853 dev_warn(priv->ipu->dev, "%s: timeout\n", __func__); 1854 force_abort(ctx); 1855 } 1856 } 1857 1858 void ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx) 1859 { 1860 __ipu_image_convert_abort(ctx); 1861 ctx->aborting = false; 1862 } 1863 EXPORT_SYMBOL_GPL(ipu_image_convert_abort); 1864 1865 /* Unprepare image conversion context */ 1866 void ipu_image_convert_unprepare(struct ipu_image_convert_ctx *ctx) 1867 { 1868 struct ipu_image_convert_chan *chan = ctx->chan; 1869 struct ipu_image_convert_priv *priv = chan->priv; 1870 unsigned long flags; 1871 bool put_res; 1872 1873 /* make sure no runs are hanging around */ 1874 __ipu_image_convert_abort(ctx); 1875 1876 dev_dbg(priv->ipu->dev, "%s: task %u: removing ctx %p\n", __func__, 1877 chan->ic_task, ctx); 1878 1879 spin_lock_irqsave(&chan->irqlock, flags); 1880 1881 list_del(&ctx->list); 1882 1883 put_res = list_empty(&chan->ctx_list); 1884 1885 spin_unlock_irqrestore(&chan->irqlock, flags); 1886 1887 if (put_res) 1888 release_ipu_resources(chan); 1889 1890 free_dma_buf(priv, &ctx->rot_intermediate[1]); 1891 free_dma_buf(priv, &ctx->rot_intermediate[0]); 1892 1893 kfree(ctx); 1894 } 1895 EXPORT_SYMBOL_GPL(ipu_image_convert_unprepare); 1896 1897 /* 1898 * "Canned" asynchronous single image conversion. Allocates and returns 1899 * a new conversion run. On successful return the caller must free the 1900 * run and call ipu_image_convert_unprepare() after conversion completes. 1901 */ 1902 struct ipu_image_convert_run * 1903 ipu_image_convert(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1904 struct ipu_image *in, struct ipu_image *out, 1905 enum ipu_rotate_mode rot_mode, 1906 ipu_image_convert_cb_t complete, 1907 void *complete_context) 1908 { 1909 struct ipu_image_convert_ctx *ctx; 1910 struct ipu_image_convert_run *run; 1911 int ret; 1912 1913 ctx = ipu_image_convert_prepare(ipu, ic_task, in, out, rot_mode, 1914 complete, complete_context); 1915 if (IS_ERR(ctx)) 1916 return ERR_CAST(ctx); 1917 1918 run = kzalloc(sizeof(*run), GFP_KERNEL); 1919 if (!run) { 1920 ipu_image_convert_unprepare(ctx); 1921 return ERR_PTR(-ENOMEM); 1922 } 1923 1924 run->ctx = ctx; 1925 run->in_phys = in->phys0; 1926 run->out_phys = out->phys0; 1927 1928 ret = ipu_image_convert_queue(run); 1929 if (ret) { 1930 ipu_image_convert_unprepare(ctx); 1931 kfree(run); 1932 return ERR_PTR(ret); 1933 } 1934 1935 return run; 1936 } 1937 EXPORT_SYMBOL_GPL(ipu_image_convert); 1938 1939 /* "Canned" synchronous single image conversion */ 1940 static void image_convert_sync_complete(struct ipu_image_convert_run *run, 1941 void *data) 1942 { 1943 struct completion *comp = data; 1944 1945 complete(comp); 1946 } 1947 1948 int ipu_image_convert_sync(struct ipu_soc *ipu, enum ipu_ic_task ic_task, 1949 struct ipu_image *in, struct ipu_image *out, 1950 enum ipu_rotate_mode rot_mode) 1951 { 1952 struct ipu_image_convert_run *run; 1953 struct completion comp; 1954 int ret; 1955 1956 init_completion(&comp); 1957 1958 run = ipu_image_convert(ipu, ic_task, in, out, rot_mode, 1959 image_convert_sync_complete, &comp); 1960 if (IS_ERR(run)) 1961 return PTR_ERR(run); 1962 1963 ret = wait_for_completion_timeout(&comp, msecs_to_jiffies(10000)); 1964 ret = (ret == 0) ? -ETIMEDOUT : 0; 1965 1966 ipu_image_convert_unprepare(run->ctx); 1967 kfree(run); 1968 1969 return ret; 1970 } 1971 EXPORT_SYMBOL_GPL(ipu_image_convert_sync); 1972 1973 int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev) 1974 { 1975 struct ipu_image_convert_priv *priv; 1976 int i; 1977 1978 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1979 if (!priv) 1980 return -ENOMEM; 1981 1982 ipu->image_convert_priv = priv; 1983 priv->ipu = ipu; 1984 1985 for (i = 0; i < IC_NUM_TASKS; i++) { 1986 struct ipu_image_convert_chan *chan = &priv->chan[i]; 1987 1988 chan->ic_task = i; 1989 chan->priv = priv; 1990 chan->dma_ch = &image_convert_dma_chan[i]; 1991 chan->out_eof_irq = -1; 1992 chan->rot_out_eof_irq = -1; 1993 1994 spin_lock_init(&chan->irqlock); 1995 INIT_LIST_HEAD(&chan->ctx_list); 1996 INIT_LIST_HEAD(&chan->pending_q); 1997 INIT_LIST_HEAD(&chan->done_q); 1998 } 1999 2000 return 0; 2001 } 2002 2003 void ipu_image_convert_exit(struct ipu_soc *ipu) 2004 { 2005 } 2006