1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2012-2014 Mentor Graphics Inc. 4 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved. 5 */ 6 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/errno.h> 10 #include <linux/spinlock.h> 11 #include <linux/bitrev.h> 12 #include <linux/io.h> 13 #include <linux/err.h> 14 #include <linux/sizes.h> 15 #include "ipu-prv.h" 16 17 /* IC Register Offsets */ 18 #define IC_CONF 0x0000 19 #define IC_PRP_ENC_RSC 0x0004 20 #define IC_PRP_VF_RSC 0x0008 21 #define IC_PP_RSC 0x000C 22 #define IC_CMBP_1 0x0010 23 #define IC_CMBP_2 0x0014 24 #define IC_IDMAC_1 0x0018 25 #define IC_IDMAC_2 0x001C 26 #define IC_IDMAC_3 0x0020 27 #define IC_IDMAC_4 0x0024 28 29 /* IC Register Fields */ 30 #define IC_CONF_PRPENC_EN (1 << 0) 31 #define IC_CONF_PRPENC_CSC1 (1 << 1) 32 #define IC_CONF_PRPENC_ROT_EN (1 << 2) 33 #define IC_CONF_PRPVF_EN (1 << 8) 34 #define IC_CONF_PRPVF_CSC1 (1 << 9) 35 #define IC_CONF_PRPVF_CSC2 (1 << 10) 36 #define IC_CONF_PRPVF_CMB (1 << 11) 37 #define IC_CONF_PRPVF_ROT_EN (1 << 12) 38 #define IC_CONF_PP_EN (1 << 16) 39 #define IC_CONF_PP_CSC1 (1 << 17) 40 #define IC_CONF_PP_CSC2 (1 << 18) 41 #define IC_CONF_PP_CMB (1 << 19) 42 #define IC_CONF_PP_ROT_EN (1 << 20) 43 #define IC_CONF_IC_GLB_LOC_A (1 << 28) 44 #define IC_CONF_KEY_COLOR_EN (1 << 29) 45 #define IC_CONF_RWS_EN (1 << 30) 46 #define IC_CONF_CSI_MEM_WR_EN (1 << 31) 47 48 #define IC_IDMAC_1_CB0_BURST_16 (1 << 0) 49 #define IC_IDMAC_1_CB1_BURST_16 (1 << 1) 50 #define IC_IDMAC_1_CB2_BURST_16 (1 << 2) 51 #define IC_IDMAC_1_CB3_BURST_16 (1 << 3) 52 #define IC_IDMAC_1_CB4_BURST_16 (1 << 4) 53 #define IC_IDMAC_1_CB5_BURST_16 (1 << 5) 54 #define IC_IDMAC_1_CB6_BURST_16 (1 << 6) 55 #define IC_IDMAC_1_CB7_BURST_16 (1 << 7) 56 #define IC_IDMAC_1_PRPENC_ROT_MASK (0x7 << 11) 57 #define IC_IDMAC_1_PRPENC_ROT_OFFSET 11 58 #define IC_IDMAC_1_PRPVF_ROT_MASK (0x7 << 14) 59 #define IC_IDMAC_1_PRPVF_ROT_OFFSET 14 60 #define IC_IDMAC_1_PP_ROT_MASK (0x7 << 17) 61 #define IC_IDMAC_1_PP_ROT_OFFSET 17 62 #define IC_IDMAC_1_PP_FLIP_RS (1 << 22) 63 #define IC_IDMAC_1_PRPVF_FLIP_RS (1 << 21) 64 #define IC_IDMAC_1_PRPENC_FLIP_RS (1 << 20) 65 66 #define IC_IDMAC_2_PRPENC_HEIGHT_MASK (0x3ff << 0) 67 #define IC_IDMAC_2_PRPENC_HEIGHT_OFFSET 0 68 #define IC_IDMAC_2_PRPVF_HEIGHT_MASK (0x3ff << 10) 69 #define IC_IDMAC_2_PRPVF_HEIGHT_OFFSET 10 70 #define IC_IDMAC_2_PP_HEIGHT_MASK (0x3ff << 20) 71 #define IC_IDMAC_2_PP_HEIGHT_OFFSET 20 72 73 #define IC_IDMAC_3_PRPENC_WIDTH_MASK (0x3ff << 0) 74 #define IC_IDMAC_3_PRPENC_WIDTH_OFFSET 0 75 #define IC_IDMAC_3_PRPVF_WIDTH_MASK (0x3ff << 10) 76 #define IC_IDMAC_3_PRPVF_WIDTH_OFFSET 10 77 #define IC_IDMAC_3_PP_WIDTH_MASK (0x3ff << 20) 78 #define IC_IDMAC_3_PP_WIDTH_OFFSET 20 79 80 struct ic_task_regoffs { 81 u32 rsc; 82 u32 tpmem_csc[2]; 83 }; 84 85 struct ic_task_bitfields { 86 u32 ic_conf_en; 87 u32 ic_conf_rot_en; 88 u32 ic_conf_cmb_en; 89 u32 ic_conf_csc1_en; 90 u32 ic_conf_csc2_en; 91 u32 ic_cmb_galpha_bit; 92 }; 93 94 static const struct ic_task_regoffs ic_task_reg[IC_NUM_TASKS] = { 95 [IC_TASK_ENCODER] = { 96 .rsc = IC_PRP_ENC_RSC, 97 .tpmem_csc = {0x2008, 0}, 98 }, 99 [IC_TASK_VIEWFINDER] = { 100 .rsc = IC_PRP_VF_RSC, 101 .tpmem_csc = {0x4028, 0x4040}, 102 }, 103 [IC_TASK_POST_PROCESSOR] = { 104 .rsc = IC_PP_RSC, 105 .tpmem_csc = {0x6060, 0x6078}, 106 }, 107 }; 108 109 static const struct ic_task_bitfields ic_task_bit[IC_NUM_TASKS] = { 110 [IC_TASK_ENCODER] = { 111 .ic_conf_en = IC_CONF_PRPENC_EN, 112 .ic_conf_rot_en = IC_CONF_PRPENC_ROT_EN, 113 .ic_conf_cmb_en = 0, /* NA */ 114 .ic_conf_csc1_en = IC_CONF_PRPENC_CSC1, 115 .ic_conf_csc2_en = 0, /* NA */ 116 .ic_cmb_galpha_bit = 0, /* NA */ 117 }, 118 [IC_TASK_VIEWFINDER] = { 119 .ic_conf_en = IC_CONF_PRPVF_EN, 120 .ic_conf_rot_en = IC_CONF_PRPVF_ROT_EN, 121 .ic_conf_cmb_en = IC_CONF_PRPVF_CMB, 122 .ic_conf_csc1_en = IC_CONF_PRPVF_CSC1, 123 .ic_conf_csc2_en = IC_CONF_PRPVF_CSC2, 124 .ic_cmb_galpha_bit = 0, 125 }, 126 [IC_TASK_POST_PROCESSOR] = { 127 .ic_conf_en = IC_CONF_PP_EN, 128 .ic_conf_rot_en = IC_CONF_PP_ROT_EN, 129 .ic_conf_cmb_en = IC_CONF_PP_CMB, 130 .ic_conf_csc1_en = IC_CONF_PP_CSC1, 131 .ic_conf_csc2_en = IC_CONF_PP_CSC2, 132 .ic_cmb_galpha_bit = 8, 133 }, 134 }; 135 136 struct ipu_ic_priv; 137 138 struct ipu_ic { 139 enum ipu_ic_task task; 140 const struct ic_task_regoffs *reg; 141 const struct ic_task_bitfields *bit; 142 143 enum ipu_color_space in_cs, g_in_cs; 144 enum ipu_color_space out_cs; 145 bool graphics; 146 bool rotation; 147 bool in_use; 148 149 struct ipu_ic_priv *priv; 150 }; 151 152 struct ipu_ic_priv { 153 void __iomem *base; 154 void __iomem *tpmem_base; 155 spinlock_t lock; 156 struct ipu_soc *ipu; 157 int use_count; 158 int irt_use_count; 159 struct ipu_ic task[IC_NUM_TASKS]; 160 }; 161 162 static inline u32 ipu_ic_read(struct ipu_ic *ic, unsigned offset) 163 { 164 return readl(ic->priv->base + offset); 165 } 166 167 static inline void ipu_ic_write(struct ipu_ic *ic, u32 value, unsigned offset) 168 { 169 writel(value, ic->priv->base + offset); 170 } 171 172 struct ic_csc_params { 173 s16 coeff[3][3]; /* signed 9-bit integer coefficients */ 174 s16 offset[3]; /* signed 11+2-bit fixed point offset */ 175 u8 scale:2; /* scale coefficients * 2^(scale-1) */ 176 bool sat:1; /* saturate to (16, 235(Y) / 240(U, V)) */ 177 }; 178 179 /* 180 * Y = R * .299 + G * .587 + B * .114; 181 * U = R * -.169 + G * -.332 + B * .500 + 128.; 182 * V = R * .500 + G * -.419 + B * -.0813 + 128.; 183 */ 184 static const struct ic_csc_params ic_csc_rgb2ycbcr = { 185 .coeff = { 186 { 77, 150, 29 }, 187 { 469, 427, 128 }, 188 { 128, 405, 491 }, 189 }, 190 .offset = { 0, 512, 512 }, 191 .scale = 1, 192 }; 193 194 /* transparent RGB->RGB matrix for graphics combining */ 195 static const struct ic_csc_params ic_csc_rgb2rgb = { 196 .coeff = { 197 { 128, 0, 0 }, 198 { 0, 128, 0 }, 199 { 0, 0, 128 }, 200 }, 201 .scale = 2, 202 }; 203 204 /* 205 * R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128)); 206 * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); 207 * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); 208 */ 209 static const struct ic_csc_params ic_csc_ycbcr2rgb = { 210 .coeff = { 211 { 149, 0, 204 }, 212 { 149, 462, 408 }, 213 { 149, 255, 0 }, 214 }, 215 .offset = { -446, 266, -554 }, 216 .scale = 2, 217 }; 218 219 static int init_csc(struct ipu_ic *ic, 220 enum ipu_color_space inf, 221 enum ipu_color_space outf, 222 int csc_index) 223 { 224 struct ipu_ic_priv *priv = ic->priv; 225 const struct ic_csc_params *params; 226 u32 __iomem *base; 227 const u16 (*c)[3]; 228 const u16 *a; 229 u32 param; 230 231 base = (u32 __iomem *) 232 (priv->tpmem_base + ic->reg->tpmem_csc[csc_index]); 233 234 if (inf == IPUV3_COLORSPACE_YUV && outf == IPUV3_COLORSPACE_RGB) 235 params = &ic_csc_ycbcr2rgb; 236 else if (inf == IPUV3_COLORSPACE_RGB && outf == IPUV3_COLORSPACE_YUV) 237 params = &ic_csc_rgb2ycbcr; 238 else if (inf == IPUV3_COLORSPACE_RGB && outf == IPUV3_COLORSPACE_RGB) 239 params = &ic_csc_rgb2rgb; 240 else { 241 dev_err(priv->ipu->dev, "Unsupported color space conversion\n"); 242 return -EINVAL; 243 } 244 245 /* Cast to unsigned */ 246 c = (const u16 (*)[3])params->coeff; 247 a = (const u16 *)params->offset; 248 249 param = ((a[0] & 0x1f) << 27) | ((c[0][0] & 0x1ff) << 18) | 250 ((c[1][1] & 0x1ff) << 9) | (c[2][2] & 0x1ff); 251 writel(param, base++); 252 253 param = ((a[0] & 0x1fe0) >> 5) | (params->scale << 8) | 254 (params->sat << 9); 255 writel(param, base++); 256 257 param = ((a[1] & 0x1f) << 27) | ((c[0][1] & 0x1ff) << 18) | 258 ((c[1][0] & 0x1ff) << 9) | (c[2][0] & 0x1ff); 259 writel(param, base++); 260 261 param = ((a[1] & 0x1fe0) >> 5); 262 writel(param, base++); 263 264 param = ((a[2] & 0x1f) << 27) | ((c[0][2] & 0x1ff) << 18) | 265 ((c[1][2] & 0x1ff) << 9) | (c[2][1] & 0x1ff); 266 writel(param, base++); 267 268 param = ((a[2] & 0x1fe0) >> 5); 269 writel(param, base++); 270 271 return 0; 272 } 273 274 static int calc_resize_coeffs(struct ipu_ic *ic, 275 u32 in_size, u32 out_size, 276 u32 *resize_coeff, 277 u32 *downsize_coeff) 278 { 279 struct ipu_ic_priv *priv = ic->priv; 280 struct ipu_soc *ipu = priv->ipu; 281 u32 temp_size, temp_downsize; 282 283 /* 284 * Input size cannot be more than 4096, and output size cannot 285 * be more than 1024 286 */ 287 if (in_size > 4096) { 288 dev_err(ipu->dev, "Unsupported resize (in_size > 4096)\n"); 289 return -EINVAL; 290 } 291 if (out_size > 1024) { 292 dev_err(ipu->dev, "Unsupported resize (out_size > 1024)\n"); 293 return -EINVAL; 294 } 295 296 /* Cannot downsize more than 4:1 */ 297 if ((out_size << 2) < in_size) { 298 dev_err(ipu->dev, "Unsupported downsize\n"); 299 return -EINVAL; 300 } 301 302 /* Compute downsizing coefficient */ 303 temp_downsize = 0; 304 temp_size = in_size; 305 while (((temp_size > 1024) || (temp_size >= out_size * 2)) && 306 (temp_downsize < 2)) { 307 temp_size >>= 1; 308 temp_downsize++; 309 } 310 *downsize_coeff = temp_downsize; 311 312 /* 313 * compute resizing coefficient using the following equation: 314 * resize_coeff = M * (SI - 1) / (SO - 1) 315 * where M = 2^13, SI = input size, SO = output size 316 */ 317 *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1); 318 if (*resize_coeff >= 16384L) { 319 dev_err(ipu->dev, "Warning! Overflow on resize coeff.\n"); 320 *resize_coeff = 0x3FFF; 321 } 322 323 return 0; 324 } 325 326 void ipu_ic_task_enable(struct ipu_ic *ic) 327 { 328 struct ipu_ic_priv *priv = ic->priv; 329 unsigned long flags; 330 u32 ic_conf; 331 332 spin_lock_irqsave(&priv->lock, flags); 333 334 ic_conf = ipu_ic_read(ic, IC_CONF); 335 336 ic_conf |= ic->bit->ic_conf_en; 337 338 if (ic->rotation) 339 ic_conf |= ic->bit->ic_conf_rot_en; 340 341 if (ic->in_cs != ic->out_cs) 342 ic_conf |= ic->bit->ic_conf_csc1_en; 343 344 if (ic->graphics) { 345 ic_conf |= ic->bit->ic_conf_cmb_en; 346 ic_conf |= ic->bit->ic_conf_csc1_en; 347 348 if (ic->g_in_cs != ic->out_cs) 349 ic_conf |= ic->bit->ic_conf_csc2_en; 350 } 351 352 ipu_ic_write(ic, ic_conf, IC_CONF); 353 354 spin_unlock_irqrestore(&priv->lock, flags); 355 } 356 EXPORT_SYMBOL_GPL(ipu_ic_task_enable); 357 358 void ipu_ic_task_disable(struct ipu_ic *ic) 359 { 360 struct ipu_ic_priv *priv = ic->priv; 361 unsigned long flags; 362 u32 ic_conf; 363 364 spin_lock_irqsave(&priv->lock, flags); 365 366 ic_conf = ipu_ic_read(ic, IC_CONF); 367 368 ic_conf &= ~(ic->bit->ic_conf_en | 369 ic->bit->ic_conf_csc1_en | 370 ic->bit->ic_conf_rot_en); 371 if (ic->bit->ic_conf_csc2_en) 372 ic_conf &= ~ic->bit->ic_conf_csc2_en; 373 if (ic->bit->ic_conf_cmb_en) 374 ic_conf &= ~ic->bit->ic_conf_cmb_en; 375 376 ipu_ic_write(ic, ic_conf, IC_CONF); 377 378 spin_unlock_irqrestore(&priv->lock, flags); 379 } 380 EXPORT_SYMBOL_GPL(ipu_ic_task_disable); 381 382 int ipu_ic_task_graphics_init(struct ipu_ic *ic, 383 enum ipu_color_space in_g_cs, 384 bool galpha_en, u32 galpha, 385 bool colorkey_en, u32 colorkey) 386 { 387 struct ipu_ic_priv *priv = ic->priv; 388 unsigned long flags; 389 u32 reg, ic_conf; 390 int ret = 0; 391 392 if (ic->task == IC_TASK_ENCODER) 393 return -EINVAL; 394 395 spin_lock_irqsave(&priv->lock, flags); 396 397 ic_conf = ipu_ic_read(ic, IC_CONF); 398 399 if (!(ic_conf & ic->bit->ic_conf_csc1_en)) { 400 /* need transparent CSC1 conversion */ 401 ret = init_csc(ic, IPUV3_COLORSPACE_RGB, 402 IPUV3_COLORSPACE_RGB, 0); 403 if (ret) 404 goto unlock; 405 } 406 407 ic->g_in_cs = in_g_cs; 408 409 if (ic->g_in_cs != ic->out_cs) { 410 ret = init_csc(ic, ic->g_in_cs, ic->out_cs, 1); 411 if (ret) 412 goto unlock; 413 } 414 415 if (galpha_en) { 416 ic_conf |= IC_CONF_IC_GLB_LOC_A; 417 reg = ipu_ic_read(ic, IC_CMBP_1); 418 reg &= ~(0xff << ic->bit->ic_cmb_galpha_bit); 419 reg |= (galpha << ic->bit->ic_cmb_galpha_bit); 420 ipu_ic_write(ic, reg, IC_CMBP_1); 421 } else 422 ic_conf &= ~IC_CONF_IC_GLB_LOC_A; 423 424 if (colorkey_en) { 425 ic_conf |= IC_CONF_KEY_COLOR_EN; 426 ipu_ic_write(ic, colorkey, IC_CMBP_2); 427 } else 428 ic_conf &= ~IC_CONF_KEY_COLOR_EN; 429 430 ipu_ic_write(ic, ic_conf, IC_CONF); 431 432 ic->graphics = true; 433 unlock: 434 spin_unlock_irqrestore(&priv->lock, flags); 435 return ret; 436 } 437 EXPORT_SYMBOL_GPL(ipu_ic_task_graphics_init); 438 439 int ipu_ic_task_init_rsc(struct ipu_ic *ic, 440 int in_width, int in_height, 441 int out_width, int out_height, 442 enum ipu_color_space in_cs, 443 enum ipu_color_space out_cs, 444 u32 rsc) 445 { 446 struct ipu_ic_priv *priv = ic->priv; 447 u32 downsize_coeff, resize_coeff; 448 unsigned long flags; 449 int ret = 0; 450 451 if (!rsc) { 452 /* Setup vertical resizing */ 453 454 ret = calc_resize_coeffs(ic, in_height, out_height, 455 &resize_coeff, &downsize_coeff); 456 if (ret) 457 return ret; 458 459 rsc = (downsize_coeff << 30) | (resize_coeff << 16); 460 461 /* Setup horizontal resizing */ 462 ret = calc_resize_coeffs(ic, in_width, out_width, 463 &resize_coeff, &downsize_coeff); 464 if (ret) 465 return ret; 466 467 rsc |= (downsize_coeff << 14) | resize_coeff; 468 } 469 470 spin_lock_irqsave(&priv->lock, flags); 471 472 ipu_ic_write(ic, rsc, ic->reg->rsc); 473 474 /* Setup color space conversion */ 475 ic->in_cs = in_cs; 476 ic->out_cs = out_cs; 477 478 if (ic->in_cs != ic->out_cs) { 479 ret = init_csc(ic, ic->in_cs, ic->out_cs, 0); 480 if (ret) 481 goto unlock; 482 } 483 484 unlock: 485 spin_unlock_irqrestore(&priv->lock, flags); 486 return ret; 487 } 488 489 int ipu_ic_task_init(struct ipu_ic *ic, 490 int in_width, int in_height, 491 int out_width, int out_height, 492 enum ipu_color_space in_cs, 493 enum ipu_color_space out_cs) 494 { 495 return ipu_ic_task_init_rsc(ic, in_width, in_height, out_width, 496 out_height, in_cs, out_cs, 0); 497 } 498 EXPORT_SYMBOL_GPL(ipu_ic_task_init); 499 500 int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel, 501 u32 width, u32 height, int burst_size, 502 enum ipu_rotate_mode rot) 503 { 504 struct ipu_ic_priv *priv = ic->priv; 505 struct ipu_soc *ipu = priv->ipu; 506 u32 ic_idmac_1, ic_idmac_2, ic_idmac_3; 507 u32 temp_rot = bitrev8(rot) >> 5; 508 bool need_hor_flip = false; 509 unsigned long flags; 510 int ret = 0; 511 512 if ((burst_size != 8) && (burst_size != 16)) { 513 dev_err(ipu->dev, "Illegal burst length for IC\n"); 514 return -EINVAL; 515 } 516 517 width--; 518 height--; 519 520 if (temp_rot & 0x2) /* Need horizontal flip */ 521 need_hor_flip = true; 522 523 spin_lock_irqsave(&priv->lock, flags); 524 525 ic_idmac_1 = ipu_ic_read(ic, IC_IDMAC_1); 526 ic_idmac_2 = ipu_ic_read(ic, IC_IDMAC_2); 527 ic_idmac_3 = ipu_ic_read(ic, IC_IDMAC_3); 528 529 switch (channel->num) { 530 case IPUV3_CHANNEL_IC_PP_MEM: 531 if (burst_size == 16) 532 ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16; 533 else 534 ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16; 535 536 if (need_hor_flip) 537 ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS; 538 else 539 ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS; 540 541 ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK; 542 ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET; 543 544 ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK; 545 ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET; 546 break; 547 case IPUV3_CHANNEL_MEM_IC_PP: 548 if (burst_size == 16) 549 ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16; 550 else 551 ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16; 552 break; 553 case IPUV3_CHANNEL_MEM_ROT_PP: 554 ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK; 555 ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET; 556 break; 557 case IPUV3_CHANNEL_MEM_IC_PRP_VF: 558 if (burst_size == 16) 559 ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16; 560 else 561 ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16; 562 break; 563 case IPUV3_CHANNEL_IC_PRP_ENC_MEM: 564 if (burst_size == 16) 565 ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16; 566 else 567 ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16; 568 569 if (need_hor_flip) 570 ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS; 571 else 572 ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS; 573 574 ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK; 575 ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET; 576 577 ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK; 578 ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET; 579 break; 580 case IPUV3_CHANNEL_MEM_ROT_ENC: 581 ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK; 582 ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET; 583 break; 584 case IPUV3_CHANNEL_IC_PRP_VF_MEM: 585 if (burst_size == 16) 586 ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16; 587 else 588 ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16; 589 590 if (need_hor_flip) 591 ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS; 592 else 593 ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS; 594 595 ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK; 596 ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET; 597 598 ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK; 599 ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET; 600 break; 601 case IPUV3_CHANNEL_MEM_ROT_VF: 602 ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK; 603 ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET; 604 break; 605 case IPUV3_CHANNEL_G_MEM_IC_PRP_VF: 606 if (burst_size == 16) 607 ic_idmac_1 |= IC_IDMAC_1_CB3_BURST_16; 608 else 609 ic_idmac_1 &= ~IC_IDMAC_1_CB3_BURST_16; 610 break; 611 case IPUV3_CHANNEL_G_MEM_IC_PP: 612 if (burst_size == 16) 613 ic_idmac_1 |= IC_IDMAC_1_CB4_BURST_16; 614 else 615 ic_idmac_1 &= ~IC_IDMAC_1_CB4_BURST_16; 616 break; 617 case IPUV3_CHANNEL_VDI_MEM_IC_VF: 618 if (burst_size == 16) 619 ic_idmac_1 |= IC_IDMAC_1_CB7_BURST_16; 620 else 621 ic_idmac_1 &= ~IC_IDMAC_1_CB7_BURST_16; 622 break; 623 default: 624 goto unlock; 625 } 626 627 ipu_ic_write(ic, ic_idmac_1, IC_IDMAC_1); 628 ipu_ic_write(ic, ic_idmac_2, IC_IDMAC_2); 629 ipu_ic_write(ic, ic_idmac_3, IC_IDMAC_3); 630 631 if (ipu_rot_mode_is_irt(rot)) 632 ic->rotation = true; 633 634 unlock: 635 spin_unlock_irqrestore(&priv->lock, flags); 636 return ret; 637 } 638 EXPORT_SYMBOL_GPL(ipu_ic_task_idma_init); 639 640 static void ipu_irt_enable(struct ipu_ic *ic) 641 { 642 struct ipu_ic_priv *priv = ic->priv; 643 644 if (!priv->irt_use_count) 645 ipu_module_enable(priv->ipu, IPU_CONF_ROT_EN); 646 647 priv->irt_use_count++; 648 } 649 650 static void ipu_irt_disable(struct ipu_ic *ic) 651 { 652 struct ipu_ic_priv *priv = ic->priv; 653 654 if (priv->irt_use_count) { 655 if (!--priv->irt_use_count) 656 ipu_module_disable(priv->ipu, IPU_CONF_ROT_EN); 657 } 658 } 659 660 int ipu_ic_enable(struct ipu_ic *ic) 661 { 662 struct ipu_ic_priv *priv = ic->priv; 663 unsigned long flags; 664 665 spin_lock_irqsave(&priv->lock, flags); 666 667 if (!priv->use_count) 668 ipu_module_enable(priv->ipu, IPU_CONF_IC_EN); 669 670 priv->use_count++; 671 672 if (ic->rotation) 673 ipu_irt_enable(ic); 674 675 spin_unlock_irqrestore(&priv->lock, flags); 676 677 return 0; 678 } 679 EXPORT_SYMBOL_GPL(ipu_ic_enable); 680 681 int ipu_ic_disable(struct ipu_ic *ic) 682 { 683 struct ipu_ic_priv *priv = ic->priv; 684 unsigned long flags; 685 686 spin_lock_irqsave(&priv->lock, flags); 687 688 priv->use_count--; 689 690 if (!priv->use_count) 691 ipu_module_disable(priv->ipu, IPU_CONF_IC_EN); 692 693 if (priv->use_count < 0) 694 priv->use_count = 0; 695 696 if (ic->rotation) 697 ipu_irt_disable(ic); 698 699 ic->rotation = ic->graphics = false; 700 701 spin_unlock_irqrestore(&priv->lock, flags); 702 703 return 0; 704 } 705 EXPORT_SYMBOL_GPL(ipu_ic_disable); 706 707 struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task) 708 { 709 struct ipu_ic_priv *priv = ipu->ic_priv; 710 unsigned long flags; 711 struct ipu_ic *ic, *ret; 712 713 if (task >= IC_NUM_TASKS) 714 return ERR_PTR(-EINVAL); 715 716 ic = &priv->task[task]; 717 718 spin_lock_irqsave(&priv->lock, flags); 719 720 if (ic->in_use) { 721 ret = ERR_PTR(-EBUSY); 722 goto unlock; 723 } 724 725 ic->in_use = true; 726 ret = ic; 727 728 unlock: 729 spin_unlock_irqrestore(&priv->lock, flags); 730 return ret; 731 } 732 EXPORT_SYMBOL_GPL(ipu_ic_get); 733 734 void ipu_ic_put(struct ipu_ic *ic) 735 { 736 struct ipu_ic_priv *priv = ic->priv; 737 unsigned long flags; 738 739 spin_lock_irqsave(&priv->lock, flags); 740 ic->in_use = false; 741 spin_unlock_irqrestore(&priv->lock, flags); 742 } 743 EXPORT_SYMBOL_GPL(ipu_ic_put); 744 745 int ipu_ic_init(struct ipu_soc *ipu, struct device *dev, 746 unsigned long base, unsigned long tpmem_base) 747 { 748 struct ipu_ic_priv *priv; 749 int i; 750 751 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 752 if (!priv) 753 return -ENOMEM; 754 755 ipu->ic_priv = priv; 756 757 spin_lock_init(&priv->lock); 758 priv->base = devm_ioremap(dev, base, PAGE_SIZE); 759 if (!priv->base) 760 return -ENOMEM; 761 priv->tpmem_base = devm_ioremap(dev, tpmem_base, SZ_64K); 762 if (!priv->tpmem_base) 763 return -ENOMEM; 764 765 dev_dbg(dev, "IC base: 0x%08lx remapped to %p\n", base, priv->base); 766 767 priv->ipu = ipu; 768 769 for (i = 0; i < IC_NUM_TASKS; i++) { 770 priv->task[i].task = i; 771 priv->task[i].priv = priv; 772 priv->task[i].reg = &ic_task_reg[i]; 773 priv->task[i].bit = &ic_task_bit[i]; 774 } 775 776 return 0; 777 } 778 779 void ipu_ic_exit(struct ipu_soc *ipu) 780 { 781 } 782 783 void ipu_ic_dump(struct ipu_ic *ic) 784 { 785 struct ipu_ic_priv *priv = ic->priv; 786 struct ipu_soc *ipu = priv->ipu; 787 788 dev_dbg(ipu->dev, "IC_CONF = \t0x%08X\n", 789 ipu_ic_read(ic, IC_CONF)); 790 dev_dbg(ipu->dev, "IC_PRP_ENC_RSC = \t0x%08X\n", 791 ipu_ic_read(ic, IC_PRP_ENC_RSC)); 792 dev_dbg(ipu->dev, "IC_PRP_VF_RSC = \t0x%08X\n", 793 ipu_ic_read(ic, IC_PRP_VF_RSC)); 794 dev_dbg(ipu->dev, "IC_PP_RSC = \t0x%08X\n", 795 ipu_ic_read(ic, IC_PP_RSC)); 796 dev_dbg(ipu->dev, "IC_CMBP_1 = \t0x%08X\n", 797 ipu_ic_read(ic, IC_CMBP_1)); 798 dev_dbg(ipu->dev, "IC_CMBP_2 = \t0x%08X\n", 799 ipu_ic_read(ic, IC_CMBP_2)); 800 dev_dbg(ipu->dev, "IC_IDMAC_1 = \t0x%08X\n", 801 ipu_ic_read(ic, IC_IDMAC_1)); 802 dev_dbg(ipu->dev, "IC_IDMAC_2 = \t0x%08X\n", 803 ipu_ic_read(ic, IC_IDMAC_2)); 804 dev_dbg(ipu->dev, "IC_IDMAC_3 = \t0x%08X\n", 805 ipu_ic_read(ic, IC_IDMAC_3)); 806 dev_dbg(ipu->dev, "IC_IDMAC_4 = \t0x%08X\n", 807 ipu_ic_read(ic, IC_IDMAC_4)); 808 } 809 EXPORT_SYMBOL_GPL(ipu_ic_dump); 810