xref: /openbmc/linux/drivers/gpu/ipu-v3/ipu-di.c (revision 0edbfea5)
1 /*
2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation; either version 2 of the License, or (at your
8  * option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13  * for more details.
14  */
15 #include <linux/export.h>
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/io.h>
20 #include <linux/err.h>
21 #include <linux/platform_device.h>
22 
23 #include <video/imx-ipu-v3.h>
24 #include "ipu-prv.h"
25 
26 struct ipu_di {
27 	void __iomem *base;
28 	int id;
29 	u32 module;
30 	struct clk *clk_di;	/* display input clock */
31 	struct clk *clk_ipu;	/* IPU bus clock */
32 	struct clk *clk_di_pixel; /* resulting pixel clock */
33 	bool inuse;
34 	struct ipu_soc *ipu;
35 };
36 
37 static DEFINE_MUTEX(di_mutex);
38 
39 struct di_sync_config {
40 	int run_count;
41 	int run_src;
42 	int offset_count;
43 	int offset_src;
44 	int repeat_count;
45 	int cnt_clr_src;
46 	int cnt_polarity_gen_en;
47 	int cnt_polarity_clr_src;
48 	int cnt_polarity_trigger_src;
49 	int cnt_up;
50 	int cnt_down;
51 };
52 
53 enum di_pins {
54 	DI_PIN11 = 0,
55 	DI_PIN12 = 1,
56 	DI_PIN13 = 2,
57 	DI_PIN14 = 3,
58 	DI_PIN15 = 4,
59 	DI_PIN16 = 5,
60 	DI_PIN17 = 6,
61 	DI_PIN_CS = 7,
62 
63 	DI_PIN_SER_CLK = 0,
64 	DI_PIN_SER_RS = 1,
65 };
66 
67 enum di_sync_wave {
68 	DI_SYNC_NONE = 0,
69 	DI_SYNC_CLK = 1,
70 	DI_SYNC_INT_HSYNC = 2,
71 	DI_SYNC_HSYNC = 3,
72 	DI_SYNC_VSYNC = 4,
73 	DI_SYNC_DE = 6,
74 
75 	DI_SYNC_CNT1 = 2,	/* counter >= 2 only */
76 	DI_SYNC_CNT4 = 5,	/* counter >= 5 only */
77 	DI_SYNC_CNT5 = 6,	/* counter >= 6 only */
78 };
79 
80 #define SYNC_WAVE 0
81 
82 #define DI_GENERAL		0x0000
83 #define DI_BS_CLKGEN0		0x0004
84 #define DI_BS_CLKGEN1		0x0008
85 #define DI_SW_GEN0(gen)		(0x000c + 4 * ((gen) - 1))
86 #define DI_SW_GEN1(gen)		(0x0030 + 4 * ((gen) - 1))
87 #define DI_STP_REP(gen)		(0x0148 + 4 * (((gen) - 1)/2))
88 #define DI_SYNC_AS_GEN		0x0054
89 #define DI_DW_GEN(gen)		(0x0058 + 4 * (gen))
90 #define DI_DW_SET(gen, set)	(0x0088 + 4 * ((gen) + 0xc * (set)))
91 #define DI_SER_CONF		0x015c
92 #define DI_SSC			0x0160
93 #define DI_POL			0x0164
94 #define DI_AW0			0x0168
95 #define DI_AW1			0x016c
96 #define DI_SCR_CONF		0x0170
97 #define DI_STAT			0x0174
98 
99 #define DI_SW_GEN0_RUN_COUNT(x)			((x) << 19)
100 #define DI_SW_GEN0_RUN_SRC(x)			((x) << 16)
101 #define DI_SW_GEN0_OFFSET_COUNT(x)		((x) << 3)
102 #define DI_SW_GEN0_OFFSET_SRC(x)		((x) << 0)
103 
104 #define DI_SW_GEN1_CNT_POL_GEN_EN(x)		((x) << 29)
105 #define DI_SW_GEN1_CNT_CLR_SRC(x)		((x) << 25)
106 #define DI_SW_GEN1_CNT_POL_TRIGGER_SRC(x)	((x) << 12)
107 #define DI_SW_GEN1_CNT_POL_CLR_SRC(x)		((x) << 9)
108 #define DI_SW_GEN1_CNT_DOWN(x)			((x) << 16)
109 #define DI_SW_GEN1_CNT_UP(x)			(x)
110 #define DI_SW_GEN1_AUTO_RELOAD			(0x10000000)
111 
112 #define DI_DW_GEN_ACCESS_SIZE_OFFSET		24
113 #define DI_DW_GEN_COMPONENT_SIZE_OFFSET		16
114 
115 #define DI_GEN_POLARITY_1			(1 << 0)
116 #define DI_GEN_POLARITY_2			(1 << 1)
117 #define DI_GEN_POLARITY_3			(1 << 2)
118 #define DI_GEN_POLARITY_4			(1 << 3)
119 #define DI_GEN_POLARITY_5			(1 << 4)
120 #define DI_GEN_POLARITY_6			(1 << 5)
121 #define DI_GEN_POLARITY_7			(1 << 6)
122 #define DI_GEN_POLARITY_8			(1 << 7)
123 #define DI_GEN_POLARITY_DISP_CLK		(1 << 17)
124 #define DI_GEN_DI_CLK_EXT			(1 << 20)
125 #define DI_GEN_DI_VSYNC_EXT			(1 << 21)
126 
127 #define DI_POL_DRDY_DATA_POLARITY		(1 << 7)
128 #define DI_POL_DRDY_POLARITY_15			(1 << 4)
129 
130 #define DI_VSYNC_SEL_OFFSET			13
131 
132 static inline u32 ipu_di_read(struct ipu_di *di, unsigned offset)
133 {
134 	return readl(di->base + offset);
135 }
136 
137 static inline void ipu_di_write(struct ipu_di *di, u32 value, unsigned offset)
138 {
139 	writel(value, di->base + offset);
140 }
141 
142 static void ipu_di_data_wave_config(struct ipu_di *di,
143 				     int wave_gen,
144 				     int access_size, int component_size)
145 {
146 	u32 reg;
147 	reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
148 	    (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
149 	ipu_di_write(di, reg, DI_DW_GEN(wave_gen));
150 }
151 
152 static void ipu_di_data_pin_config(struct ipu_di *di, int wave_gen, int di_pin,
153 		int set, int up, int down)
154 {
155 	u32 reg;
156 
157 	reg = ipu_di_read(di, DI_DW_GEN(wave_gen));
158 	reg &= ~(0x3 << (di_pin * 2));
159 	reg |= set << (di_pin * 2);
160 	ipu_di_write(di, reg, DI_DW_GEN(wave_gen));
161 
162 	ipu_di_write(di, (down << 16) | up, DI_DW_SET(wave_gen, set));
163 }
164 
165 static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config,
166 		int start, int count)
167 {
168 	u32 reg;
169 	int i;
170 
171 	for (i = 0; i < count; i++) {
172 		struct di_sync_config *c = &config[i];
173 		int wave_gen = start + i + 1;
174 
175 		if ((c->run_count >= 0x1000) || (c->offset_count >= 0x1000) ||
176 				(c->repeat_count >= 0x1000) ||
177 				(c->cnt_up >= 0x400) ||
178 				(c->cnt_down >= 0x400)) {
179 			dev_err(di->ipu->dev, "DI%d counters out of range.\n",
180 					di->id);
181 			return;
182 		}
183 
184 		reg = DI_SW_GEN0_RUN_COUNT(c->run_count) |
185 			DI_SW_GEN0_RUN_SRC(c->run_src) |
186 			DI_SW_GEN0_OFFSET_COUNT(c->offset_count) |
187 			DI_SW_GEN0_OFFSET_SRC(c->offset_src);
188 		ipu_di_write(di, reg, DI_SW_GEN0(wave_gen));
189 
190 		reg = DI_SW_GEN1_CNT_POL_GEN_EN(c->cnt_polarity_gen_en) |
191 			DI_SW_GEN1_CNT_CLR_SRC(c->cnt_clr_src) |
192 			DI_SW_GEN1_CNT_POL_TRIGGER_SRC(
193 					c->cnt_polarity_trigger_src) |
194 			DI_SW_GEN1_CNT_POL_CLR_SRC(c->cnt_polarity_clr_src) |
195 			DI_SW_GEN1_CNT_DOWN(c->cnt_down) |
196 			DI_SW_GEN1_CNT_UP(c->cnt_up);
197 
198 		/* Enable auto reload */
199 		if (c->repeat_count == 0)
200 			reg |= DI_SW_GEN1_AUTO_RELOAD;
201 
202 		ipu_di_write(di, reg, DI_SW_GEN1(wave_gen));
203 
204 		reg = ipu_di_read(di, DI_STP_REP(wave_gen));
205 		reg &= ~(0xffff << (16 * ((wave_gen - 1) & 0x1)));
206 		reg |= c->repeat_count << (16 * ((wave_gen - 1) & 0x1));
207 		ipu_di_write(di, reg, DI_STP_REP(wave_gen));
208 	}
209 }
210 
211 static void ipu_di_sync_config_interlaced(struct ipu_di *di,
212 		struct ipu_di_signal_cfg *sig)
213 {
214 	u32 h_total = sig->mode.hactive + sig->mode.hsync_len +
215 		sig->mode.hback_porch + sig->mode.hfront_porch;
216 	u32 v_total = sig->mode.vactive + sig->mode.vsync_len +
217 		sig->mode.vback_porch + sig->mode.vfront_porch;
218 	struct di_sync_config cfg[] = {
219 		{
220 			/* 1: internal VSYNC for each frame */
221 			.run_count = v_total * 2 - 1,
222 			.run_src = 3,			/* == counter 7 */
223 		}, {
224 			/* PIN2: HSYNC waveform */
225 			.run_count = h_total - 1,
226 			.run_src = DI_SYNC_CLK,
227 			.cnt_polarity_gen_en = 1,
228 			.cnt_polarity_trigger_src = DI_SYNC_CLK,
229 			.cnt_down = sig->mode.hsync_len * 2,
230 		}, {
231 			/* PIN3: VSYNC waveform */
232 			.run_count = v_total - 1,
233 			.run_src = 4,			/* == counter 7 */
234 			.cnt_polarity_gen_en = 1,
235 			.cnt_polarity_trigger_src = 4,	/* == counter 7 */
236 			.cnt_down = sig->mode.vsync_len * 2,
237 			.cnt_clr_src = DI_SYNC_CNT1,
238 		}, {
239 			/* 4: Field */
240 			.run_count = v_total / 2,
241 			.run_src = DI_SYNC_HSYNC,
242 			.offset_count = h_total / 2,
243 			.offset_src = DI_SYNC_CLK,
244 			.repeat_count = 2,
245 			.cnt_clr_src = DI_SYNC_CNT1,
246 		}, {
247 			/* 5: Active lines */
248 			.run_src = DI_SYNC_HSYNC,
249 			.offset_count = (sig->mode.vsync_len +
250 					 sig->mode.vback_porch) / 2,
251 			.offset_src = DI_SYNC_HSYNC,
252 			.repeat_count = sig->mode.vactive / 2,
253 			.cnt_clr_src = DI_SYNC_CNT4,
254 		}, {
255 			/* 6: Active pixel, referenced by DC */
256 			.run_src = DI_SYNC_CLK,
257 			.offset_count = sig->mode.hsync_len +
258 					sig->mode.hback_porch,
259 			.offset_src = DI_SYNC_CLK,
260 			.repeat_count = sig->mode.hactive,
261 			.cnt_clr_src = DI_SYNC_CNT5,
262 		}, {
263 			/* 7: Half line HSYNC */
264 			.run_count = h_total / 2 - 1,
265 			.run_src = DI_SYNC_CLK,
266 		}
267 	};
268 
269 	ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg));
270 
271 	ipu_di_write(di, v_total / 2 - 1, DI_SCR_CONF);
272 }
273 
274 static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
275 		struct ipu_di_signal_cfg *sig, int div)
276 {
277 	u32 h_total = sig->mode.hactive + sig->mode.hsync_len +
278 		sig->mode.hback_porch + sig->mode.hfront_porch;
279 	u32 v_total = sig->mode.vactive + sig->mode.vsync_len +
280 		sig->mode.vback_porch + sig->mode.vfront_porch;
281 	struct di_sync_config cfg[] = {
282 		{
283 			/* 1: INT_HSYNC */
284 			.run_count = h_total - 1,
285 			.run_src = DI_SYNC_CLK,
286 		} , {
287 			/* PIN2: HSYNC */
288 			.run_count = h_total - 1,
289 			.run_src = DI_SYNC_CLK,
290 			.offset_count = div * sig->v_to_h_sync,
291 			.offset_src = DI_SYNC_CLK,
292 			.cnt_polarity_gen_en = 1,
293 			.cnt_polarity_trigger_src = DI_SYNC_CLK,
294 			.cnt_down = sig->mode.hsync_len * 2,
295 		} , {
296 			/* PIN3: VSYNC */
297 			.run_count = v_total - 1,
298 			.run_src = DI_SYNC_INT_HSYNC,
299 			.cnt_polarity_gen_en = 1,
300 			.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
301 			.cnt_down = sig->mode.vsync_len * 2,
302 		} , {
303 			/* 4: Line Active */
304 			.run_src = DI_SYNC_HSYNC,
305 			.offset_count = sig->mode.vsync_len +
306 					sig->mode.vback_porch,
307 			.offset_src = DI_SYNC_HSYNC,
308 			.repeat_count = sig->mode.vactive,
309 			.cnt_clr_src = DI_SYNC_VSYNC,
310 		} , {
311 			/* 5: Pixel Active, referenced by DC */
312 			.run_src = DI_SYNC_CLK,
313 			.offset_count = sig->mode.hsync_len +
314 					sig->mode.hback_porch,
315 			.offset_src = DI_SYNC_CLK,
316 			.repeat_count = sig->mode.hactive,
317 			.cnt_clr_src = 5, /* Line Active */
318 		} , {
319 			/* unused */
320 		} , {
321 			/* unused */
322 		} , {
323 			/* unused */
324 		} , {
325 			/* unused */
326 		},
327 	};
328 	/* can't use #7 and #8 for line active and pixel active counters */
329 	struct di_sync_config cfg_vga[] = {
330 		{
331 			/* 1: INT_HSYNC */
332 			.run_count = h_total - 1,
333 			.run_src = DI_SYNC_CLK,
334 		} , {
335 			/* 2: VSYNC */
336 			.run_count = v_total - 1,
337 			.run_src = DI_SYNC_INT_HSYNC,
338 		} , {
339 			/* 3: Line Active */
340 			.run_src = DI_SYNC_INT_HSYNC,
341 			.offset_count = sig->mode.vsync_len +
342 					sig->mode.vback_porch,
343 			.offset_src = DI_SYNC_INT_HSYNC,
344 			.repeat_count = sig->mode.vactive,
345 			.cnt_clr_src = 3 /* VSYNC */,
346 		} , {
347 			/* PIN4: HSYNC for VGA via TVEv2 on TQ MBa53 */
348 			.run_count = h_total - 1,
349 			.run_src = DI_SYNC_CLK,
350 			.offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */
351 			.offset_src = DI_SYNC_CLK,
352 			.cnt_polarity_gen_en = 1,
353 			.cnt_polarity_trigger_src = DI_SYNC_CLK,
354 			.cnt_down = sig->mode.hsync_len * 2,
355 		} , {
356 			/* 5: Pixel Active signal to DC */
357 			.run_src = DI_SYNC_CLK,
358 			.offset_count = sig->mode.hsync_len +
359 					sig->mode.hback_porch,
360 			.offset_src = DI_SYNC_CLK,
361 			.repeat_count = sig->mode.hactive,
362 			.cnt_clr_src = 4, /* Line Active */
363 		} , {
364 			/* PIN6: VSYNC for VGA via TVEv2 on TQ MBa53 */
365 			.run_count = v_total - 1,
366 			.run_src = DI_SYNC_INT_HSYNC,
367 			.offset_count = 1, /* magic value from Freescale TVE driver */
368 			.offset_src = DI_SYNC_INT_HSYNC,
369 			.cnt_polarity_gen_en = 1,
370 			.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
371 			.cnt_down = sig->mode.vsync_len * 2,
372 		} , {
373 			/* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */
374 			.run_count = h_total - 1,
375 			.run_src = DI_SYNC_CLK,
376 			.offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */
377 			.offset_src = DI_SYNC_CLK,
378 			.cnt_polarity_gen_en = 1,
379 			.cnt_polarity_trigger_src = DI_SYNC_CLK,
380 			.cnt_down = sig->mode.hsync_len * 2,
381 		} , {
382 			/* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */
383 			.run_count = v_total - 1,
384 			.run_src = DI_SYNC_INT_HSYNC,
385 			.offset_count = 1, /* magic value from Freescale TVE driver */
386 			.offset_src = DI_SYNC_INT_HSYNC,
387 			.cnt_polarity_gen_en = 1,
388 			.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
389 			.cnt_down = sig->mode.vsync_len * 2,
390 		} , {
391 			/* unused */
392 		},
393 	};
394 
395 	ipu_di_write(di, v_total - 1, DI_SCR_CONF);
396 	if (sig->hsync_pin == 2 && sig->vsync_pin == 3)
397 		ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg));
398 	else
399 		ipu_di_sync_config(di, cfg_vga, 0, ARRAY_SIZE(cfg_vga));
400 }
401 
402 static void ipu_di_config_clock(struct ipu_di *di,
403 	const struct ipu_di_signal_cfg *sig)
404 {
405 	struct clk *clk;
406 	unsigned clkgen0;
407 	uint32_t val;
408 
409 	if (sig->clkflags & IPU_DI_CLKMODE_EXT) {
410 		/*
411 		 * CLKMODE_EXT means we must use the DI clock: this is
412 		 * needed for things like LVDS which needs to feed the
413 		 * DI and LDB with the same pixel clock.
414 		 */
415 		clk = di->clk_di;
416 
417 		if (sig->clkflags & IPU_DI_CLKMODE_SYNC) {
418 			/*
419 			 * CLKMODE_SYNC means that we want the DI to be
420 			 * clocked at the same rate as the parent clock.
421 			 * This is needed (eg) for LDB which needs to be
422 			 * fed with the same pixel clock.  We assume that
423 			 * the LDB clock has already been set correctly.
424 			 */
425 			clkgen0 = 1 << 4;
426 		} else {
427 			/*
428 			 * We can use the divider.  We should really have
429 			 * a flag here indicating whether the bridge can
430 			 * cope with a fractional divider or not.  For the
431 			 * time being, let's go for simplicitly and
432 			 * reliability.
433 			 */
434 			unsigned long in_rate;
435 			unsigned div;
436 
437 			clk_set_rate(clk, sig->mode.pixelclock);
438 
439 			in_rate = clk_get_rate(clk);
440 			div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);
441 			div = clamp(div, 1U, 255U);
442 
443 			clkgen0 = div << 4;
444 		}
445 	} else {
446 		/*
447 		 * For other interfaces, we can arbitarily select between
448 		 * the DI specific clock and the internal IPU clock.  See
449 		 * DI_GENERAL bit 20.  We select the IPU clock if it can
450 		 * give us a clock rate within 1% of the requested frequency,
451 		 * otherwise we use the DI clock.
452 		 */
453 		unsigned long rate, clkrate;
454 		unsigned div, error;
455 
456 		clkrate = clk_get_rate(di->clk_ipu);
457 		div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock);
458 		div = clamp(div, 1U, 255U);
459 		rate = clkrate / div;
460 
461 		error = rate / (sig->mode.pixelclock / 1000);
462 
463 		dev_dbg(di->ipu->dev, "  IPU clock can give %lu with divider %u, error %d.%u%%\n",
464 			rate, div, (signed)(error - 1000) / 10, error % 10);
465 
466 		/* Allow a 1% error */
467 		if (error < 1010 && error >= 990) {
468 			clk = di->clk_ipu;
469 
470 			clkgen0 = div << 4;
471 		} else {
472 			unsigned long in_rate;
473 			unsigned div;
474 
475 			clk = di->clk_di;
476 
477 			clk_set_rate(clk, sig->mode.pixelclock);
478 
479 			in_rate = clk_get_rate(clk);
480 			div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);
481 			div = clamp(div, 1U, 255U);
482 
483 			clkgen0 = div << 4;
484 		}
485 	}
486 
487 	di->clk_di_pixel = clk;
488 
489 	/* Set the divider */
490 	ipu_di_write(di, clkgen0, DI_BS_CLKGEN0);
491 
492 	/*
493 	 * Set the high/low periods.  Bits 24:16 give us the falling edge,
494 	 * and bits 8:0 give the rising edge.  LSB is fraction, and is
495 	 * based on the divider above.  We want a 50% duty cycle, so set
496 	 * the falling edge to be half the divider.
497 	 */
498 	ipu_di_write(di, (clkgen0 >> 4) << 16, DI_BS_CLKGEN1);
499 
500 	/* Finally select the input clock */
501 	val = ipu_di_read(di, DI_GENERAL) & ~DI_GEN_DI_CLK_EXT;
502 	if (clk == di->clk_di)
503 		val |= DI_GEN_DI_CLK_EXT;
504 	ipu_di_write(di, val, DI_GENERAL);
505 
506 	dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n",
507 		sig->mode.pixelclock,
508 		clk_get_rate(di->clk_ipu),
509 		clk_get_rate(di->clk_di),
510 		clk == di->clk_di ? "DI" : "IPU",
511 		clk_get_rate(di->clk_di_pixel) / (clkgen0 >> 4));
512 }
513 
514 /*
515  * This function is called to adjust a video mode to IPU restrictions.
516  * It is meant to be called from drm crtc mode_fixup() methods.
517  */
518 int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode)
519 {
520 	u32 diff;
521 
522 	if (mode->vfront_porch >= 2)
523 		return 0;
524 
525 	diff = 2 - mode->vfront_porch;
526 
527 	if (mode->vback_porch >= diff) {
528 		mode->vfront_porch = 2;
529 		mode->vback_porch -= diff;
530 	} else if (mode->vsync_len > diff) {
531 		mode->vfront_porch = 2;
532 		mode->vsync_len = mode->vsync_len - diff;
533 	} else {
534 		dev_warn(di->ipu->dev, "failed to adjust videomode\n");
535 		return -EINVAL;
536 	}
537 
538 	dev_warn(di->ipu->dev, "videomode adapted for IPU restrictions\n");
539 	return 0;
540 }
541 EXPORT_SYMBOL_GPL(ipu_di_adjust_videomode);
542 
543 static u32 ipu_di_gen_polarity(int pin)
544 {
545 	switch (pin) {
546 	case 1:
547 		return DI_GEN_POLARITY_1;
548 	case 2:
549 		return DI_GEN_POLARITY_2;
550 	case 3:
551 		return DI_GEN_POLARITY_3;
552 	case 4:
553 		return DI_GEN_POLARITY_4;
554 	case 5:
555 		return DI_GEN_POLARITY_5;
556 	case 6:
557 		return DI_GEN_POLARITY_6;
558 	case 7:
559 		return DI_GEN_POLARITY_7;
560 	case 8:
561 		return DI_GEN_POLARITY_8;
562 	}
563 	return 0;
564 }
565 
566 int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
567 {
568 	u32 reg;
569 	u32 di_gen, vsync_cnt;
570 	u32 div;
571 
572 	dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n",
573 		di->id, sig->mode.hactive, sig->mode.vactive);
574 
575 	if ((sig->mode.vsync_len == 0) || (sig->mode.hsync_len == 0))
576 		return -EINVAL;
577 
578 	dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n",
579 		clk_get_rate(di->clk_ipu),
580 		clk_get_rate(di->clk_di),
581 		sig->mode.pixelclock);
582 
583 	mutex_lock(&di_mutex);
584 
585 	ipu_di_config_clock(di, sig);
586 
587 	div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff;
588 	div = div / 16;		/* Now divider is integer portion */
589 
590 	/* Setup pixel clock timing */
591 	/* Down time is half of period */
592 	ipu_di_write(di, (div << 16), DI_BS_CLKGEN1);
593 
594 	ipu_di_data_wave_config(di, SYNC_WAVE, div - 1, div - 1);
595 	ipu_di_data_pin_config(di, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
596 
597 	di_gen = ipu_di_read(di, DI_GENERAL) & DI_GEN_DI_CLK_EXT;
598 	di_gen |= DI_GEN_DI_VSYNC_EXT;
599 
600 	if (sig->mode.flags & DISPLAY_FLAGS_INTERLACED) {
601 		ipu_di_sync_config_interlaced(di, sig);
602 
603 		/* set y_sel = 1 */
604 		di_gen |= 0x10000000;
605 
606 		vsync_cnt = 3;
607 	} else {
608 		ipu_di_sync_config_noninterlaced(di, sig, div);
609 
610 		vsync_cnt = 3;
611 		if (di->id == 1)
612 			/*
613 			 * TODO: change only for TVEv2, parallel display
614 			 * uses pin 2 / 3
615 			 */
616 			if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
617 				vsync_cnt = 6;
618 	}
619 
620 	if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH)
621 		di_gen |= ipu_di_gen_polarity(sig->hsync_pin);
622 	if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH)
623 		di_gen |= ipu_di_gen_polarity(sig->vsync_pin);
624 
625 	if (sig->clk_pol)
626 		di_gen |= DI_GEN_POLARITY_DISP_CLK;
627 
628 	ipu_di_write(di, di_gen, DI_GENERAL);
629 
630 	ipu_di_write(di, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) | 0x00000002,
631 		     DI_SYNC_AS_GEN);
632 
633 	reg = ipu_di_read(di, DI_POL);
634 	reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
635 
636 	if (sig->enable_pol)
637 		reg |= DI_POL_DRDY_POLARITY_15;
638 	if (sig->data_pol)
639 		reg |= DI_POL_DRDY_DATA_POLARITY;
640 
641 	ipu_di_write(di, reg, DI_POL);
642 
643 	mutex_unlock(&di_mutex);
644 
645 	return 0;
646 }
647 EXPORT_SYMBOL_GPL(ipu_di_init_sync_panel);
648 
649 int ipu_di_enable(struct ipu_di *di)
650 {
651 	int ret;
652 
653 	WARN_ON(IS_ERR(di->clk_di_pixel));
654 
655 	ret = clk_prepare_enable(di->clk_di_pixel);
656 	if (ret)
657 		return ret;
658 
659 	ipu_module_enable(di->ipu, di->module);
660 
661 	return 0;
662 }
663 EXPORT_SYMBOL_GPL(ipu_di_enable);
664 
665 int ipu_di_disable(struct ipu_di *di)
666 {
667 	WARN_ON(IS_ERR(di->clk_di_pixel));
668 
669 	ipu_module_disable(di->ipu, di->module);
670 
671 	clk_disable_unprepare(di->clk_di_pixel);
672 
673 	return 0;
674 }
675 EXPORT_SYMBOL_GPL(ipu_di_disable);
676 
677 int ipu_di_get_num(struct ipu_di *di)
678 {
679 	return di->id;
680 }
681 EXPORT_SYMBOL_GPL(ipu_di_get_num);
682 
683 static DEFINE_MUTEX(ipu_di_lock);
684 
685 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp)
686 {
687 	struct ipu_di *di;
688 
689 	if (disp > 1)
690 		return ERR_PTR(-EINVAL);
691 
692 	di = ipu->di_priv[disp];
693 
694 	mutex_lock(&ipu_di_lock);
695 
696 	if (di->inuse) {
697 		di = ERR_PTR(-EBUSY);
698 		goto out;
699 	}
700 
701 	di->inuse = true;
702 out:
703 	mutex_unlock(&ipu_di_lock);
704 
705 	return di;
706 }
707 EXPORT_SYMBOL_GPL(ipu_di_get);
708 
709 void ipu_di_put(struct ipu_di *di)
710 {
711 	mutex_lock(&ipu_di_lock);
712 
713 	di->inuse = false;
714 
715 	mutex_unlock(&ipu_di_lock);
716 }
717 EXPORT_SYMBOL_GPL(ipu_di_put);
718 
719 int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
720 		unsigned long base,
721 		u32 module, struct clk *clk_ipu)
722 {
723 	struct ipu_di *di;
724 
725 	if (id > 1)
726 		return -ENODEV;
727 
728 	di = devm_kzalloc(dev, sizeof(*di), GFP_KERNEL);
729 	if (!di)
730 		return -ENOMEM;
731 
732 	ipu->di_priv[id] = di;
733 
734 	di->clk_di = devm_clk_get(dev, id ? "di1" : "di0");
735 	if (IS_ERR(di->clk_di))
736 		return PTR_ERR(di->clk_di);
737 
738 	di->module = module;
739 	di->id = id;
740 	di->clk_ipu = clk_ipu;
741 	di->base = devm_ioremap(dev, base, PAGE_SIZE);
742 	if (!di->base)
743 		return -ENOMEM;
744 
745 	ipu_di_write(di, 0x10, DI_BS_CLKGEN0);
746 
747 	dev_dbg(dev, "DI%d base: 0x%08lx remapped to %p\n",
748 			id, base, di->base);
749 	di->inuse = false;
750 	di->ipu = ipu;
751 
752 	return 0;
753 }
754 
755 void ipu_di_exit(struct ipu_soc *ipu, int id)
756 {
757 }
758