xref: /openbmc/linux/drivers/gpu/ipu-v3/ipu-dc.c (revision 6852aa02)
1 /*
2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation; either version 2 of the License, or (at your
8  * option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13  * for more details.
14  */
15 
16 #include <linux/export.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/errno.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 
24 #include <video/imx-ipu-v3.h>
25 #include "ipu-prv.h"
26 
27 #define DC_MAP_CONF_PTR(n)	(0x108 + ((n) & ~0x1) * 2)
28 #define DC_MAP_CONF_VAL(n)	(0x144 + ((n) & ~0x1) * 2)
29 
30 #define DC_EVT_NF		0
31 #define DC_EVT_NL		1
32 #define DC_EVT_EOF		2
33 #define DC_EVT_NFIELD		3
34 #define DC_EVT_EOL		4
35 #define DC_EVT_EOFIELD		5
36 #define DC_EVT_NEW_ADDR		6
37 #define DC_EVT_NEW_CHAN		7
38 #define DC_EVT_NEW_DATA		8
39 
40 #define DC_EVT_NEW_ADDR_W_0	0
41 #define DC_EVT_NEW_ADDR_W_1	1
42 #define DC_EVT_NEW_CHAN_W_0	2
43 #define DC_EVT_NEW_CHAN_W_1	3
44 #define DC_EVT_NEW_DATA_W_0	4
45 #define DC_EVT_NEW_DATA_W_1	5
46 #define DC_EVT_NEW_ADDR_R_0	6
47 #define DC_EVT_NEW_ADDR_R_1	7
48 #define DC_EVT_NEW_CHAN_R_0	8
49 #define DC_EVT_NEW_CHAN_R_1	9
50 #define DC_EVT_NEW_DATA_R_0	10
51 #define DC_EVT_NEW_DATA_R_1	11
52 
53 #define DC_WR_CH_CONF		0x0
54 #define DC_WR_CH_ADDR		0x4
55 #define DC_RL_CH(evt)		(8 + ((evt) & ~0x1) * 2)
56 
57 #define DC_GEN			0xd4
58 #define DC_DISP_CONF1(disp)	(0xd8 + (disp) * 4)
59 #define DC_DISP_CONF2(disp)	(0xe8 + (disp) * 4)
60 #define DC_STAT			0x1c8
61 
62 #define WROD(lf)		(0x18 | ((lf) << 1))
63 #define WRG			0x01
64 #define WCLK			0xc9
65 
66 #define SYNC_WAVE 0
67 #define NULL_WAVE (-1)
68 
69 #define DC_GEN_SYNC_1_6_SYNC	(2 << 1)
70 #define DC_GEN_SYNC_PRIORITY_1	(1 << 7)
71 
72 #define DC_WR_CH_CONF_WORD_SIZE_8		(0 << 0)
73 #define DC_WR_CH_CONF_WORD_SIZE_16		(1 << 0)
74 #define DC_WR_CH_CONF_WORD_SIZE_24		(2 << 0)
75 #define DC_WR_CH_CONF_WORD_SIZE_32		(3 << 0)
76 #define DC_WR_CH_CONF_DISP_ID_PARALLEL(i)	(((i) & 0x1) << 3)
77 #define DC_WR_CH_CONF_DISP_ID_SERIAL		(2 << 3)
78 #define DC_WR_CH_CONF_DISP_ID_ASYNC		(3 << 4)
79 #define DC_WR_CH_CONF_FIELD_MODE		(1 << 9)
80 #define DC_WR_CH_CONF_PROG_TYPE_NORMAL		(4 << 5)
81 #define DC_WR_CH_CONF_PROG_TYPE_MASK		(7 << 5)
82 #define DC_WR_CH_CONF_PROG_DI_ID		(1 << 2)
83 #define DC_WR_CH_CONF_PROG_DISP_ID(i)		(((i) & 0x1) << 3)
84 
85 #define IPU_DC_NUM_CHANNELS	10
86 
87 struct ipu_dc_priv;
88 
89 enum ipu_dc_map {
90 	IPU_DC_MAP_RGB24,
91 	IPU_DC_MAP_RGB565,
92 	IPU_DC_MAP_GBR24, /* TVEv2 */
93 	IPU_DC_MAP_BGR666,
94 	IPU_DC_MAP_LVDS666,
95 	IPU_DC_MAP_BGR24,
96 };
97 
98 struct ipu_dc {
99 	/* The display interface number assigned to this dc channel */
100 	unsigned int		di;
101 	void __iomem		*base;
102 	struct ipu_dc_priv	*priv;
103 	int			chno;
104 	bool			in_use;
105 };
106 
107 struct ipu_dc_priv {
108 	void __iomem		*dc_reg;
109 	void __iomem		*dc_tmpl_reg;
110 	struct ipu_soc		*ipu;
111 	struct device		*dev;
112 	struct ipu_dc		channels[IPU_DC_NUM_CHANNELS];
113 	struct mutex		mutex;
114 	struct completion	comp;
115 	int			use_count;
116 };
117 
118 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
119 {
120 	u32 reg;
121 
122 	reg = readl(dc->base + DC_RL_CH(event));
123 	reg &= ~(0xffff << (16 * (event & 0x1)));
124 	reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
125 	writel(reg, dc->base + DC_RL_CH(event));
126 }
127 
128 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
129 		int map, int wave, int glue, int sync, int stop)
130 {
131 	struct ipu_dc_priv *priv = dc->priv;
132 	u32 reg1, reg2;
133 
134 	if (opcode == WCLK) {
135 		reg1 = (operand << 20) & 0xfff00000;
136 		reg2 = operand >> 12 | opcode << 1 | stop << 9;
137 	} else if (opcode == WRG) {
138 		reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
139 		reg2 = operand >> 17 | opcode << 7 | stop << 9;
140 	} else {
141 		reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
142 		reg2 = operand >> 12 | opcode << 4 | stop << 9;
143 	}
144 	writel(reg1, priv->dc_tmpl_reg + word * 8);
145 	writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
146 }
147 
148 static int ipu_bus_format_to_map(u32 fmt)
149 {
150 	switch (fmt) {
151 	default:
152 		WARN_ON(1);
153 		/* fall-through */
154 	case MEDIA_BUS_FMT_RGB888_1X24:
155 		return IPU_DC_MAP_RGB24;
156 	case MEDIA_BUS_FMT_RGB565_1X16:
157 		return IPU_DC_MAP_RGB565;
158 	case MEDIA_BUS_FMT_GBR888_1X24:
159 		return IPU_DC_MAP_GBR24;
160 	case MEDIA_BUS_FMT_RGB666_1X18:
161 		return IPU_DC_MAP_BGR666;
162 	case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
163 		return IPU_DC_MAP_LVDS666;
164 	case MEDIA_BUS_FMT_BGR888_1X24:
165 		return IPU_DC_MAP_BGR24;
166 	}
167 }
168 
169 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
170 		u32 bus_format, u32 width)
171 {
172 	struct ipu_dc_priv *priv = dc->priv;
173 	int addr, sync;
174 	u32 reg = 0;
175 	int map;
176 
177 	dc->di = ipu_di_get_num(di);
178 
179 	map = ipu_bus_format_to_map(bus_format);
180 
181 	/*
182 	 * In interlaced mode we need more counters to create the asymmetric
183 	 * per-field VSYNC signals. The pixel active signal synchronising DC
184 	 * to DI moves to signal generator #6 (see ipu-di.c). In progressive
185 	 * mode counter #5 is used.
186 	 */
187 	sync = interlaced ? 6 : 5;
188 
189 	/* Reserve 5 microcode template words for each DI */
190 	if (dc->di)
191 		addr = 5;
192 	else
193 		addr = 0;
194 
195 	if (interlaced) {
196 		dc_link_event(dc, DC_EVT_NL, addr, 3);
197 		dc_link_event(dc, DC_EVT_EOL, addr, 2);
198 		dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1);
199 
200 		/* Init template microcode */
201 		dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
202 	} else {
203 		dc_link_event(dc, DC_EVT_NL, addr + 2, 3);
204 		dc_link_event(dc, DC_EVT_EOL, addr + 3, 2);
205 		dc_link_event(dc, DC_EVT_NEW_DATA, addr + 1, 1);
206 
207 		/* Init template microcode */
208 		dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1);
209 		dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0);
210 		dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
211 		dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1);
212 	}
213 
214 	dc_link_event(dc, DC_EVT_NF, 0, 0);
215 	dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
216 	dc_link_event(dc, DC_EVT_EOF, 0, 0);
217 	dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
218 	dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
219 	dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
220 
221 	reg = readl(dc->base + DC_WR_CH_CONF);
222 	if (interlaced)
223 		reg |= DC_WR_CH_CONF_FIELD_MODE;
224 	else
225 		reg &= ~DC_WR_CH_CONF_FIELD_MODE;
226 	writel(reg, dc->base + DC_WR_CH_CONF);
227 
228 	writel(0x0, dc->base + DC_WR_CH_ADDR);
229 	writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
230 
231 	return 0;
232 }
233 EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
234 
235 void ipu_dc_enable(struct ipu_soc *ipu)
236 {
237 	struct ipu_dc_priv *priv = ipu->dc_priv;
238 
239 	mutex_lock(&priv->mutex);
240 
241 	if (!priv->use_count)
242 		ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
243 
244 	priv->use_count++;
245 
246 	mutex_unlock(&priv->mutex);
247 }
248 EXPORT_SYMBOL_GPL(ipu_dc_enable);
249 
250 void ipu_dc_enable_channel(struct ipu_dc *dc)
251 {
252 	int di;
253 	u32 reg;
254 
255 	di = dc->di;
256 
257 	reg = readl(dc->base + DC_WR_CH_CONF);
258 	reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
259 	writel(reg, dc->base + DC_WR_CH_CONF);
260 }
261 EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
262 
263 void ipu_dc_disable_channel(struct ipu_dc *dc)
264 {
265 	u32 val;
266 
267 	val = readl(dc->base + DC_WR_CH_CONF);
268 	val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
269 	writel(val, dc->base + DC_WR_CH_CONF);
270 }
271 EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
272 
273 void ipu_dc_disable(struct ipu_soc *ipu)
274 {
275 	struct ipu_dc_priv *priv = ipu->dc_priv;
276 
277 	mutex_lock(&priv->mutex);
278 
279 	priv->use_count--;
280 	if (!priv->use_count)
281 		ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);
282 
283 	if (priv->use_count < 0)
284 		priv->use_count = 0;
285 
286 	mutex_unlock(&priv->mutex);
287 }
288 EXPORT_SYMBOL_GPL(ipu_dc_disable);
289 
290 static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
291 		int byte_num, int offset, int mask)
292 {
293 	int ptr = map * 3 + byte_num;
294 	u32 reg;
295 
296 	reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
297 	reg &= ~(0xffff << (16 * (ptr & 0x1)));
298 	reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
299 	writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
300 
301 	reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
302 	reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
303 	reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
304 	writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
305 }
306 
307 static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
308 {
309 	u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
310 
311 	writel(reg & ~(0xffff << (16 * (map & 0x1))),
312 		     priv->dc_reg + DC_MAP_CONF_PTR(map));
313 }
314 
315 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
316 {
317 	struct ipu_dc_priv *priv = ipu->dc_priv;
318 	struct ipu_dc *dc;
319 
320 	if (channel >= IPU_DC_NUM_CHANNELS)
321 		return ERR_PTR(-ENODEV);
322 
323 	dc = &priv->channels[channel];
324 
325 	mutex_lock(&priv->mutex);
326 
327 	if (dc->in_use) {
328 		mutex_unlock(&priv->mutex);
329 		return ERR_PTR(-EBUSY);
330 	}
331 
332 	dc->in_use = true;
333 
334 	mutex_unlock(&priv->mutex);
335 
336 	return dc;
337 }
338 EXPORT_SYMBOL_GPL(ipu_dc_get);
339 
340 void ipu_dc_put(struct ipu_dc *dc)
341 {
342 	struct ipu_dc_priv *priv = dc->priv;
343 
344 	mutex_lock(&priv->mutex);
345 	dc->in_use = false;
346 	mutex_unlock(&priv->mutex);
347 }
348 EXPORT_SYMBOL_GPL(ipu_dc_put);
349 
350 int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
351 		unsigned long base, unsigned long template_base)
352 {
353 	struct ipu_dc_priv *priv;
354 	static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
355 		0x78, 0, 0x94, 0xb4};
356 	int i;
357 
358 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
359 	if (!priv)
360 		return -ENOMEM;
361 
362 	mutex_init(&priv->mutex);
363 
364 	priv->dev = dev;
365 	priv->ipu = ipu;
366 	priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
367 	priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
368 	if (!priv->dc_reg || !priv->dc_tmpl_reg)
369 		return -ENOMEM;
370 
371 	for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
372 		priv->channels[i].chno = i;
373 		priv->channels[i].priv = priv;
374 		priv->channels[i].base = priv->dc_reg + channel_offsets[i];
375 	}
376 
377 	writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
378 			DC_WR_CH_CONF_PROG_DI_ID,
379 			priv->channels[1].base + DC_WR_CH_CONF);
380 	writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
381 			priv->channels[5].base + DC_WR_CH_CONF);
382 
383 	writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1,
384 		priv->dc_reg + DC_GEN);
385 
386 	ipu->dc_priv = priv;
387 
388 	dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
389 			base, template_base);
390 
391 	/* rgb24 */
392 	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
393 	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
394 	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
395 	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
396 
397 	/* rgb565 */
398 	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
399 	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
400 	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
401 	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
402 
403 	/* gbr24 */
404 	ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
405 	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
406 	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
407 	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
408 
409 	/* bgr666 */
410 	ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
411 	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
412 	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
413 	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
414 
415 	/* lvds666 */
416 	ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
417 	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */
418 	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */
419 	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */
420 
421 	/* bgr24 */
422 	ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
423 	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
424 	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
425 	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
426 
427 	return 0;
428 }
429 
430 void ipu_dc_exit(struct ipu_soc *ipu)
431 {
432 }
433