1 /* 2 * Copyright (C) 2012-2014 Mentor Graphics Inc. 3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 */ 15 #include <linux/export.h> 16 #include <linux/module.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/delay.h> 20 #include <linux/io.h> 21 #include <linux/err.h> 22 #include <linux/platform_device.h> 23 #include <linux/videodev2.h> 24 #include <uapi/linux/v4l2-mediabus.h> 25 #include <linux/clk.h> 26 #include <linux/clk-provider.h> 27 #include <linux/clkdev.h> 28 29 #include "ipu-prv.h" 30 31 struct ipu_csi { 32 void __iomem *base; 33 int id; 34 u32 module; 35 struct clk *clk_ipu; /* IPU bus clock */ 36 spinlock_t lock; 37 bool inuse; 38 struct ipu_soc *ipu; 39 }; 40 41 /* CSI Register Offsets */ 42 #define CSI_SENS_CONF 0x0000 43 #define CSI_SENS_FRM_SIZE 0x0004 44 #define CSI_ACT_FRM_SIZE 0x0008 45 #define CSI_OUT_FRM_CTRL 0x000c 46 #define CSI_TST_CTRL 0x0010 47 #define CSI_CCIR_CODE_1 0x0014 48 #define CSI_CCIR_CODE_2 0x0018 49 #define CSI_CCIR_CODE_3 0x001c 50 #define CSI_MIPI_DI 0x0020 51 #define CSI_SKIP 0x0024 52 #define CSI_CPD_CTRL 0x0028 53 #define CSI_CPD_RC(n) (0x002c + ((n)*4)) 54 #define CSI_CPD_RS(n) (0x004c + ((n)*4)) 55 #define CSI_CPD_GRC(n) (0x005c + ((n)*4)) 56 #define CSI_CPD_GRS(n) (0x007c + ((n)*4)) 57 #define CSI_CPD_GBC(n) (0x008c + ((n)*4)) 58 #define CSI_CPD_GBS(n) (0x00Ac + ((n)*4)) 59 #define CSI_CPD_BC(n) (0x00Bc + ((n)*4)) 60 #define CSI_CPD_BS(n) (0x00Dc + ((n)*4)) 61 #define CSI_CPD_OFFSET1 0x00ec 62 #define CSI_CPD_OFFSET2 0x00f0 63 64 /* CSI Register Fields */ 65 #define CSI_SENS_CONF_DATA_FMT_SHIFT 8 66 #define CSI_SENS_CONF_DATA_FMT_MASK 0x00000700 67 #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 0L 68 #define CSI_SENS_CONF_DATA_FMT_YUV422_YUYV 1L 69 #define CSI_SENS_CONF_DATA_FMT_YUV422_UYVY 2L 70 #define CSI_SENS_CONF_DATA_FMT_BAYER 3L 71 #define CSI_SENS_CONF_DATA_FMT_RGB565 4L 72 #define CSI_SENS_CONF_DATA_FMT_RGB555 5L 73 #define CSI_SENS_CONF_DATA_FMT_RGB444 6L 74 #define CSI_SENS_CONF_DATA_FMT_JPEG 7L 75 76 #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0 77 #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1 78 #define CSI_SENS_CONF_DATA_POL_SHIFT 2 79 #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3 80 #define CSI_SENS_CONF_SENS_PRTCL_MASK 0x00000070 81 #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4 82 #define CSI_SENS_CONF_PACK_TIGHT_SHIFT 7 83 #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 11 84 #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15 85 #define CSI_SENS_CONF_DIVRATIO_SHIFT 16 86 87 #define CSI_SENS_CONF_DIVRATIO_MASK 0x00ff0000 88 #define CSI_SENS_CONF_DATA_DEST_SHIFT 24 89 #define CSI_SENS_CONF_DATA_DEST_MASK 0x07000000 90 #define CSI_SENS_CONF_JPEG8_EN_SHIFT 27 91 #define CSI_SENS_CONF_JPEG_EN_SHIFT 28 92 #define CSI_SENS_CONF_FORCE_EOF_SHIFT 29 93 #define CSI_SENS_CONF_DATA_EN_POL_SHIFT 31 94 95 #define CSI_DATA_DEST_IC 2 96 #define CSI_DATA_DEST_IDMAC 4 97 98 #define CSI_CCIR_ERR_DET_EN 0x01000000 99 #define CSI_HORI_DOWNSIZE_EN 0x80000000 100 #define CSI_VERT_DOWNSIZE_EN 0x40000000 101 #define CSI_TEST_GEN_MODE_EN 0x01000000 102 103 #define CSI_HSC_MASK 0x1fff0000 104 #define CSI_HSC_SHIFT 16 105 #define CSI_VSC_MASK 0x00000fff 106 #define CSI_VSC_SHIFT 0 107 108 #define CSI_TEST_GEN_R_MASK 0x000000ff 109 #define CSI_TEST_GEN_R_SHIFT 0 110 #define CSI_TEST_GEN_G_MASK 0x0000ff00 111 #define CSI_TEST_GEN_G_SHIFT 8 112 #define CSI_TEST_GEN_B_MASK 0x00ff0000 113 #define CSI_TEST_GEN_B_SHIFT 16 114 115 #define CSI_MAX_RATIO_SKIP_SMFC_MASK 0x00000007 116 #define CSI_MAX_RATIO_SKIP_SMFC_SHIFT 0 117 #define CSI_SKIP_SMFC_MASK 0x000000f8 118 #define CSI_SKIP_SMFC_SHIFT 3 119 #define CSI_ID_2_SKIP_MASK 0x00000300 120 #define CSI_ID_2_SKIP_SHIFT 8 121 122 #define CSI_COLOR_FIRST_ROW_MASK 0x00000002 123 #define CSI_COLOR_FIRST_COMP_MASK 0x00000001 124 125 /* MIPI CSI-2 data types */ 126 #define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */ 127 #define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */ 128 #define MIPI_DT_YUV422 0x1e /* UYVY... */ 129 #define MIPI_DT_RGB444 0x20 130 #define MIPI_DT_RGB555 0x21 131 #define MIPI_DT_RGB565 0x22 132 #define MIPI_DT_RGB666 0x23 133 #define MIPI_DT_RGB888 0x24 134 #define MIPI_DT_RAW6 0x28 135 #define MIPI_DT_RAW7 0x29 136 #define MIPI_DT_RAW8 0x2a 137 #define MIPI_DT_RAW10 0x2b 138 #define MIPI_DT_RAW12 0x2c 139 #define MIPI_DT_RAW14 0x2d 140 141 /* 142 * Bitfield of CSI bus signal polarities and modes. 143 */ 144 struct ipu_csi_bus_config { 145 unsigned data_width:4; 146 unsigned clk_mode:3; 147 unsigned ext_vsync:1; 148 unsigned vsync_pol:1; 149 unsigned hsync_pol:1; 150 unsigned pixclk_pol:1; 151 unsigned data_pol:1; 152 unsigned sens_clksrc:1; 153 unsigned pack_tight:1; 154 unsigned force_eof:1; 155 unsigned data_en_pol:1; 156 157 unsigned data_fmt; 158 unsigned mipi_dt; 159 }; 160 161 /* 162 * Enumeration of CSI data bus widths. 163 */ 164 enum ipu_csi_data_width { 165 IPU_CSI_DATA_WIDTH_4 = 0, 166 IPU_CSI_DATA_WIDTH_8 = 1, 167 IPU_CSI_DATA_WIDTH_10 = 3, 168 IPU_CSI_DATA_WIDTH_12 = 5, 169 IPU_CSI_DATA_WIDTH_16 = 9, 170 }; 171 172 /* 173 * Enumeration of CSI clock modes. 174 */ 175 enum ipu_csi_clk_mode { 176 IPU_CSI_CLK_MODE_GATED_CLK, 177 IPU_CSI_CLK_MODE_NONGATED_CLK, 178 IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE, 179 IPU_CSI_CLK_MODE_CCIR656_INTERLACED, 180 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR, 181 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR, 182 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR, 183 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR, 184 }; 185 186 static inline u32 ipu_csi_read(struct ipu_csi *csi, unsigned offset) 187 { 188 return readl(csi->base + offset); 189 } 190 191 static inline void ipu_csi_write(struct ipu_csi *csi, u32 value, 192 unsigned offset) 193 { 194 writel(value, csi->base + offset); 195 } 196 197 /* 198 * Set mclk division ratio for generating test mode mclk. Only used 199 * for test generator. 200 */ 201 static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk, 202 u32 ipu_clk) 203 { 204 u32 temp; 205 int div_ratio; 206 207 div_ratio = (ipu_clk / pixel_clk) - 1; 208 209 if (div_ratio > 0xFF || div_ratio < 0) { 210 dev_err(csi->ipu->dev, 211 "value of pixel_clk extends normal range\n"); 212 return -EINVAL; 213 } 214 215 temp = ipu_csi_read(csi, CSI_SENS_CONF); 216 temp &= ~CSI_SENS_CONF_DIVRATIO_MASK; 217 ipu_csi_write(csi, temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT), 218 CSI_SENS_CONF); 219 220 return 0; 221 } 222 223 /* 224 * Find the CSI data format and data width for the given V4L2 media 225 * bus pixel format code. 226 */ 227 static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code, 228 enum v4l2_mbus_type mbus_type) 229 { 230 switch (mbus_code) { 231 case MEDIA_BUS_FMT_BGR565_2X8_BE: 232 case MEDIA_BUS_FMT_BGR565_2X8_LE: 233 case MEDIA_BUS_FMT_RGB565_2X8_BE: 234 case MEDIA_BUS_FMT_RGB565_2X8_LE: 235 if (mbus_type == V4L2_MBUS_CSI2_DPHY) 236 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565; 237 else 238 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER; 239 cfg->mipi_dt = MIPI_DT_RGB565; 240 cfg->data_width = IPU_CSI_DATA_WIDTH_8; 241 break; 242 case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE: 243 case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE: 244 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB444; 245 cfg->mipi_dt = MIPI_DT_RGB444; 246 cfg->data_width = IPU_CSI_DATA_WIDTH_8; 247 break; 248 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE: 249 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: 250 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555; 251 cfg->mipi_dt = MIPI_DT_RGB555; 252 cfg->data_width = IPU_CSI_DATA_WIDTH_8; 253 break; 254 case MEDIA_BUS_FMT_RGB888_1X24: 255 case MEDIA_BUS_FMT_BGR888_1X24: 256 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444; 257 cfg->mipi_dt = MIPI_DT_RGB888; 258 cfg->data_width = IPU_CSI_DATA_WIDTH_8; 259 break; 260 case MEDIA_BUS_FMT_UYVY8_2X8: 261 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY; 262 cfg->mipi_dt = MIPI_DT_YUV422; 263 cfg->data_width = IPU_CSI_DATA_WIDTH_8; 264 break; 265 case MEDIA_BUS_FMT_YUYV8_2X8: 266 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV; 267 cfg->mipi_dt = MIPI_DT_YUV422; 268 cfg->data_width = IPU_CSI_DATA_WIDTH_8; 269 break; 270 case MEDIA_BUS_FMT_UYVY8_1X16: 271 case MEDIA_BUS_FMT_YUYV8_1X16: 272 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER; 273 cfg->mipi_dt = MIPI_DT_YUV422; 274 cfg->data_width = IPU_CSI_DATA_WIDTH_16; 275 break; 276 case MEDIA_BUS_FMT_SBGGR8_1X8: 277 case MEDIA_BUS_FMT_SGBRG8_1X8: 278 case MEDIA_BUS_FMT_SGRBG8_1X8: 279 case MEDIA_BUS_FMT_SRGGB8_1X8: 280 case MEDIA_BUS_FMT_Y8_1X8: 281 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER; 282 cfg->mipi_dt = MIPI_DT_RAW8; 283 cfg->data_width = IPU_CSI_DATA_WIDTH_8; 284 break; 285 case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8: 286 case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8: 287 case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8: 288 case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8: 289 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE: 290 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE: 291 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE: 292 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE: 293 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER; 294 cfg->mipi_dt = MIPI_DT_RAW10; 295 cfg->data_width = IPU_CSI_DATA_WIDTH_8; 296 break; 297 case MEDIA_BUS_FMT_SBGGR10_1X10: 298 case MEDIA_BUS_FMT_SGBRG10_1X10: 299 case MEDIA_BUS_FMT_SGRBG10_1X10: 300 case MEDIA_BUS_FMT_SRGGB10_1X10: 301 case MEDIA_BUS_FMT_Y10_1X10: 302 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER; 303 cfg->mipi_dt = MIPI_DT_RAW10; 304 cfg->data_width = IPU_CSI_DATA_WIDTH_10; 305 break; 306 case MEDIA_BUS_FMT_SBGGR12_1X12: 307 case MEDIA_BUS_FMT_SGBRG12_1X12: 308 case MEDIA_BUS_FMT_SGRBG12_1X12: 309 case MEDIA_BUS_FMT_SRGGB12_1X12: 310 case MEDIA_BUS_FMT_Y12_1X12: 311 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER; 312 cfg->mipi_dt = MIPI_DT_RAW12; 313 cfg->data_width = IPU_CSI_DATA_WIDTH_12; 314 break; 315 case MEDIA_BUS_FMT_JPEG_1X8: 316 /* TODO */ 317 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_JPEG; 318 cfg->mipi_dt = MIPI_DT_RAW8; 319 cfg->data_width = IPU_CSI_DATA_WIDTH_8; 320 break; 321 default: 322 return -EINVAL; 323 } 324 325 return 0; 326 } 327 328 /* 329 * Fill a CSI bus config struct from mbus_config and mbus_framefmt. 330 */ 331 static int fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg, 332 struct v4l2_mbus_config *mbus_cfg, 333 struct v4l2_mbus_framefmt *mbus_fmt) 334 { 335 int ret; 336 337 memset(csicfg, 0, sizeof(*csicfg)); 338 339 ret = mbus_code_to_bus_cfg(csicfg, mbus_fmt->code, mbus_cfg->type); 340 if (ret < 0) 341 return ret; 342 343 switch (mbus_cfg->type) { 344 case V4L2_MBUS_PARALLEL: 345 csicfg->ext_vsync = 1; 346 csicfg->vsync_pol = (mbus_cfg->flags & 347 V4L2_MBUS_VSYNC_ACTIVE_LOW) ? 1 : 0; 348 csicfg->hsync_pol = (mbus_cfg->flags & 349 V4L2_MBUS_HSYNC_ACTIVE_LOW) ? 1 : 0; 350 csicfg->pixclk_pol = (mbus_cfg->flags & 351 V4L2_MBUS_PCLK_SAMPLE_FALLING) ? 1 : 0; 352 csicfg->clk_mode = IPU_CSI_CLK_MODE_GATED_CLK; 353 break; 354 case V4L2_MBUS_BT656: 355 csicfg->ext_vsync = 0; 356 if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field) || 357 mbus_fmt->field == V4L2_FIELD_ALTERNATE) 358 csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED; 359 else 360 csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE; 361 break; 362 case V4L2_MBUS_CSI2_DPHY: 363 /* 364 * MIPI CSI-2 requires non gated clock mode, all other 365 * parameters are not applicable for MIPI CSI-2 bus. 366 */ 367 csicfg->clk_mode = IPU_CSI_CLK_MODE_NONGATED_CLK; 368 break; 369 default: 370 /* will never get here, keep compiler quiet */ 371 break; 372 } 373 374 return 0; 375 } 376 377 int ipu_csi_init_interface(struct ipu_csi *csi, 378 struct v4l2_mbus_config *mbus_cfg, 379 struct v4l2_mbus_framefmt *mbus_fmt) 380 { 381 struct ipu_csi_bus_config cfg; 382 unsigned long flags; 383 u32 width, height, data = 0; 384 int ret; 385 386 ret = fill_csi_bus_cfg(&cfg, mbus_cfg, mbus_fmt); 387 if (ret < 0) 388 return ret; 389 390 /* set default sensor frame width and height */ 391 width = mbus_fmt->width; 392 height = mbus_fmt->height; 393 394 /* Set the CSI_SENS_CONF register remaining fields */ 395 data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT | 396 cfg.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT | 397 cfg.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT | 398 cfg.vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT | 399 cfg.hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT | 400 cfg.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT | 401 cfg.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT | 402 cfg.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT | 403 cfg.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT | 404 cfg.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT | 405 cfg.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT; 406 407 spin_lock_irqsave(&csi->lock, flags); 408 409 ipu_csi_write(csi, data, CSI_SENS_CONF); 410 411 /* Set CCIR registers */ 412 413 switch (cfg.clk_mode) { 414 case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE: 415 ipu_csi_write(csi, 0x40030, CSI_CCIR_CODE_1); 416 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3); 417 break; 418 case IPU_CSI_CLK_MODE_CCIR656_INTERLACED: 419 if (mbus_fmt->width == 720 && mbus_fmt->height == 576) { 420 /* 421 * PAL case 422 * 423 * Field0BlankEnd = 0x6, Field0BlankStart = 0x2, 424 * Field0ActiveEnd = 0x4, Field0ActiveStart = 0 425 * Field1BlankEnd = 0x7, Field1BlankStart = 0x3, 426 * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1 427 */ 428 height = 625; /* framelines for PAL */ 429 430 ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN, 431 CSI_CCIR_CODE_1); 432 ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2); 433 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3); 434 } else if (mbus_fmt->width == 720 && mbus_fmt->height == 480) { 435 /* 436 * NTSC case 437 * 438 * Field0BlankEnd = 0x7, Field0BlankStart = 0x3, 439 * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1 440 * Field1BlankEnd = 0x6, Field1BlankStart = 0x2, 441 * Field1ActiveEnd = 0x4, Field1ActiveStart = 0 442 */ 443 height = 525; /* framelines for NTSC */ 444 445 ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN, 446 CSI_CCIR_CODE_1); 447 ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2); 448 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3); 449 } else { 450 dev_err(csi->ipu->dev, 451 "Unsupported CCIR656 interlaced video mode\n"); 452 spin_unlock_irqrestore(&csi->lock, flags); 453 return -EINVAL; 454 } 455 break; 456 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR: 457 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR: 458 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR: 459 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR: 460 ipu_csi_write(csi, 0x40030 | CSI_CCIR_ERR_DET_EN, 461 CSI_CCIR_CODE_1); 462 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3); 463 break; 464 case IPU_CSI_CLK_MODE_GATED_CLK: 465 case IPU_CSI_CLK_MODE_NONGATED_CLK: 466 ipu_csi_write(csi, 0, CSI_CCIR_CODE_1); 467 break; 468 } 469 470 /* Setup sensor frame size */ 471 ipu_csi_write(csi, (width - 1) | ((height - 1) << 16), 472 CSI_SENS_FRM_SIZE); 473 474 dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n", 475 ipu_csi_read(csi, CSI_SENS_CONF)); 476 dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n", 477 ipu_csi_read(csi, CSI_ACT_FRM_SIZE)); 478 479 spin_unlock_irqrestore(&csi->lock, flags); 480 481 return 0; 482 } 483 EXPORT_SYMBOL_GPL(ipu_csi_init_interface); 484 485 bool ipu_csi_is_interlaced(struct ipu_csi *csi) 486 { 487 unsigned long flags; 488 u32 sensor_protocol; 489 490 spin_lock_irqsave(&csi->lock, flags); 491 sensor_protocol = 492 (ipu_csi_read(csi, CSI_SENS_CONF) & 493 CSI_SENS_CONF_SENS_PRTCL_MASK) >> 494 CSI_SENS_CONF_SENS_PRTCL_SHIFT; 495 spin_unlock_irqrestore(&csi->lock, flags); 496 497 switch (sensor_protocol) { 498 case IPU_CSI_CLK_MODE_GATED_CLK: 499 case IPU_CSI_CLK_MODE_NONGATED_CLK: 500 case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE: 501 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR: 502 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR: 503 return false; 504 case IPU_CSI_CLK_MODE_CCIR656_INTERLACED: 505 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR: 506 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR: 507 return true; 508 default: 509 dev_err(csi->ipu->dev, 510 "CSI %d sensor protocol unsupported\n", csi->id); 511 return false; 512 } 513 } 514 EXPORT_SYMBOL_GPL(ipu_csi_is_interlaced); 515 516 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w) 517 { 518 unsigned long flags; 519 u32 reg; 520 521 spin_lock_irqsave(&csi->lock, flags); 522 523 reg = ipu_csi_read(csi, CSI_ACT_FRM_SIZE); 524 w->width = (reg & 0xFFFF) + 1; 525 w->height = (reg >> 16 & 0xFFFF) + 1; 526 527 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL); 528 w->left = (reg & CSI_HSC_MASK) >> CSI_HSC_SHIFT; 529 w->top = (reg & CSI_VSC_MASK) >> CSI_VSC_SHIFT; 530 531 spin_unlock_irqrestore(&csi->lock, flags); 532 } 533 EXPORT_SYMBOL_GPL(ipu_csi_get_window); 534 535 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w) 536 { 537 unsigned long flags; 538 u32 reg; 539 540 spin_lock_irqsave(&csi->lock, flags); 541 542 ipu_csi_write(csi, (w->width - 1) | ((w->height - 1) << 16), 543 CSI_ACT_FRM_SIZE); 544 545 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL); 546 reg &= ~(CSI_HSC_MASK | CSI_VSC_MASK); 547 reg |= ((w->top << CSI_VSC_SHIFT) | (w->left << CSI_HSC_SHIFT)); 548 ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL); 549 550 spin_unlock_irqrestore(&csi->lock, flags); 551 } 552 EXPORT_SYMBOL_GPL(ipu_csi_set_window); 553 554 void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert) 555 { 556 unsigned long flags; 557 u32 reg; 558 559 spin_lock_irqsave(&csi->lock, flags); 560 561 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL); 562 reg &= ~(CSI_HORI_DOWNSIZE_EN | CSI_VERT_DOWNSIZE_EN); 563 reg |= (horiz ? CSI_HORI_DOWNSIZE_EN : 0) | 564 (vert ? CSI_VERT_DOWNSIZE_EN : 0); 565 ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL); 566 567 spin_unlock_irqrestore(&csi->lock, flags); 568 } 569 EXPORT_SYMBOL_GPL(ipu_csi_set_downsize); 570 571 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active, 572 u32 r_value, u32 g_value, u32 b_value, 573 u32 pix_clk) 574 { 575 unsigned long flags; 576 u32 ipu_clk = clk_get_rate(csi->clk_ipu); 577 u32 temp; 578 579 spin_lock_irqsave(&csi->lock, flags); 580 581 temp = ipu_csi_read(csi, CSI_TST_CTRL); 582 583 if (!active) { 584 temp &= ~CSI_TEST_GEN_MODE_EN; 585 ipu_csi_write(csi, temp, CSI_TST_CTRL); 586 } else { 587 /* Set sensb_mclk div_ratio */ 588 ipu_csi_set_testgen_mclk(csi, pix_clk, ipu_clk); 589 590 temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK | 591 CSI_TEST_GEN_B_MASK); 592 temp |= CSI_TEST_GEN_MODE_EN; 593 temp |= (r_value << CSI_TEST_GEN_R_SHIFT) | 594 (g_value << CSI_TEST_GEN_G_SHIFT) | 595 (b_value << CSI_TEST_GEN_B_SHIFT); 596 ipu_csi_write(csi, temp, CSI_TST_CTRL); 597 } 598 599 spin_unlock_irqrestore(&csi->lock, flags); 600 } 601 EXPORT_SYMBOL_GPL(ipu_csi_set_test_generator); 602 603 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc, 604 struct v4l2_mbus_framefmt *mbus_fmt) 605 { 606 struct ipu_csi_bus_config cfg; 607 unsigned long flags; 608 u32 temp; 609 int ret; 610 611 if (vc > 3) 612 return -EINVAL; 613 614 ret = mbus_code_to_bus_cfg(&cfg, mbus_fmt->code, V4L2_MBUS_CSI2_DPHY); 615 if (ret < 0) 616 return ret; 617 618 spin_lock_irqsave(&csi->lock, flags); 619 620 temp = ipu_csi_read(csi, CSI_MIPI_DI); 621 temp &= ~(0xff << (vc * 8)); 622 temp |= (cfg.mipi_dt << (vc * 8)); 623 ipu_csi_write(csi, temp, CSI_MIPI_DI); 624 625 spin_unlock_irqrestore(&csi->lock, flags); 626 627 return 0; 628 } 629 EXPORT_SYMBOL_GPL(ipu_csi_set_mipi_datatype); 630 631 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip, 632 u32 max_ratio, u32 id) 633 { 634 unsigned long flags; 635 u32 temp; 636 637 if (max_ratio > 5 || id > 3) 638 return -EINVAL; 639 640 spin_lock_irqsave(&csi->lock, flags); 641 642 temp = ipu_csi_read(csi, CSI_SKIP); 643 temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK | 644 CSI_SKIP_SMFC_MASK); 645 temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) | 646 (id << CSI_ID_2_SKIP_SHIFT) | 647 (skip << CSI_SKIP_SMFC_SHIFT); 648 ipu_csi_write(csi, temp, CSI_SKIP); 649 650 spin_unlock_irqrestore(&csi->lock, flags); 651 652 return 0; 653 } 654 EXPORT_SYMBOL_GPL(ipu_csi_set_skip_smfc); 655 656 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest) 657 { 658 unsigned long flags; 659 u32 csi_sens_conf, dest; 660 661 if (csi_dest == IPU_CSI_DEST_IDMAC) 662 dest = CSI_DATA_DEST_IDMAC; 663 else 664 dest = CSI_DATA_DEST_IC; /* IC or VDIC */ 665 666 spin_lock_irqsave(&csi->lock, flags); 667 668 csi_sens_conf = ipu_csi_read(csi, CSI_SENS_CONF); 669 csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK; 670 csi_sens_conf |= (dest << CSI_SENS_CONF_DATA_DEST_SHIFT); 671 ipu_csi_write(csi, csi_sens_conf, CSI_SENS_CONF); 672 673 spin_unlock_irqrestore(&csi->lock, flags); 674 675 return 0; 676 } 677 EXPORT_SYMBOL_GPL(ipu_csi_set_dest); 678 679 int ipu_csi_enable(struct ipu_csi *csi) 680 { 681 ipu_module_enable(csi->ipu, csi->module); 682 683 return 0; 684 } 685 EXPORT_SYMBOL_GPL(ipu_csi_enable); 686 687 int ipu_csi_disable(struct ipu_csi *csi) 688 { 689 ipu_module_disable(csi->ipu, csi->module); 690 691 return 0; 692 } 693 EXPORT_SYMBOL_GPL(ipu_csi_disable); 694 695 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id) 696 { 697 unsigned long flags; 698 struct ipu_csi *csi, *ret; 699 700 if (id > 1) 701 return ERR_PTR(-EINVAL); 702 703 csi = ipu->csi_priv[id]; 704 ret = csi; 705 706 spin_lock_irqsave(&csi->lock, flags); 707 708 if (csi->inuse) { 709 ret = ERR_PTR(-EBUSY); 710 goto unlock; 711 } 712 713 csi->inuse = true; 714 unlock: 715 spin_unlock_irqrestore(&csi->lock, flags); 716 return ret; 717 } 718 EXPORT_SYMBOL_GPL(ipu_csi_get); 719 720 void ipu_csi_put(struct ipu_csi *csi) 721 { 722 unsigned long flags; 723 724 spin_lock_irqsave(&csi->lock, flags); 725 csi->inuse = false; 726 spin_unlock_irqrestore(&csi->lock, flags); 727 } 728 EXPORT_SYMBOL_GPL(ipu_csi_put); 729 730 int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id, 731 unsigned long base, u32 module, struct clk *clk_ipu) 732 { 733 struct ipu_csi *csi; 734 735 if (id > 1) 736 return -ENODEV; 737 738 csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL); 739 if (!csi) 740 return -ENOMEM; 741 742 ipu->csi_priv[id] = csi; 743 744 spin_lock_init(&csi->lock); 745 csi->module = module; 746 csi->id = id; 747 csi->clk_ipu = clk_ipu; 748 csi->base = devm_ioremap(dev, base, PAGE_SIZE); 749 if (!csi->base) 750 return -ENOMEM; 751 752 dev_dbg(dev, "CSI%d base: 0x%08lx remapped to %p\n", 753 id, base, csi->base); 754 csi->ipu = ipu; 755 756 return 0; 757 } 758 759 void ipu_csi_exit(struct ipu_soc *ipu, int id) 760 { 761 } 762 763 void ipu_csi_dump(struct ipu_csi *csi) 764 { 765 dev_dbg(csi->ipu->dev, "CSI_SENS_CONF: %08x\n", 766 ipu_csi_read(csi, CSI_SENS_CONF)); 767 dev_dbg(csi->ipu->dev, "CSI_SENS_FRM_SIZE: %08x\n", 768 ipu_csi_read(csi, CSI_SENS_FRM_SIZE)); 769 dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE: %08x\n", 770 ipu_csi_read(csi, CSI_ACT_FRM_SIZE)); 771 dev_dbg(csi->ipu->dev, "CSI_OUT_FRM_CTRL: %08x\n", 772 ipu_csi_read(csi, CSI_OUT_FRM_CTRL)); 773 dev_dbg(csi->ipu->dev, "CSI_TST_CTRL: %08x\n", 774 ipu_csi_read(csi, CSI_TST_CTRL)); 775 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_1: %08x\n", 776 ipu_csi_read(csi, CSI_CCIR_CODE_1)); 777 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_2: %08x\n", 778 ipu_csi_read(csi, CSI_CCIR_CODE_2)); 779 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_3: %08x\n", 780 ipu_csi_read(csi, CSI_CCIR_CODE_3)); 781 dev_dbg(csi->ipu->dev, "CSI_MIPI_DI: %08x\n", 782 ipu_csi_read(csi, CSI_MIPI_DI)); 783 dev_dbg(csi->ipu->dev, "CSI_SKIP: %08x\n", 784 ipu_csi_read(csi, CSI_SKIP)); 785 } 786 EXPORT_SYMBOL_GPL(ipu_csi_dump); 787