1 /* 2 * Copyright (C) 2012 Mentor Graphics Inc. 3 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 #include <linux/types.h> 13 #include <linux/bitrev.h> 14 #include <linux/io.h> 15 #include <drm/drm_fourcc.h> 16 #include "ipu-prv.h" 17 18 struct ipu_cpmem_word { 19 u32 data[5]; 20 u32 res[3]; 21 }; 22 23 struct ipu_ch_param { 24 struct ipu_cpmem_word word[2]; 25 }; 26 27 struct ipu_cpmem { 28 struct ipu_ch_param __iomem *base; 29 u32 module; 30 spinlock_t lock; 31 int use_count; 32 struct ipu_soc *ipu; 33 }; 34 35 #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size)) 36 37 #define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22) 38 #define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22) 39 #define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4) 40 #define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1) 41 #define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1) 42 #define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14) 43 #define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14) 44 45 #define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10) 46 #define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9) 47 #define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13) 48 #define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12) 49 #define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1) 50 #define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1) 51 #define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12) 52 #define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11) 53 #define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10) 54 #define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7) 55 #define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10) 56 #define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1) 57 #define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1) 58 #define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7) 59 #define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1) 60 #define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1) 61 #define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3) 62 #define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2) 63 #define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1) 64 #define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3) 65 #define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2) 66 #define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1) 67 #define IPU_FIELD_ROT_HF_VF IPU_CPMEM_WORD(0, 119, 3) 68 #define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1) 69 #define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1) 70 #define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1) 71 #define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1) 72 #define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1) 73 #define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13) 74 #define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12) 75 #define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29) 76 #define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29) 77 #define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20) 78 #define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7) 79 #define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4) 80 #define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1) 81 #define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3) 82 #define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2) 83 #define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7) 84 #define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14) 85 #define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3) 86 #define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3) 87 #define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3) 88 #define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3) 89 #define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5) 90 #define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5) 91 #define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5) 92 #define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5) 93 #define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1) 94 #define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1) 95 #define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1) 96 97 static inline struct ipu_ch_param __iomem * 98 ipu_get_cpmem(struct ipuv3_channel *ch) 99 { 100 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; 101 102 return cpmem->base + ch->num; 103 } 104 105 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) 106 { 107 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); 108 u32 bit = (wbs >> 8) % 160; 109 u32 size = wbs & 0xff; 110 u32 word = (wbs >> 8) / 160; 111 u32 i = bit / 32; 112 u32 ofs = bit % 32; 113 u32 mask = (1 << size) - 1; 114 u32 val; 115 116 pr_debug("%s %d %d %d\n", __func__, word, bit , size); 117 118 val = readl(&base->word[word].data[i]); 119 val &= ~(mask << ofs); 120 val |= v << ofs; 121 writel(val, &base->word[word].data[i]); 122 123 if ((bit + size - 1) / 32 > i) { 124 val = readl(&base->word[word].data[i + 1]); 125 val &= ~(mask >> (ofs ? (32 - ofs) : 0)); 126 val |= v >> (ofs ? (32 - ofs) : 0); 127 writel(val, &base->word[word].data[i + 1]); 128 } 129 } 130 131 static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs) 132 { 133 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); 134 u32 bit = (wbs >> 8) % 160; 135 u32 size = wbs & 0xff; 136 u32 word = (wbs >> 8) / 160; 137 u32 i = bit / 32; 138 u32 ofs = bit % 32; 139 u32 mask = (1 << size) - 1; 140 u32 val = 0; 141 142 pr_debug("%s %d %d %d\n", __func__, word, bit , size); 143 144 val = (readl(&base->word[word].data[i]) >> ofs) & mask; 145 146 if ((bit + size - 1) / 32 > i) { 147 u32 tmp; 148 149 tmp = readl(&base->word[word].data[i + 1]); 150 tmp &= mask >> (ofs ? (32 - ofs) : 0); 151 val |= tmp << (ofs ? (32 - ofs) : 0); 152 } 153 154 return val; 155 } 156 157 /* 158 * The V4L2 spec defines packed RGB formats in memory byte order, which from 159 * point of view of the IPU corresponds to little-endian words with the first 160 * component in the least significant bits. 161 * The DRM pixel formats and IPU internal representation are ordered the other 162 * way around, with the first named component ordered at the most significant 163 * bits. Further, V4L2 formats are not well defined: 164 * https://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html 165 * We choose the interpretation which matches GStreamer behavior. 166 */ 167 static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat) 168 { 169 switch (pixelformat) { 170 case V4L2_PIX_FMT_RGB565: 171 /* 172 * Here we choose the 'corrected' interpretation of RGBP, a 173 * little-endian 16-bit word with the red component at the most 174 * significant bits: 175 * g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B 176 */ 177 return DRM_FORMAT_RGB565; 178 case V4L2_PIX_FMT_BGR24: 179 /* B G R <=> [24:0] R:G:B */ 180 return DRM_FORMAT_RGB888; 181 case V4L2_PIX_FMT_RGB24: 182 /* R G B <=> [24:0] B:G:R */ 183 return DRM_FORMAT_BGR888; 184 case V4L2_PIX_FMT_BGR32: 185 /* B G R A <=> [32:0] A:B:G:R */ 186 return DRM_FORMAT_XRGB8888; 187 case V4L2_PIX_FMT_RGB32: 188 /* R G B A <=> [32:0] A:B:G:R */ 189 return DRM_FORMAT_XBGR8888; 190 case V4L2_PIX_FMT_UYVY: 191 return DRM_FORMAT_UYVY; 192 case V4L2_PIX_FMT_YUYV: 193 return DRM_FORMAT_YUYV; 194 case V4L2_PIX_FMT_YUV420: 195 return DRM_FORMAT_YUV420; 196 case V4L2_PIX_FMT_YUV422P: 197 return DRM_FORMAT_YUV422; 198 case V4L2_PIX_FMT_YVU420: 199 return DRM_FORMAT_YVU420; 200 case V4L2_PIX_FMT_NV12: 201 return DRM_FORMAT_NV12; 202 case V4L2_PIX_FMT_NV16: 203 return DRM_FORMAT_NV16; 204 } 205 206 return -EINVAL; 207 } 208 209 void ipu_cpmem_zero(struct ipuv3_channel *ch) 210 { 211 struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch); 212 void __iomem *base = p; 213 int i; 214 215 for (i = 0; i < sizeof(*p) / sizeof(u32); i++) 216 writel(0, base + i * sizeof(u32)); 217 } 218 EXPORT_SYMBOL_GPL(ipu_cpmem_zero); 219 220 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres) 221 { 222 ipu_ch_param_write_field(ch, IPU_FIELD_FW, xres - 1); 223 ipu_ch_param_write_field(ch, IPU_FIELD_FH, yres - 1); 224 } 225 EXPORT_SYMBOL_GPL(ipu_cpmem_set_resolution); 226 227 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride) 228 { 229 ipu_ch_param_write_field(ch, IPU_FIELD_SLY, stride - 1); 230 } 231 EXPORT_SYMBOL_GPL(ipu_cpmem_set_stride); 232 233 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch) 234 { 235 struct ipu_soc *ipu = ch->ipu; 236 u32 val; 237 238 if (ipu->ipu_type == IPUV3EX) 239 ipu_ch_param_write_field(ch, IPU_FIELD_ID, 1); 240 241 val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num)); 242 val |= 1 << (ch->num % 32); 243 ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num)); 244 }; 245 EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority); 246 247 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf) 248 { 249 if (bufnum) 250 ipu_ch_param_write_field(ch, IPU_FIELD_EBA1, buf >> 3); 251 else 252 ipu_ch_param_write_field(ch, IPU_FIELD_EBA0, buf >> 3); 253 } 254 EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer); 255 256 void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off) 257 { 258 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_off / 8); 259 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_off / 8); 260 } 261 EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset); 262 263 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride) 264 { 265 ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1); 266 ipu_ch_param_write_field(ch, IPU_FIELD_ILO, stride / 8); 267 ipu_ch_param_write_field(ch, IPU_FIELD_SLY, (stride * 2) - 1); 268 }; 269 EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan); 270 271 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id) 272 { 273 id &= 0x3; 274 ipu_ch_param_write_field(ch, IPU_FIELD_ID, id); 275 } 276 EXPORT_SYMBOL_GPL(ipu_cpmem_set_axi_id); 277 278 int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch) 279 { 280 return ipu_ch_param_read_field(ch, IPU_FIELD_NPB) + 1; 281 } 282 EXPORT_SYMBOL_GPL(ipu_cpmem_get_burstsize); 283 284 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize) 285 { 286 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1); 287 }; 288 EXPORT_SYMBOL_GPL(ipu_cpmem_set_burstsize); 289 290 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch) 291 { 292 ipu_ch_param_write_field(ch, IPU_FIELD_BM, 1); 293 } 294 EXPORT_SYMBOL_GPL(ipu_cpmem_set_block_mode); 295 296 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch, 297 enum ipu_rotate_mode rot) 298 { 299 u32 temp_rot = bitrev8(rot) >> 5; 300 301 ipu_ch_param_write_field(ch, IPU_FIELD_ROT_HF_VF, temp_rot); 302 } 303 EXPORT_SYMBOL_GPL(ipu_cpmem_set_rotation); 304 305 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch, 306 const struct ipu_rgb *rgb) 307 { 308 int bpp = 0, npb = 0, ro, go, bo, to; 309 310 ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset; 311 go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset; 312 bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset; 313 to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset; 314 315 ipu_ch_param_write_field(ch, IPU_FIELD_WID0, rgb->red.length - 1); 316 ipu_ch_param_write_field(ch, IPU_FIELD_OFS0, ro); 317 ipu_ch_param_write_field(ch, IPU_FIELD_WID1, rgb->green.length - 1); 318 ipu_ch_param_write_field(ch, IPU_FIELD_OFS1, go); 319 ipu_ch_param_write_field(ch, IPU_FIELD_WID2, rgb->blue.length - 1); 320 ipu_ch_param_write_field(ch, IPU_FIELD_OFS2, bo); 321 322 if (rgb->transp.length) { 323 ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 324 rgb->transp.length - 1); 325 ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, to); 326 } else { 327 ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7); 328 ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, 329 rgb->bits_per_pixel); 330 } 331 332 switch (rgb->bits_per_pixel) { 333 case 32: 334 bpp = 0; 335 npb = 15; 336 break; 337 case 24: 338 bpp = 1; 339 npb = 19; 340 break; 341 case 16: 342 bpp = 3; 343 npb = 31; 344 break; 345 case 8: 346 bpp = 5; 347 npb = 63; 348 break; 349 default: 350 return -EINVAL; 351 } 352 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp); 353 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb); 354 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 7); /* rgb mode */ 355 356 return 0; 357 } 358 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb); 359 360 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width) 361 { 362 int bpp = 0, npb = 0; 363 364 switch (width) { 365 case 32: 366 bpp = 0; 367 npb = 15; 368 break; 369 case 24: 370 bpp = 1; 371 npb = 19; 372 break; 373 case 16: 374 bpp = 3; 375 npb = 31; 376 break; 377 case 8: 378 bpp = 5; 379 npb = 63; 380 break; 381 default: 382 return -EINVAL; 383 } 384 385 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp); 386 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb); 387 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 6); /* raw mode */ 388 389 return 0; 390 } 391 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough); 392 393 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format) 394 { 395 switch (pixel_format) { 396 case V4L2_PIX_FMT_UYVY: 397 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */ 398 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);/* pix fmt */ 399 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */ 400 break; 401 case V4L2_PIX_FMT_YUYV: 402 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */ 403 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);/* pix fmt */ 404 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */ 405 break; 406 } 407 } 408 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved); 409 410 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, 411 unsigned int uv_stride, 412 unsigned int u_offset, unsigned int v_offset) 413 { 414 ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, uv_stride - 1); 415 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8); 416 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8); 417 } 418 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full); 419 420 static const struct ipu_rgb def_xrgb_32 = { 421 .red = { .offset = 16, .length = 8, }, 422 .green = { .offset = 8, .length = 8, }, 423 .blue = { .offset = 0, .length = 8, }, 424 .transp = { .offset = 24, .length = 8, }, 425 .bits_per_pixel = 32, 426 }; 427 428 static const struct ipu_rgb def_xbgr_32 = { 429 .red = { .offset = 0, .length = 8, }, 430 .green = { .offset = 8, .length = 8, }, 431 .blue = { .offset = 16, .length = 8, }, 432 .transp = { .offset = 24, .length = 8, }, 433 .bits_per_pixel = 32, 434 }; 435 436 static const struct ipu_rgb def_rgbx_32 = { 437 .red = { .offset = 24, .length = 8, }, 438 .green = { .offset = 16, .length = 8, }, 439 .blue = { .offset = 8, .length = 8, }, 440 .transp = { .offset = 0, .length = 8, }, 441 .bits_per_pixel = 32, 442 }; 443 444 static const struct ipu_rgb def_bgrx_32 = { 445 .red = { .offset = 8, .length = 8, }, 446 .green = { .offset = 16, .length = 8, }, 447 .blue = { .offset = 24, .length = 8, }, 448 .transp = { .offset = 0, .length = 8, }, 449 .bits_per_pixel = 32, 450 }; 451 452 static const struct ipu_rgb def_rgb_24 = { 453 .red = { .offset = 16, .length = 8, }, 454 .green = { .offset = 8, .length = 8, }, 455 .blue = { .offset = 0, .length = 8, }, 456 .transp = { .offset = 0, .length = 0, }, 457 .bits_per_pixel = 24, 458 }; 459 460 static const struct ipu_rgb def_bgr_24 = { 461 .red = { .offset = 0, .length = 8, }, 462 .green = { .offset = 8, .length = 8, }, 463 .blue = { .offset = 16, .length = 8, }, 464 .transp = { .offset = 0, .length = 0, }, 465 .bits_per_pixel = 24, 466 }; 467 468 static const struct ipu_rgb def_rgb_16 = { 469 .red = { .offset = 11, .length = 5, }, 470 .green = { .offset = 5, .length = 6, }, 471 .blue = { .offset = 0, .length = 5, }, 472 .transp = { .offset = 0, .length = 0, }, 473 .bits_per_pixel = 16, 474 }; 475 476 static const struct ipu_rgb def_bgr_16 = { 477 .red = { .offset = 0, .length = 5, }, 478 .green = { .offset = 5, .length = 6, }, 479 .blue = { .offset = 11, .length = 5, }, 480 .transp = { .offset = 0, .length = 0, }, 481 .bits_per_pixel = 16, 482 }; 483 484 static const struct ipu_rgb def_argb_16 = { 485 .red = { .offset = 10, .length = 5, }, 486 .green = { .offset = 5, .length = 5, }, 487 .blue = { .offset = 0, .length = 5, }, 488 .transp = { .offset = 15, .length = 1, }, 489 .bits_per_pixel = 16, 490 }; 491 492 static const struct ipu_rgb def_argb_16_4444 = { 493 .red = { .offset = 8, .length = 4, }, 494 .green = { .offset = 4, .length = 4, }, 495 .blue = { .offset = 0, .length = 4, }, 496 .transp = { .offset = 12, .length = 4, }, 497 .bits_per_pixel = 16, 498 }; 499 500 static const struct ipu_rgb def_abgr_16 = { 501 .red = { .offset = 0, .length = 5, }, 502 .green = { .offset = 5, .length = 5, }, 503 .blue = { .offset = 10, .length = 5, }, 504 .transp = { .offset = 15, .length = 1, }, 505 .bits_per_pixel = 16, 506 }; 507 508 static const struct ipu_rgb def_rgba_16 = { 509 .red = { .offset = 11, .length = 5, }, 510 .green = { .offset = 6, .length = 5, }, 511 .blue = { .offset = 1, .length = 5, }, 512 .transp = { .offset = 0, .length = 1, }, 513 .bits_per_pixel = 16, 514 }; 515 516 static const struct ipu_rgb def_bgra_16 = { 517 .red = { .offset = 1, .length = 5, }, 518 .green = { .offset = 6, .length = 5, }, 519 .blue = { .offset = 11, .length = 5, }, 520 .transp = { .offset = 0, .length = 1, }, 521 .bits_per_pixel = 16, 522 }; 523 524 #define Y_OFFSET(pix, x, y) ((x) + pix->width * (y)) 525 #define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 526 (pix->width * (y) / 4) + (x) / 2) 527 #define V_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 528 (pix->width * pix->height / 4) + \ 529 (pix->width * (y) / 4) + (x) / 2) 530 #define U2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 531 (pix->width * (y) / 2) + (x) / 2) 532 #define V2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 533 (pix->width * pix->height / 2) + \ 534 (pix->width * (y) / 2) + (x) / 2) 535 #define UV_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 536 (pix->width * (y) / 2) + (x)) 537 #define UV2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 538 (pix->width * y) + (x)) 539 540 #define NUM_ALPHA_CHANNELS 7 541 542 /* See Table 37-12. Alpha channels mapping. */ 543 static int ipu_channel_albm(int ch_num) 544 { 545 switch (ch_num) { 546 case IPUV3_CHANNEL_G_MEM_IC_PRP_VF: return 0; 547 case IPUV3_CHANNEL_G_MEM_IC_PP: return 1; 548 case IPUV3_CHANNEL_MEM_FG_SYNC: return 2; 549 case IPUV3_CHANNEL_MEM_FG_ASYNC: return 3; 550 case IPUV3_CHANNEL_MEM_BG_SYNC: return 4; 551 case IPUV3_CHANNEL_MEM_BG_ASYNC: return 5; 552 case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB: return 6; 553 default: 554 return -EINVAL; 555 } 556 } 557 558 static void ipu_cpmem_set_separate_alpha(struct ipuv3_channel *ch) 559 { 560 struct ipu_soc *ipu = ch->ipu; 561 int albm; 562 u32 val; 563 564 albm = ipu_channel_albm(ch->num); 565 if (albm < 0) 566 return; 567 568 ipu_ch_param_write_field(ch, IPU_FIELD_ALU, 1); 569 ipu_ch_param_write_field(ch, IPU_FIELD_ALBM, albm); 570 ipu_ch_param_write_field(ch, IPU_FIELD_CRE, 1); 571 572 val = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA); 573 val |= BIT(ch->num); 574 ipu_idmac_write(ipu, val, IDMAC_SEP_ALPHA); 575 } 576 577 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc) 578 { 579 switch (drm_fourcc) { 580 case DRM_FORMAT_YUV420: 581 case DRM_FORMAT_YVU420: 582 /* pix format */ 583 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 2); 584 /* burst size */ 585 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 586 break; 587 case DRM_FORMAT_YUV422: 588 case DRM_FORMAT_YVU422: 589 /* pix format */ 590 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 1); 591 /* burst size */ 592 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 593 break; 594 case DRM_FORMAT_YUV444: 595 case DRM_FORMAT_YVU444: 596 /* pix format */ 597 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0); 598 /* burst size */ 599 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 600 break; 601 case DRM_FORMAT_NV12: 602 /* pix format */ 603 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 4); 604 /* burst size */ 605 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 606 break; 607 case DRM_FORMAT_NV16: 608 /* pix format */ 609 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 3); 610 /* burst size */ 611 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 612 break; 613 case DRM_FORMAT_UYVY: 614 /* bits/pixel */ 615 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); 616 /* pix format */ 617 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA); 618 /* burst size */ 619 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 620 break; 621 case DRM_FORMAT_YUYV: 622 /* bits/pixel */ 623 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); 624 /* pix format */ 625 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8); 626 /* burst size */ 627 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 628 break; 629 case DRM_FORMAT_ABGR8888: 630 case DRM_FORMAT_XBGR8888: 631 ipu_cpmem_set_format_rgb(ch, &def_xbgr_32); 632 break; 633 case DRM_FORMAT_ARGB8888: 634 case DRM_FORMAT_XRGB8888: 635 ipu_cpmem_set_format_rgb(ch, &def_xrgb_32); 636 break; 637 case DRM_FORMAT_RGBA8888: 638 case DRM_FORMAT_RGBX8888: 639 case DRM_FORMAT_RGBX8888_A8: 640 ipu_cpmem_set_format_rgb(ch, &def_rgbx_32); 641 break; 642 case DRM_FORMAT_BGRA8888: 643 case DRM_FORMAT_BGRX8888: 644 case DRM_FORMAT_BGRX8888_A8: 645 ipu_cpmem_set_format_rgb(ch, &def_bgrx_32); 646 break; 647 case DRM_FORMAT_BGR888: 648 case DRM_FORMAT_BGR888_A8: 649 ipu_cpmem_set_format_rgb(ch, &def_bgr_24); 650 break; 651 case DRM_FORMAT_RGB888: 652 case DRM_FORMAT_RGB888_A8: 653 ipu_cpmem_set_format_rgb(ch, &def_rgb_24); 654 break; 655 case DRM_FORMAT_RGB565: 656 case DRM_FORMAT_RGB565_A8: 657 ipu_cpmem_set_format_rgb(ch, &def_rgb_16); 658 break; 659 case DRM_FORMAT_BGR565: 660 case DRM_FORMAT_BGR565_A8: 661 ipu_cpmem_set_format_rgb(ch, &def_bgr_16); 662 break; 663 case DRM_FORMAT_ARGB1555: 664 ipu_cpmem_set_format_rgb(ch, &def_argb_16); 665 break; 666 case DRM_FORMAT_ABGR1555: 667 ipu_cpmem_set_format_rgb(ch, &def_abgr_16); 668 break; 669 case DRM_FORMAT_RGBA5551: 670 ipu_cpmem_set_format_rgb(ch, &def_rgba_16); 671 break; 672 case DRM_FORMAT_BGRA5551: 673 ipu_cpmem_set_format_rgb(ch, &def_bgra_16); 674 break; 675 case DRM_FORMAT_ARGB4444: 676 ipu_cpmem_set_format_rgb(ch, &def_argb_16_4444); 677 break; 678 default: 679 return -EINVAL; 680 } 681 682 switch (drm_fourcc) { 683 case DRM_FORMAT_RGB565_A8: 684 case DRM_FORMAT_BGR565_A8: 685 case DRM_FORMAT_RGB888_A8: 686 case DRM_FORMAT_BGR888_A8: 687 case DRM_FORMAT_RGBX8888_A8: 688 case DRM_FORMAT_BGRX8888_A8: 689 ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7); 690 ipu_cpmem_set_separate_alpha(ch); 691 break; 692 default: 693 break; 694 } 695 696 return 0; 697 } 698 EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt); 699 700 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image) 701 { 702 struct v4l2_pix_format *pix = &image->pix; 703 int offset, u_offset, v_offset; 704 int ret = 0; 705 706 pr_debug("%s: resolution: %dx%d stride: %d\n", 707 __func__, pix->width, pix->height, 708 pix->bytesperline); 709 710 ipu_cpmem_set_resolution(ch, image->rect.width, image->rect.height); 711 ipu_cpmem_set_stride(ch, pix->bytesperline); 712 713 ipu_cpmem_set_fmt(ch, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat)); 714 715 switch (pix->pixelformat) { 716 case V4L2_PIX_FMT_YUV420: 717 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 718 u_offset = U_OFFSET(pix, image->rect.left, 719 image->rect.top) - offset; 720 v_offset = V_OFFSET(pix, image->rect.left, 721 image->rect.top) - offset; 722 723 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2, 724 u_offset, v_offset); 725 break; 726 case V4L2_PIX_FMT_YVU420: 727 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 728 u_offset = U_OFFSET(pix, image->rect.left, 729 image->rect.top) - offset; 730 v_offset = V_OFFSET(pix, image->rect.left, 731 image->rect.top) - offset; 732 733 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2, 734 v_offset, u_offset); 735 break; 736 case V4L2_PIX_FMT_YUV422P: 737 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 738 u_offset = U2_OFFSET(pix, image->rect.left, 739 image->rect.top) - offset; 740 v_offset = V2_OFFSET(pix, image->rect.left, 741 image->rect.top) - offset; 742 743 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2, 744 u_offset, v_offset); 745 break; 746 case V4L2_PIX_FMT_NV12: 747 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 748 u_offset = UV_OFFSET(pix, image->rect.left, 749 image->rect.top) - offset; 750 v_offset = 0; 751 752 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline, 753 u_offset, v_offset); 754 break; 755 case V4L2_PIX_FMT_NV16: 756 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 757 u_offset = UV2_OFFSET(pix, image->rect.left, 758 image->rect.top) - offset; 759 v_offset = 0; 760 761 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline, 762 u_offset, v_offset); 763 break; 764 case V4L2_PIX_FMT_UYVY: 765 case V4L2_PIX_FMT_YUYV: 766 case V4L2_PIX_FMT_RGB565: 767 offset = image->rect.left * 2 + 768 image->rect.top * pix->bytesperline; 769 break; 770 case V4L2_PIX_FMT_RGB32: 771 case V4L2_PIX_FMT_BGR32: 772 offset = image->rect.left * 4 + 773 image->rect.top * pix->bytesperline; 774 break; 775 case V4L2_PIX_FMT_RGB24: 776 case V4L2_PIX_FMT_BGR24: 777 offset = image->rect.left * 3 + 778 image->rect.top * pix->bytesperline; 779 break; 780 case V4L2_PIX_FMT_SBGGR8: 781 case V4L2_PIX_FMT_SGBRG8: 782 case V4L2_PIX_FMT_SGRBG8: 783 case V4L2_PIX_FMT_SRGGB8: 784 offset = image->rect.left + image->rect.top * pix->bytesperline; 785 break; 786 case V4L2_PIX_FMT_SBGGR16: 787 case V4L2_PIX_FMT_SGBRG16: 788 case V4L2_PIX_FMT_SGRBG16: 789 case V4L2_PIX_FMT_SRGGB16: 790 offset = image->rect.left * 2 + 791 image->rect.top * pix->bytesperline; 792 break; 793 default: 794 /* This should not happen */ 795 WARN_ON(1); 796 offset = 0; 797 ret = -EINVAL; 798 } 799 800 ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset); 801 ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset); 802 803 return ret; 804 } 805 EXPORT_SYMBOL_GPL(ipu_cpmem_set_image); 806 807 void ipu_cpmem_dump(struct ipuv3_channel *ch) 808 { 809 struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch); 810 struct ipu_soc *ipu = ch->ipu; 811 int chno = ch->num; 812 813 dev_dbg(ipu->dev, "ch %d word 0 - %08X %08X %08X %08X %08X\n", chno, 814 readl(&p->word[0].data[0]), 815 readl(&p->word[0].data[1]), 816 readl(&p->word[0].data[2]), 817 readl(&p->word[0].data[3]), 818 readl(&p->word[0].data[4])); 819 dev_dbg(ipu->dev, "ch %d word 1 - %08X %08X %08X %08X %08X\n", chno, 820 readl(&p->word[1].data[0]), 821 readl(&p->word[1].data[1]), 822 readl(&p->word[1].data[2]), 823 readl(&p->word[1].data[3]), 824 readl(&p->word[1].data[4])); 825 dev_dbg(ipu->dev, "PFS 0x%x, ", 826 ipu_ch_param_read_field(ch, IPU_FIELD_PFS)); 827 dev_dbg(ipu->dev, "BPP 0x%x, ", 828 ipu_ch_param_read_field(ch, IPU_FIELD_BPP)); 829 dev_dbg(ipu->dev, "NPB 0x%x\n", 830 ipu_ch_param_read_field(ch, IPU_FIELD_NPB)); 831 832 dev_dbg(ipu->dev, "FW %d, ", 833 ipu_ch_param_read_field(ch, IPU_FIELD_FW)); 834 dev_dbg(ipu->dev, "FH %d, ", 835 ipu_ch_param_read_field(ch, IPU_FIELD_FH)); 836 dev_dbg(ipu->dev, "EBA0 0x%x\n", 837 ipu_ch_param_read_field(ch, IPU_FIELD_EBA0) << 3); 838 dev_dbg(ipu->dev, "EBA1 0x%x\n", 839 ipu_ch_param_read_field(ch, IPU_FIELD_EBA1) << 3); 840 dev_dbg(ipu->dev, "Stride %d\n", 841 ipu_ch_param_read_field(ch, IPU_FIELD_SL)); 842 dev_dbg(ipu->dev, "scan_order %d\n", 843 ipu_ch_param_read_field(ch, IPU_FIELD_SO)); 844 dev_dbg(ipu->dev, "uv_stride %d\n", 845 ipu_ch_param_read_field(ch, IPU_FIELD_SLUV)); 846 dev_dbg(ipu->dev, "u_offset 0x%x\n", 847 ipu_ch_param_read_field(ch, IPU_FIELD_UBO) << 3); 848 dev_dbg(ipu->dev, "v_offset 0x%x\n", 849 ipu_ch_param_read_field(ch, IPU_FIELD_VBO) << 3); 850 851 dev_dbg(ipu->dev, "Width0 %d+1, ", 852 ipu_ch_param_read_field(ch, IPU_FIELD_WID0)); 853 dev_dbg(ipu->dev, "Width1 %d+1, ", 854 ipu_ch_param_read_field(ch, IPU_FIELD_WID1)); 855 dev_dbg(ipu->dev, "Width2 %d+1, ", 856 ipu_ch_param_read_field(ch, IPU_FIELD_WID2)); 857 dev_dbg(ipu->dev, "Width3 %d+1, ", 858 ipu_ch_param_read_field(ch, IPU_FIELD_WID3)); 859 dev_dbg(ipu->dev, "Offset0 %d, ", 860 ipu_ch_param_read_field(ch, IPU_FIELD_OFS0)); 861 dev_dbg(ipu->dev, "Offset1 %d, ", 862 ipu_ch_param_read_field(ch, IPU_FIELD_OFS1)); 863 dev_dbg(ipu->dev, "Offset2 %d, ", 864 ipu_ch_param_read_field(ch, IPU_FIELD_OFS2)); 865 dev_dbg(ipu->dev, "Offset3 %d\n", 866 ipu_ch_param_read_field(ch, IPU_FIELD_OFS3)); 867 } 868 EXPORT_SYMBOL_GPL(ipu_cpmem_dump); 869 870 int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base) 871 { 872 struct ipu_cpmem *cpmem; 873 874 cpmem = devm_kzalloc(dev, sizeof(*cpmem), GFP_KERNEL); 875 if (!cpmem) 876 return -ENOMEM; 877 878 ipu->cpmem_priv = cpmem; 879 880 spin_lock_init(&cpmem->lock); 881 cpmem->base = devm_ioremap(dev, base, SZ_128K); 882 if (!cpmem->base) 883 return -ENOMEM; 884 885 dev_dbg(dev, "CPMEM base: 0x%08lx remapped to %p\n", 886 base, cpmem->base); 887 cpmem->ipu = ipu; 888 889 return 0; 890 } 891 892 void ipu_cpmem_exit(struct ipu_soc *ipu) 893 { 894 } 895