1 /* 2 * Copyright (C) 2012 Mentor Graphics Inc. 3 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 #include <linux/types.h> 13 #include <linux/bitrev.h> 14 #include <linux/io.h> 15 #include <linux/sizes.h> 16 #include <drm/drm_fourcc.h> 17 #include "ipu-prv.h" 18 19 struct ipu_cpmem_word { 20 u32 data[5]; 21 u32 res[3]; 22 }; 23 24 struct ipu_ch_param { 25 struct ipu_cpmem_word word[2]; 26 }; 27 28 struct ipu_cpmem { 29 struct ipu_ch_param __iomem *base; 30 u32 module; 31 spinlock_t lock; 32 int use_count; 33 struct ipu_soc *ipu; 34 }; 35 36 #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size)) 37 38 #define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22) 39 #define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22) 40 #define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4) 41 #define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1) 42 #define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1) 43 #define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14) 44 #define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14) 45 46 #define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10) 47 #define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9) 48 #define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13) 49 #define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12) 50 #define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1) 51 #define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1) 52 #define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12) 53 #define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11) 54 #define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10) 55 #define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7) 56 #define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10) 57 #define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1) 58 #define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1) 59 #define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7) 60 #define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1) 61 #define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1) 62 #define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3) 63 #define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2) 64 #define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1) 65 #define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3) 66 #define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2) 67 #define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1) 68 #define IPU_FIELD_ROT_HF_VF IPU_CPMEM_WORD(0, 119, 3) 69 #define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1) 70 #define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1) 71 #define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1) 72 #define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1) 73 #define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1) 74 #define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13) 75 #define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12) 76 #define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29) 77 #define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29) 78 #define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20) 79 #define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7) 80 #define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4) 81 #define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1) 82 #define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3) 83 #define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2) 84 #define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7) 85 #define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14) 86 #define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3) 87 #define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3) 88 #define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3) 89 #define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3) 90 #define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5) 91 #define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5) 92 #define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5) 93 #define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5) 94 #define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1) 95 #define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1) 96 #define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1) 97 98 static inline struct ipu_ch_param __iomem * 99 ipu_get_cpmem(struct ipuv3_channel *ch) 100 { 101 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; 102 103 return cpmem->base + ch->num; 104 } 105 106 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) 107 { 108 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); 109 u32 bit = (wbs >> 8) % 160; 110 u32 size = wbs & 0xff; 111 u32 word = (wbs >> 8) / 160; 112 u32 i = bit / 32; 113 u32 ofs = bit % 32; 114 u32 mask = (1 << size) - 1; 115 u32 val; 116 117 pr_debug("%s %d %d %d\n", __func__, word, bit , size); 118 119 val = readl(&base->word[word].data[i]); 120 val &= ~(mask << ofs); 121 val |= v << ofs; 122 writel(val, &base->word[word].data[i]); 123 124 if ((bit + size - 1) / 32 > i) { 125 val = readl(&base->word[word].data[i + 1]); 126 val &= ~(mask >> (ofs ? (32 - ofs) : 0)); 127 val |= v >> (ofs ? (32 - ofs) : 0); 128 writel(val, &base->word[word].data[i + 1]); 129 } 130 } 131 132 static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs) 133 { 134 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); 135 u32 bit = (wbs >> 8) % 160; 136 u32 size = wbs & 0xff; 137 u32 word = (wbs >> 8) / 160; 138 u32 i = bit / 32; 139 u32 ofs = bit % 32; 140 u32 mask = (1 << size) - 1; 141 u32 val = 0; 142 143 pr_debug("%s %d %d %d\n", __func__, word, bit , size); 144 145 val = (readl(&base->word[word].data[i]) >> ofs) & mask; 146 147 if ((bit + size - 1) / 32 > i) { 148 u32 tmp; 149 150 tmp = readl(&base->word[word].data[i + 1]); 151 tmp &= mask >> (ofs ? (32 - ofs) : 0); 152 val |= tmp << (ofs ? (32 - ofs) : 0); 153 } 154 155 return val; 156 } 157 158 /* 159 * The V4L2 spec defines packed RGB formats in memory byte order, which from 160 * point of view of the IPU corresponds to little-endian words with the first 161 * component in the least significant bits. 162 * The DRM pixel formats and IPU internal representation are ordered the other 163 * way around, with the first named component ordered at the most significant 164 * bits. Further, V4L2 formats are not well defined: 165 * https://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html 166 * We choose the interpretation which matches GStreamer behavior. 167 */ 168 static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat) 169 { 170 switch (pixelformat) { 171 case V4L2_PIX_FMT_RGB565: 172 /* 173 * Here we choose the 'corrected' interpretation of RGBP, a 174 * little-endian 16-bit word with the red component at the most 175 * significant bits: 176 * g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B 177 */ 178 return DRM_FORMAT_RGB565; 179 case V4L2_PIX_FMT_BGR24: 180 /* B G R <=> [24:0] R:G:B */ 181 return DRM_FORMAT_RGB888; 182 case V4L2_PIX_FMT_RGB24: 183 /* R G B <=> [24:0] B:G:R */ 184 return DRM_FORMAT_BGR888; 185 case V4L2_PIX_FMT_BGR32: 186 /* B G R A <=> [32:0] A:B:G:R */ 187 return DRM_FORMAT_XRGB8888; 188 case V4L2_PIX_FMT_RGB32: 189 /* R G B A <=> [32:0] A:B:G:R */ 190 return DRM_FORMAT_XBGR8888; 191 case V4L2_PIX_FMT_XBGR32: 192 /* B G R X <=> [32:0] X:R:G:B */ 193 return DRM_FORMAT_XRGB8888; 194 case V4L2_PIX_FMT_XRGB32: 195 /* X R G B <=> [32:0] B:G:R:X */ 196 return DRM_FORMAT_BGRX8888; 197 case V4L2_PIX_FMT_UYVY: 198 return DRM_FORMAT_UYVY; 199 case V4L2_PIX_FMT_YUYV: 200 return DRM_FORMAT_YUYV; 201 case V4L2_PIX_FMT_YUV420: 202 return DRM_FORMAT_YUV420; 203 case V4L2_PIX_FMT_YUV422P: 204 return DRM_FORMAT_YUV422; 205 case V4L2_PIX_FMT_YVU420: 206 return DRM_FORMAT_YVU420; 207 case V4L2_PIX_FMT_NV12: 208 return DRM_FORMAT_NV12; 209 case V4L2_PIX_FMT_NV16: 210 return DRM_FORMAT_NV16; 211 } 212 213 return -EINVAL; 214 } 215 216 void ipu_cpmem_zero(struct ipuv3_channel *ch) 217 { 218 struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch); 219 void __iomem *base = p; 220 int i; 221 222 for (i = 0; i < sizeof(*p) / sizeof(u32); i++) 223 writel(0, base + i * sizeof(u32)); 224 } 225 EXPORT_SYMBOL_GPL(ipu_cpmem_zero); 226 227 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres) 228 { 229 ipu_ch_param_write_field(ch, IPU_FIELD_FW, xres - 1); 230 ipu_ch_param_write_field(ch, IPU_FIELD_FH, yres - 1); 231 } 232 EXPORT_SYMBOL_GPL(ipu_cpmem_set_resolution); 233 234 void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch) 235 { 236 ipu_ch_param_write_field(ch, IPU_FIELD_RDRW, 1); 237 } 238 EXPORT_SYMBOL_GPL(ipu_cpmem_skip_odd_chroma_rows); 239 240 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride) 241 { 242 ipu_ch_param_write_field(ch, IPU_FIELD_SLY, stride - 1); 243 } 244 EXPORT_SYMBOL_GPL(ipu_cpmem_set_stride); 245 246 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch) 247 { 248 struct ipu_soc *ipu = ch->ipu; 249 u32 val; 250 251 if (ipu->ipu_type == IPUV3EX) 252 ipu_ch_param_write_field(ch, IPU_FIELD_ID, 1); 253 254 val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num)); 255 val |= 1 << (ch->num % 32); 256 ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num)); 257 }; 258 EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority); 259 260 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf) 261 { 262 WARN_ON_ONCE(buf & 0x7); 263 264 if (bufnum) 265 ipu_ch_param_write_field(ch, IPU_FIELD_EBA1, buf >> 3); 266 else 267 ipu_ch_param_write_field(ch, IPU_FIELD_EBA0, buf >> 3); 268 } 269 EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer); 270 271 void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off) 272 { 273 WARN_ON_ONCE((u_off & 0x7) || (v_off & 0x7)); 274 275 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_off / 8); 276 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_off / 8); 277 } 278 EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset); 279 280 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride, 281 u32 pixelformat) 282 { 283 u32 ilo, sly, sluv; 284 285 if (stride < 0) { 286 stride = -stride; 287 ilo = 0x100000 - (stride / 8); 288 } else { 289 ilo = stride / 8; 290 } 291 292 sly = (stride * 2) - 1; 293 294 switch (pixelformat) { 295 case V4L2_PIX_FMT_YUV420: 296 case V4L2_PIX_FMT_YVU420: 297 sluv = stride / 2 - 1; 298 break; 299 case V4L2_PIX_FMT_NV12: 300 sluv = stride - 1; 301 break; 302 case V4L2_PIX_FMT_YUV422P: 303 sluv = stride - 1; 304 break; 305 case V4L2_PIX_FMT_NV16: 306 sluv = stride * 2 - 1; 307 break; 308 default: 309 sluv = 0; 310 break; 311 } 312 313 ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1); 314 ipu_ch_param_write_field(ch, IPU_FIELD_ILO, ilo); 315 ipu_ch_param_write_field(ch, IPU_FIELD_SLY, sly); 316 if (sluv) 317 ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, sluv); 318 }; 319 EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan); 320 321 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id) 322 { 323 id &= 0x3; 324 ipu_ch_param_write_field(ch, IPU_FIELD_ID, id); 325 } 326 EXPORT_SYMBOL_GPL(ipu_cpmem_set_axi_id); 327 328 int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch) 329 { 330 return ipu_ch_param_read_field(ch, IPU_FIELD_NPB) + 1; 331 } 332 EXPORT_SYMBOL_GPL(ipu_cpmem_get_burstsize); 333 334 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize) 335 { 336 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1); 337 }; 338 EXPORT_SYMBOL_GPL(ipu_cpmem_set_burstsize); 339 340 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch) 341 { 342 ipu_ch_param_write_field(ch, IPU_FIELD_BM, 1); 343 } 344 EXPORT_SYMBOL_GPL(ipu_cpmem_set_block_mode); 345 346 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch, 347 enum ipu_rotate_mode rot) 348 { 349 u32 temp_rot = bitrev8(rot) >> 5; 350 351 ipu_ch_param_write_field(ch, IPU_FIELD_ROT_HF_VF, temp_rot); 352 } 353 EXPORT_SYMBOL_GPL(ipu_cpmem_set_rotation); 354 355 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch, 356 const struct ipu_rgb *rgb) 357 { 358 int bpp = 0, npb = 0, ro, go, bo, to; 359 360 ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset; 361 go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset; 362 bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset; 363 to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset; 364 365 ipu_ch_param_write_field(ch, IPU_FIELD_WID0, rgb->red.length - 1); 366 ipu_ch_param_write_field(ch, IPU_FIELD_OFS0, ro); 367 ipu_ch_param_write_field(ch, IPU_FIELD_WID1, rgb->green.length - 1); 368 ipu_ch_param_write_field(ch, IPU_FIELD_OFS1, go); 369 ipu_ch_param_write_field(ch, IPU_FIELD_WID2, rgb->blue.length - 1); 370 ipu_ch_param_write_field(ch, IPU_FIELD_OFS2, bo); 371 372 if (rgb->transp.length) { 373 ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 374 rgb->transp.length - 1); 375 ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, to); 376 } else { 377 ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7); 378 ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, 379 rgb->bits_per_pixel); 380 } 381 382 switch (rgb->bits_per_pixel) { 383 case 32: 384 bpp = 0; 385 npb = 15; 386 break; 387 case 24: 388 bpp = 1; 389 npb = 19; 390 break; 391 case 16: 392 bpp = 3; 393 npb = 31; 394 break; 395 case 8: 396 bpp = 5; 397 npb = 63; 398 break; 399 default: 400 return -EINVAL; 401 } 402 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp); 403 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb); 404 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 7); /* rgb mode */ 405 406 return 0; 407 } 408 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb); 409 410 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width) 411 { 412 int bpp = 0, npb = 0; 413 414 switch (width) { 415 case 32: 416 bpp = 0; 417 npb = 15; 418 break; 419 case 24: 420 bpp = 1; 421 npb = 19; 422 break; 423 case 16: 424 bpp = 3; 425 npb = 31; 426 break; 427 case 8: 428 bpp = 5; 429 npb = 63; 430 break; 431 default: 432 return -EINVAL; 433 } 434 435 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp); 436 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb); 437 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 6); /* raw mode */ 438 439 return 0; 440 } 441 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough); 442 443 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format) 444 { 445 switch (pixel_format) { 446 case V4L2_PIX_FMT_UYVY: 447 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */ 448 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);/* pix fmt */ 449 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */ 450 break; 451 case V4L2_PIX_FMT_YUYV: 452 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */ 453 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);/* pix fmt */ 454 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */ 455 break; 456 } 457 } 458 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved); 459 460 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, 461 unsigned int uv_stride, 462 unsigned int u_offset, unsigned int v_offset) 463 { 464 WARN_ON_ONCE((u_offset & 0x7) || (v_offset & 0x7)); 465 466 ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, uv_stride - 1); 467 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8); 468 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8); 469 } 470 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full); 471 472 static const struct ipu_rgb def_xrgb_32 = { 473 .red = { .offset = 16, .length = 8, }, 474 .green = { .offset = 8, .length = 8, }, 475 .blue = { .offset = 0, .length = 8, }, 476 .transp = { .offset = 24, .length = 8, }, 477 .bits_per_pixel = 32, 478 }; 479 480 static const struct ipu_rgb def_xbgr_32 = { 481 .red = { .offset = 0, .length = 8, }, 482 .green = { .offset = 8, .length = 8, }, 483 .blue = { .offset = 16, .length = 8, }, 484 .transp = { .offset = 24, .length = 8, }, 485 .bits_per_pixel = 32, 486 }; 487 488 static const struct ipu_rgb def_rgbx_32 = { 489 .red = { .offset = 24, .length = 8, }, 490 .green = { .offset = 16, .length = 8, }, 491 .blue = { .offset = 8, .length = 8, }, 492 .transp = { .offset = 0, .length = 8, }, 493 .bits_per_pixel = 32, 494 }; 495 496 static const struct ipu_rgb def_bgrx_32 = { 497 .red = { .offset = 8, .length = 8, }, 498 .green = { .offset = 16, .length = 8, }, 499 .blue = { .offset = 24, .length = 8, }, 500 .transp = { .offset = 0, .length = 8, }, 501 .bits_per_pixel = 32, 502 }; 503 504 static const struct ipu_rgb def_rgb_24 = { 505 .red = { .offset = 16, .length = 8, }, 506 .green = { .offset = 8, .length = 8, }, 507 .blue = { .offset = 0, .length = 8, }, 508 .transp = { .offset = 0, .length = 0, }, 509 .bits_per_pixel = 24, 510 }; 511 512 static const struct ipu_rgb def_bgr_24 = { 513 .red = { .offset = 0, .length = 8, }, 514 .green = { .offset = 8, .length = 8, }, 515 .blue = { .offset = 16, .length = 8, }, 516 .transp = { .offset = 0, .length = 0, }, 517 .bits_per_pixel = 24, 518 }; 519 520 static const struct ipu_rgb def_rgb_16 = { 521 .red = { .offset = 11, .length = 5, }, 522 .green = { .offset = 5, .length = 6, }, 523 .blue = { .offset = 0, .length = 5, }, 524 .transp = { .offset = 0, .length = 0, }, 525 .bits_per_pixel = 16, 526 }; 527 528 static const struct ipu_rgb def_bgr_16 = { 529 .red = { .offset = 0, .length = 5, }, 530 .green = { .offset = 5, .length = 6, }, 531 .blue = { .offset = 11, .length = 5, }, 532 .transp = { .offset = 0, .length = 0, }, 533 .bits_per_pixel = 16, 534 }; 535 536 static const struct ipu_rgb def_argb_16 = { 537 .red = { .offset = 10, .length = 5, }, 538 .green = { .offset = 5, .length = 5, }, 539 .blue = { .offset = 0, .length = 5, }, 540 .transp = { .offset = 15, .length = 1, }, 541 .bits_per_pixel = 16, 542 }; 543 544 static const struct ipu_rgb def_argb_16_4444 = { 545 .red = { .offset = 8, .length = 4, }, 546 .green = { .offset = 4, .length = 4, }, 547 .blue = { .offset = 0, .length = 4, }, 548 .transp = { .offset = 12, .length = 4, }, 549 .bits_per_pixel = 16, 550 }; 551 552 static const struct ipu_rgb def_abgr_16 = { 553 .red = { .offset = 0, .length = 5, }, 554 .green = { .offset = 5, .length = 5, }, 555 .blue = { .offset = 10, .length = 5, }, 556 .transp = { .offset = 15, .length = 1, }, 557 .bits_per_pixel = 16, 558 }; 559 560 static const struct ipu_rgb def_rgba_16 = { 561 .red = { .offset = 11, .length = 5, }, 562 .green = { .offset = 6, .length = 5, }, 563 .blue = { .offset = 1, .length = 5, }, 564 .transp = { .offset = 0, .length = 1, }, 565 .bits_per_pixel = 16, 566 }; 567 568 static const struct ipu_rgb def_bgra_16 = { 569 .red = { .offset = 1, .length = 5, }, 570 .green = { .offset = 6, .length = 5, }, 571 .blue = { .offset = 11, .length = 5, }, 572 .transp = { .offset = 0, .length = 1, }, 573 .bits_per_pixel = 16, 574 }; 575 576 #define Y_OFFSET(pix, x, y) ((x) + pix->width * (y)) 577 #define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 578 (pix->width * ((y) / 2) / 2) + (x) / 2) 579 #define V_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 580 (pix->width * pix->height / 4) + \ 581 (pix->width * ((y) / 2) / 2) + (x) / 2) 582 #define U2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 583 (pix->width * (y) / 2) + (x) / 2) 584 #define V2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 585 (pix->width * pix->height / 2) + \ 586 (pix->width * (y) / 2) + (x) / 2) 587 #define UV_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 588 (pix->width * ((y) / 2)) + (x)) 589 #define UV2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 590 (pix->width * y) + (x)) 591 592 #define NUM_ALPHA_CHANNELS 7 593 594 /* See Table 37-12. Alpha channels mapping. */ 595 static int ipu_channel_albm(int ch_num) 596 { 597 switch (ch_num) { 598 case IPUV3_CHANNEL_G_MEM_IC_PRP_VF: return 0; 599 case IPUV3_CHANNEL_G_MEM_IC_PP: return 1; 600 case IPUV3_CHANNEL_MEM_FG_SYNC: return 2; 601 case IPUV3_CHANNEL_MEM_FG_ASYNC: return 3; 602 case IPUV3_CHANNEL_MEM_BG_SYNC: return 4; 603 case IPUV3_CHANNEL_MEM_BG_ASYNC: return 5; 604 case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB: return 6; 605 default: 606 return -EINVAL; 607 } 608 } 609 610 static void ipu_cpmem_set_separate_alpha(struct ipuv3_channel *ch) 611 { 612 struct ipu_soc *ipu = ch->ipu; 613 int albm; 614 u32 val; 615 616 albm = ipu_channel_albm(ch->num); 617 if (albm < 0) 618 return; 619 620 ipu_ch_param_write_field(ch, IPU_FIELD_ALU, 1); 621 ipu_ch_param_write_field(ch, IPU_FIELD_ALBM, albm); 622 ipu_ch_param_write_field(ch, IPU_FIELD_CRE, 1); 623 624 val = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA); 625 val |= BIT(ch->num); 626 ipu_idmac_write(ipu, val, IDMAC_SEP_ALPHA); 627 } 628 629 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc) 630 { 631 switch (drm_fourcc) { 632 case DRM_FORMAT_YUV420: 633 case DRM_FORMAT_YVU420: 634 /* pix format */ 635 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 2); 636 /* burst size */ 637 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 638 break; 639 case DRM_FORMAT_YUV422: 640 case DRM_FORMAT_YVU422: 641 /* pix format */ 642 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 1); 643 /* burst size */ 644 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 645 break; 646 case DRM_FORMAT_YUV444: 647 case DRM_FORMAT_YVU444: 648 /* pix format */ 649 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0); 650 /* burst size */ 651 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 652 break; 653 case DRM_FORMAT_NV12: 654 /* pix format */ 655 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 4); 656 /* burst size */ 657 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 658 break; 659 case DRM_FORMAT_NV16: 660 /* pix format */ 661 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 3); 662 /* burst size */ 663 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 664 break; 665 case DRM_FORMAT_UYVY: 666 /* bits/pixel */ 667 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); 668 /* pix format */ 669 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA); 670 /* burst size */ 671 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 672 break; 673 case DRM_FORMAT_YUYV: 674 /* bits/pixel */ 675 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); 676 /* pix format */ 677 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8); 678 /* burst size */ 679 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 680 break; 681 case DRM_FORMAT_ABGR8888: 682 case DRM_FORMAT_XBGR8888: 683 ipu_cpmem_set_format_rgb(ch, &def_xbgr_32); 684 break; 685 case DRM_FORMAT_ARGB8888: 686 case DRM_FORMAT_XRGB8888: 687 ipu_cpmem_set_format_rgb(ch, &def_xrgb_32); 688 break; 689 case DRM_FORMAT_RGBA8888: 690 case DRM_FORMAT_RGBX8888: 691 case DRM_FORMAT_RGBX8888_A8: 692 ipu_cpmem_set_format_rgb(ch, &def_rgbx_32); 693 break; 694 case DRM_FORMAT_BGRA8888: 695 case DRM_FORMAT_BGRX8888: 696 case DRM_FORMAT_BGRX8888_A8: 697 ipu_cpmem_set_format_rgb(ch, &def_bgrx_32); 698 break; 699 case DRM_FORMAT_BGR888: 700 case DRM_FORMAT_BGR888_A8: 701 ipu_cpmem_set_format_rgb(ch, &def_bgr_24); 702 break; 703 case DRM_FORMAT_RGB888: 704 case DRM_FORMAT_RGB888_A8: 705 ipu_cpmem_set_format_rgb(ch, &def_rgb_24); 706 break; 707 case DRM_FORMAT_RGB565: 708 case DRM_FORMAT_RGB565_A8: 709 ipu_cpmem_set_format_rgb(ch, &def_rgb_16); 710 break; 711 case DRM_FORMAT_BGR565: 712 case DRM_FORMAT_BGR565_A8: 713 ipu_cpmem_set_format_rgb(ch, &def_bgr_16); 714 break; 715 case DRM_FORMAT_ARGB1555: 716 ipu_cpmem_set_format_rgb(ch, &def_argb_16); 717 break; 718 case DRM_FORMAT_ABGR1555: 719 ipu_cpmem_set_format_rgb(ch, &def_abgr_16); 720 break; 721 case DRM_FORMAT_RGBA5551: 722 ipu_cpmem_set_format_rgb(ch, &def_rgba_16); 723 break; 724 case DRM_FORMAT_BGRA5551: 725 ipu_cpmem_set_format_rgb(ch, &def_bgra_16); 726 break; 727 case DRM_FORMAT_ARGB4444: 728 ipu_cpmem_set_format_rgb(ch, &def_argb_16_4444); 729 break; 730 default: 731 return -EINVAL; 732 } 733 734 switch (drm_fourcc) { 735 case DRM_FORMAT_RGB565_A8: 736 case DRM_FORMAT_BGR565_A8: 737 case DRM_FORMAT_RGB888_A8: 738 case DRM_FORMAT_BGR888_A8: 739 case DRM_FORMAT_RGBX8888_A8: 740 case DRM_FORMAT_BGRX8888_A8: 741 ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7); 742 ipu_cpmem_set_separate_alpha(ch); 743 break; 744 default: 745 break; 746 } 747 748 return 0; 749 } 750 EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt); 751 752 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image) 753 { 754 struct v4l2_pix_format *pix = &image->pix; 755 int offset, u_offset, v_offset; 756 int ret = 0; 757 758 pr_debug("%s: resolution: %dx%d stride: %d\n", 759 __func__, pix->width, pix->height, 760 pix->bytesperline); 761 762 ipu_cpmem_set_resolution(ch, image->rect.width, image->rect.height); 763 ipu_cpmem_set_stride(ch, pix->bytesperline); 764 765 ipu_cpmem_set_fmt(ch, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat)); 766 767 switch (pix->pixelformat) { 768 case V4L2_PIX_FMT_YUV420: 769 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 770 u_offset = image->u_offset ? 771 image->u_offset : U_OFFSET(pix, image->rect.left, 772 image->rect.top) - offset; 773 v_offset = image->v_offset ? 774 image->v_offset : V_OFFSET(pix, image->rect.left, 775 image->rect.top) - offset; 776 777 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2, 778 u_offset, v_offset); 779 break; 780 case V4L2_PIX_FMT_YVU420: 781 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 782 u_offset = image->u_offset ? 783 image->u_offset : V_OFFSET(pix, image->rect.left, 784 image->rect.top) - offset; 785 v_offset = image->v_offset ? 786 image->v_offset : U_OFFSET(pix, image->rect.left, 787 image->rect.top) - offset; 788 789 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2, 790 u_offset, v_offset); 791 break; 792 case V4L2_PIX_FMT_YUV422P: 793 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 794 u_offset = image->u_offset ? 795 image->u_offset : U2_OFFSET(pix, image->rect.left, 796 image->rect.top) - offset; 797 v_offset = image->v_offset ? 798 image->v_offset : V2_OFFSET(pix, image->rect.left, 799 image->rect.top) - offset; 800 801 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2, 802 u_offset, v_offset); 803 break; 804 case V4L2_PIX_FMT_NV12: 805 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 806 u_offset = image->u_offset ? 807 image->u_offset : UV_OFFSET(pix, image->rect.left, 808 image->rect.top) - offset; 809 v_offset = image->v_offset ? image->v_offset : 0; 810 811 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline, 812 u_offset, v_offset); 813 break; 814 case V4L2_PIX_FMT_NV16: 815 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 816 u_offset = image->u_offset ? 817 image->u_offset : UV2_OFFSET(pix, image->rect.left, 818 image->rect.top) - offset; 819 v_offset = image->v_offset ? image->v_offset : 0; 820 821 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline, 822 u_offset, v_offset); 823 break; 824 case V4L2_PIX_FMT_UYVY: 825 case V4L2_PIX_FMT_YUYV: 826 case V4L2_PIX_FMT_RGB565: 827 offset = image->rect.left * 2 + 828 image->rect.top * pix->bytesperline; 829 break; 830 case V4L2_PIX_FMT_RGB32: 831 case V4L2_PIX_FMT_BGR32: 832 case V4L2_PIX_FMT_XRGB32: 833 case V4L2_PIX_FMT_XBGR32: 834 offset = image->rect.left * 4 + 835 image->rect.top * pix->bytesperline; 836 break; 837 case V4L2_PIX_FMT_RGB24: 838 case V4L2_PIX_FMT_BGR24: 839 offset = image->rect.left * 3 + 840 image->rect.top * pix->bytesperline; 841 break; 842 case V4L2_PIX_FMT_SBGGR8: 843 case V4L2_PIX_FMT_SGBRG8: 844 case V4L2_PIX_FMT_SGRBG8: 845 case V4L2_PIX_FMT_SRGGB8: 846 case V4L2_PIX_FMT_GREY: 847 offset = image->rect.left + image->rect.top * pix->bytesperline; 848 break; 849 case V4L2_PIX_FMT_SBGGR16: 850 case V4L2_PIX_FMT_SGBRG16: 851 case V4L2_PIX_FMT_SGRBG16: 852 case V4L2_PIX_FMT_SRGGB16: 853 case V4L2_PIX_FMT_Y16: 854 offset = image->rect.left * 2 + 855 image->rect.top * pix->bytesperline; 856 break; 857 default: 858 /* This should not happen */ 859 WARN_ON(1); 860 offset = 0; 861 ret = -EINVAL; 862 } 863 864 ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset); 865 ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset); 866 867 return ret; 868 } 869 EXPORT_SYMBOL_GPL(ipu_cpmem_set_image); 870 871 void ipu_cpmem_dump(struct ipuv3_channel *ch) 872 { 873 struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch); 874 struct ipu_soc *ipu = ch->ipu; 875 int chno = ch->num; 876 877 dev_dbg(ipu->dev, "ch %d word 0 - %08X %08X %08X %08X %08X\n", chno, 878 readl(&p->word[0].data[0]), 879 readl(&p->word[0].data[1]), 880 readl(&p->word[0].data[2]), 881 readl(&p->word[0].data[3]), 882 readl(&p->word[0].data[4])); 883 dev_dbg(ipu->dev, "ch %d word 1 - %08X %08X %08X %08X %08X\n", chno, 884 readl(&p->word[1].data[0]), 885 readl(&p->word[1].data[1]), 886 readl(&p->word[1].data[2]), 887 readl(&p->word[1].data[3]), 888 readl(&p->word[1].data[4])); 889 dev_dbg(ipu->dev, "PFS 0x%x, ", 890 ipu_ch_param_read_field(ch, IPU_FIELD_PFS)); 891 dev_dbg(ipu->dev, "BPP 0x%x, ", 892 ipu_ch_param_read_field(ch, IPU_FIELD_BPP)); 893 dev_dbg(ipu->dev, "NPB 0x%x\n", 894 ipu_ch_param_read_field(ch, IPU_FIELD_NPB)); 895 896 dev_dbg(ipu->dev, "FW %d, ", 897 ipu_ch_param_read_field(ch, IPU_FIELD_FW)); 898 dev_dbg(ipu->dev, "FH %d, ", 899 ipu_ch_param_read_field(ch, IPU_FIELD_FH)); 900 dev_dbg(ipu->dev, "EBA0 0x%x\n", 901 ipu_ch_param_read_field(ch, IPU_FIELD_EBA0) << 3); 902 dev_dbg(ipu->dev, "EBA1 0x%x\n", 903 ipu_ch_param_read_field(ch, IPU_FIELD_EBA1) << 3); 904 dev_dbg(ipu->dev, "Stride %d\n", 905 ipu_ch_param_read_field(ch, IPU_FIELD_SL)); 906 dev_dbg(ipu->dev, "scan_order %d\n", 907 ipu_ch_param_read_field(ch, IPU_FIELD_SO)); 908 dev_dbg(ipu->dev, "uv_stride %d\n", 909 ipu_ch_param_read_field(ch, IPU_FIELD_SLUV)); 910 dev_dbg(ipu->dev, "u_offset 0x%x\n", 911 ipu_ch_param_read_field(ch, IPU_FIELD_UBO) << 3); 912 dev_dbg(ipu->dev, "v_offset 0x%x\n", 913 ipu_ch_param_read_field(ch, IPU_FIELD_VBO) << 3); 914 915 dev_dbg(ipu->dev, "Width0 %d+1, ", 916 ipu_ch_param_read_field(ch, IPU_FIELD_WID0)); 917 dev_dbg(ipu->dev, "Width1 %d+1, ", 918 ipu_ch_param_read_field(ch, IPU_FIELD_WID1)); 919 dev_dbg(ipu->dev, "Width2 %d+1, ", 920 ipu_ch_param_read_field(ch, IPU_FIELD_WID2)); 921 dev_dbg(ipu->dev, "Width3 %d+1, ", 922 ipu_ch_param_read_field(ch, IPU_FIELD_WID3)); 923 dev_dbg(ipu->dev, "Offset0 %d, ", 924 ipu_ch_param_read_field(ch, IPU_FIELD_OFS0)); 925 dev_dbg(ipu->dev, "Offset1 %d, ", 926 ipu_ch_param_read_field(ch, IPU_FIELD_OFS1)); 927 dev_dbg(ipu->dev, "Offset2 %d, ", 928 ipu_ch_param_read_field(ch, IPU_FIELD_OFS2)); 929 dev_dbg(ipu->dev, "Offset3 %d\n", 930 ipu_ch_param_read_field(ch, IPU_FIELD_OFS3)); 931 } 932 EXPORT_SYMBOL_GPL(ipu_cpmem_dump); 933 934 int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base) 935 { 936 struct ipu_cpmem *cpmem; 937 938 cpmem = devm_kzalloc(dev, sizeof(*cpmem), GFP_KERNEL); 939 if (!cpmem) 940 return -ENOMEM; 941 942 ipu->cpmem_priv = cpmem; 943 944 spin_lock_init(&cpmem->lock); 945 cpmem->base = devm_ioremap(dev, base, SZ_128K); 946 if (!cpmem->base) 947 return -ENOMEM; 948 949 dev_dbg(dev, "CPMEM base: 0x%08lx remapped to %p\n", 950 base, cpmem->base); 951 cpmem->ipu = ipu; 952 953 return 0; 954 } 955 956 void ipu_cpmem_exit(struct ipu_soc *ipu) 957 { 958 } 959