1 /* 2 * Copyright (C) 2012 Mentor Graphics Inc. 3 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 #include <linux/types.h> 13 #include <linux/bitrev.h> 14 #include <linux/io.h> 15 #include <linux/sizes.h> 16 #include <drm/drm_fourcc.h> 17 #include "ipu-prv.h" 18 19 struct ipu_cpmem_word { 20 u32 data[5]; 21 u32 res[3]; 22 }; 23 24 struct ipu_ch_param { 25 struct ipu_cpmem_word word[2]; 26 }; 27 28 struct ipu_cpmem { 29 struct ipu_ch_param __iomem *base; 30 u32 module; 31 spinlock_t lock; 32 int use_count; 33 struct ipu_soc *ipu; 34 }; 35 36 #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size)) 37 38 #define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22) 39 #define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22) 40 #define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4) 41 #define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1) 42 #define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1) 43 #define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14) 44 #define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14) 45 46 #define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10) 47 #define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9) 48 #define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13) 49 #define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12) 50 #define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1) 51 #define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1) 52 #define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12) 53 #define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11) 54 #define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10) 55 #define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7) 56 #define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10) 57 #define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1) 58 #define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1) 59 #define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7) 60 #define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1) 61 #define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1) 62 #define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3) 63 #define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2) 64 #define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1) 65 #define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3) 66 #define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2) 67 #define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1) 68 #define IPU_FIELD_ROT_HF_VF IPU_CPMEM_WORD(0, 119, 3) 69 #define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1) 70 #define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1) 71 #define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1) 72 #define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1) 73 #define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1) 74 #define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13) 75 #define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12) 76 #define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29) 77 #define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29) 78 #define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20) 79 #define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7) 80 #define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4) 81 #define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1) 82 #define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3) 83 #define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2) 84 #define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7) 85 #define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14) 86 #define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3) 87 #define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3) 88 #define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3) 89 #define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3) 90 #define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5) 91 #define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5) 92 #define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5) 93 #define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5) 94 #define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1) 95 #define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1) 96 #define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1) 97 98 static inline struct ipu_ch_param __iomem * 99 ipu_get_cpmem(struct ipuv3_channel *ch) 100 { 101 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; 102 103 return cpmem->base + ch->num; 104 } 105 106 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) 107 { 108 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); 109 u32 bit = (wbs >> 8) % 160; 110 u32 size = wbs & 0xff; 111 u32 word = (wbs >> 8) / 160; 112 u32 i = bit / 32; 113 u32 ofs = bit % 32; 114 u32 mask = (1 << size) - 1; 115 u32 val; 116 117 pr_debug("%s %d %d %d\n", __func__, word, bit , size); 118 119 val = readl(&base->word[word].data[i]); 120 val &= ~(mask << ofs); 121 val |= v << ofs; 122 writel(val, &base->word[word].data[i]); 123 124 if ((bit + size - 1) / 32 > i) { 125 val = readl(&base->word[word].data[i + 1]); 126 val &= ~(mask >> (ofs ? (32 - ofs) : 0)); 127 val |= v >> (ofs ? (32 - ofs) : 0); 128 writel(val, &base->word[word].data[i + 1]); 129 } 130 } 131 132 static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs) 133 { 134 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); 135 u32 bit = (wbs >> 8) % 160; 136 u32 size = wbs & 0xff; 137 u32 word = (wbs >> 8) / 160; 138 u32 i = bit / 32; 139 u32 ofs = bit % 32; 140 u32 mask = (1 << size) - 1; 141 u32 val = 0; 142 143 pr_debug("%s %d %d %d\n", __func__, word, bit , size); 144 145 val = (readl(&base->word[word].data[i]) >> ofs) & mask; 146 147 if ((bit + size - 1) / 32 > i) { 148 u32 tmp; 149 150 tmp = readl(&base->word[word].data[i + 1]); 151 tmp &= mask >> (ofs ? (32 - ofs) : 0); 152 val |= tmp << (ofs ? (32 - ofs) : 0); 153 } 154 155 return val; 156 } 157 158 /* 159 * The V4L2 spec defines packed RGB formats in memory byte order, which from 160 * point of view of the IPU corresponds to little-endian words with the first 161 * component in the least significant bits. 162 * The DRM pixel formats and IPU internal representation are ordered the other 163 * way around, with the first named component ordered at the most significant 164 * bits. Further, V4L2 formats are not well defined: 165 * https://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html 166 * We choose the interpretation which matches GStreamer behavior. 167 */ 168 static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat) 169 { 170 switch (pixelformat) { 171 case V4L2_PIX_FMT_RGB565: 172 /* 173 * Here we choose the 'corrected' interpretation of RGBP, a 174 * little-endian 16-bit word with the red component at the most 175 * significant bits: 176 * g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B 177 */ 178 return DRM_FORMAT_RGB565; 179 case V4L2_PIX_FMT_BGR24: 180 /* B G R <=> [24:0] R:G:B */ 181 return DRM_FORMAT_RGB888; 182 case V4L2_PIX_FMT_RGB24: 183 /* R G B <=> [24:0] B:G:R */ 184 return DRM_FORMAT_BGR888; 185 case V4L2_PIX_FMT_BGR32: 186 /* B G R A <=> [32:0] A:B:G:R */ 187 return DRM_FORMAT_XRGB8888; 188 case V4L2_PIX_FMT_RGB32: 189 /* R G B A <=> [32:0] A:B:G:R */ 190 return DRM_FORMAT_XBGR8888; 191 case V4L2_PIX_FMT_XBGR32: 192 /* B G R X <=> [32:0] X:R:G:B */ 193 return DRM_FORMAT_XRGB8888; 194 case V4L2_PIX_FMT_XRGB32: 195 /* X R G B <=> [32:0] B:G:R:X */ 196 return DRM_FORMAT_BGRX8888; 197 case V4L2_PIX_FMT_UYVY: 198 return DRM_FORMAT_UYVY; 199 case V4L2_PIX_FMT_YUYV: 200 return DRM_FORMAT_YUYV; 201 case V4L2_PIX_FMT_YUV420: 202 return DRM_FORMAT_YUV420; 203 case V4L2_PIX_FMT_YUV422P: 204 return DRM_FORMAT_YUV422; 205 case V4L2_PIX_FMT_YVU420: 206 return DRM_FORMAT_YVU420; 207 case V4L2_PIX_FMT_NV12: 208 return DRM_FORMAT_NV12; 209 case V4L2_PIX_FMT_NV16: 210 return DRM_FORMAT_NV16; 211 } 212 213 return -EINVAL; 214 } 215 216 void ipu_cpmem_zero(struct ipuv3_channel *ch) 217 { 218 struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch); 219 void __iomem *base = p; 220 int i; 221 222 for (i = 0; i < sizeof(*p) / sizeof(u32); i++) 223 writel(0, base + i * sizeof(u32)); 224 } 225 EXPORT_SYMBOL_GPL(ipu_cpmem_zero); 226 227 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres) 228 { 229 ipu_ch_param_write_field(ch, IPU_FIELD_FW, xres - 1); 230 ipu_ch_param_write_field(ch, IPU_FIELD_FH, yres - 1); 231 } 232 EXPORT_SYMBOL_GPL(ipu_cpmem_set_resolution); 233 234 void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch) 235 { 236 ipu_ch_param_write_field(ch, IPU_FIELD_RDRW, 1); 237 } 238 EXPORT_SYMBOL_GPL(ipu_cpmem_skip_odd_chroma_rows); 239 240 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride) 241 { 242 ipu_ch_param_write_field(ch, IPU_FIELD_SLY, stride - 1); 243 } 244 EXPORT_SYMBOL_GPL(ipu_cpmem_set_stride); 245 246 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch) 247 { 248 struct ipu_soc *ipu = ch->ipu; 249 u32 val; 250 251 if (ipu->ipu_type == IPUV3EX) 252 ipu_ch_param_write_field(ch, IPU_FIELD_ID, 1); 253 254 val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num)); 255 val |= 1 << (ch->num % 32); 256 ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num)); 257 }; 258 EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority); 259 260 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf) 261 { 262 if (bufnum) 263 ipu_ch_param_write_field(ch, IPU_FIELD_EBA1, buf >> 3); 264 else 265 ipu_ch_param_write_field(ch, IPU_FIELD_EBA0, buf >> 3); 266 } 267 EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer); 268 269 void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off) 270 { 271 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_off / 8); 272 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_off / 8); 273 } 274 EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset); 275 276 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride) 277 { 278 u32 ilo, sly; 279 280 if (stride < 0) { 281 stride = -stride; 282 ilo = 0x100000 - (stride / 8); 283 } else { 284 ilo = stride / 8; 285 } 286 287 sly = (stride * 2) - 1; 288 289 ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1); 290 ipu_ch_param_write_field(ch, IPU_FIELD_ILO, ilo); 291 ipu_ch_param_write_field(ch, IPU_FIELD_SLY, sly); 292 }; 293 EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan); 294 295 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id) 296 { 297 id &= 0x3; 298 ipu_ch_param_write_field(ch, IPU_FIELD_ID, id); 299 } 300 EXPORT_SYMBOL_GPL(ipu_cpmem_set_axi_id); 301 302 int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch) 303 { 304 return ipu_ch_param_read_field(ch, IPU_FIELD_NPB) + 1; 305 } 306 EXPORT_SYMBOL_GPL(ipu_cpmem_get_burstsize); 307 308 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize) 309 { 310 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1); 311 }; 312 EXPORT_SYMBOL_GPL(ipu_cpmem_set_burstsize); 313 314 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch) 315 { 316 ipu_ch_param_write_field(ch, IPU_FIELD_BM, 1); 317 } 318 EXPORT_SYMBOL_GPL(ipu_cpmem_set_block_mode); 319 320 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch, 321 enum ipu_rotate_mode rot) 322 { 323 u32 temp_rot = bitrev8(rot) >> 5; 324 325 ipu_ch_param_write_field(ch, IPU_FIELD_ROT_HF_VF, temp_rot); 326 } 327 EXPORT_SYMBOL_GPL(ipu_cpmem_set_rotation); 328 329 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch, 330 const struct ipu_rgb *rgb) 331 { 332 int bpp = 0, npb = 0, ro, go, bo, to; 333 334 ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset; 335 go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset; 336 bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset; 337 to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset; 338 339 ipu_ch_param_write_field(ch, IPU_FIELD_WID0, rgb->red.length - 1); 340 ipu_ch_param_write_field(ch, IPU_FIELD_OFS0, ro); 341 ipu_ch_param_write_field(ch, IPU_FIELD_WID1, rgb->green.length - 1); 342 ipu_ch_param_write_field(ch, IPU_FIELD_OFS1, go); 343 ipu_ch_param_write_field(ch, IPU_FIELD_WID2, rgb->blue.length - 1); 344 ipu_ch_param_write_field(ch, IPU_FIELD_OFS2, bo); 345 346 if (rgb->transp.length) { 347 ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 348 rgb->transp.length - 1); 349 ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, to); 350 } else { 351 ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7); 352 ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, 353 rgb->bits_per_pixel); 354 } 355 356 switch (rgb->bits_per_pixel) { 357 case 32: 358 bpp = 0; 359 npb = 15; 360 break; 361 case 24: 362 bpp = 1; 363 npb = 19; 364 break; 365 case 16: 366 bpp = 3; 367 npb = 31; 368 break; 369 case 8: 370 bpp = 5; 371 npb = 63; 372 break; 373 default: 374 return -EINVAL; 375 } 376 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp); 377 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb); 378 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 7); /* rgb mode */ 379 380 return 0; 381 } 382 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb); 383 384 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width) 385 { 386 int bpp = 0, npb = 0; 387 388 switch (width) { 389 case 32: 390 bpp = 0; 391 npb = 15; 392 break; 393 case 24: 394 bpp = 1; 395 npb = 19; 396 break; 397 case 16: 398 bpp = 3; 399 npb = 31; 400 break; 401 case 8: 402 bpp = 5; 403 npb = 63; 404 break; 405 default: 406 return -EINVAL; 407 } 408 409 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp); 410 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb); 411 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 6); /* raw mode */ 412 413 return 0; 414 } 415 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough); 416 417 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format) 418 { 419 switch (pixel_format) { 420 case V4L2_PIX_FMT_UYVY: 421 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */ 422 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);/* pix fmt */ 423 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */ 424 break; 425 case V4L2_PIX_FMT_YUYV: 426 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */ 427 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);/* pix fmt */ 428 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */ 429 break; 430 } 431 } 432 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved); 433 434 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, 435 unsigned int uv_stride, 436 unsigned int u_offset, unsigned int v_offset) 437 { 438 ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, uv_stride - 1); 439 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8); 440 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8); 441 } 442 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full); 443 444 static const struct ipu_rgb def_xrgb_32 = { 445 .red = { .offset = 16, .length = 8, }, 446 .green = { .offset = 8, .length = 8, }, 447 .blue = { .offset = 0, .length = 8, }, 448 .transp = { .offset = 24, .length = 8, }, 449 .bits_per_pixel = 32, 450 }; 451 452 static const struct ipu_rgb def_xbgr_32 = { 453 .red = { .offset = 0, .length = 8, }, 454 .green = { .offset = 8, .length = 8, }, 455 .blue = { .offset = 16, .length = 8, }, 456 .transp = { .offset = 24, .length = 8, }, 457 .bits_per_pixel = 32, 458 }; 459 460 static const struct ipu_rgb def_rgbx_32 = { 461 .red = { .offset = 24, .length = 8, }, 462 .green = { .offset = 16, .length = 8, }, 463 .blue = { .offset = 8, .length = 8, }, 464 .transp = { .offset = 0, .length = 8, }, 465 .bits_per_pixel = 32, 466 }; 467 468 static const struct ipu_rgb def_bgrx_32 = { 469 .red = { .offset = 8, .length = 8, }, 470 .green = { .offset = 16, .length = 8, }, 471 .blue = { .offset = 24, .length = 8, }, 472 .transp = { .offset = 0, .length = 8, }, 473 .bits_per_pixel = 32, 474 }; 475 476 static const struct ipu_rgb def_rgb_24 = { 477 .red = { .offset = 16, .length = 8, }, 478 .green = { .offset = 8, .length = 8, }, 479 .blue = { .offset = 0, .length = 8, }, 480 .transp = { .offset = 0, .length = 0, }, 481 .bits_per_pixel = 24, 482 }; 483 484 static const struct ipu_rgb def_bgr_24 = { 485 .red = { .offset = 0, .length = 8, }, 486 .green = { .offset = 8, .length = 8, }, 487 .blue = { .offset = 16, .length = 8, }, 488 .transp = { .offset = 0, .length = 0, }, 489 .bits_per_pixel = 24, 490 }; 491 492 static const struct ipu_rgb def_rgb_16 = { 493 .red = { .offset = 11, .length = 5, }, 494 .green = { .offset = 5, .length = 6, }, 495 .blue = { .offset = 0, .length = 5, }, 496 .transp = { .offset = 0, .length = 0, }, 497 .bits_per_pixel = 16, 498 }; 499 500 static const struct ipu_rgb def_bgr_16 = { 501 .red = { .offset = 0, .length = 5, }, 502 .green = { .offset = 5, .length = 6, }, 503 .blue = { .offset = 11, .length = 5, }, 504 .transp = { .offset = 0, .length = 0, }, 505 .bits_per_pixel = 16, 506 }; 507 508 static const struct ipu_rgb def_argb_16 = { 509 .red = { .offset = 10, .length = 5, }, 510 .green = { .offset = 5, .length = 5, }, 511 .blue = { .offset = 0, .length = 5, }, 512 .transp = { .offset = 15, .length = 1, }, 513 .bits_per_pixel = 16, 514 }; 515 516 static const struct ipu_rgb def_argb_16_4444 = { 517 .red = { .offset = 8, .length = 4, }, 518 .green = { .offset = 4, .length = 4, }, 519 .blue = { .offset = 0, .length = 4, }, 520 .transp = { .offset = 12, .length = 4, }, 521 .bits_per_pixel = 16, 522 }; 523 524 static const struct ipu_rgb def_abgr_16 = { 525 .red = { .offset = 0, .length = 5, }, 526 .green = { .offset = 5, .length = 5, }, 527 .blue = { .offset = 10, .length = 5, }, 528 .transp = { .offset = 15, .length = 1, }, 529 .bits_per_pixel = 16, 530 }; 531 532 static const struct ipu_rgb def_rgba_16 = { 533 .red = { .offset = 11, .length = 5, }, 534 .green = { .offset = 6, .length = 5, }, 535 .blue = { .offset = 1, .length = 5, }, 536 .transp = { .offset = 0, .length = 1, }, 537 .bits_per_pixel = 16, 538 }; 539 540 static const struct ipu_rgb def_bgra_16 = { 541 .red = { .offset = 1, .length = 5, }, 542 .green = { .offset = 6, .length = 5, }, 543 .blue = { .offset = 11, .length = 5, }, 544 .transp = { .offset = 0, .length = 1, }, 545 .bits_per_pixel = 16, 546 }; 547 548 #define Y_OFFSET(pix, x, y) ((x) + pix->width * (y)) 549 #define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 550 (pix->width * ((y) / 2) / 2) + (x) / 2) 551 #define V_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 552 (pix->width * pix->height / 4) + \ 553 (pix->width * ((y) / 2) / 2) + (x) / 2) 554 #define U2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 555 (pix->width * (y) / 2) + (x) / 2) 556 #define V2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 557 (pix->width * pix->height / 2) + \ 558 (pix->width * (y) / 2) + (x) / 2) 559 #define UV_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 560 (pix->width * ((y) / 2)) + (x)) 561 #define UV2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ 562 (pix->width * y) + (x)) 563 564 #define NUM_ALPHA_CHANNELS 7 565 566 /* See Table 37-12. Alpha channels mapping. */ 567 static int ipu_channel_albm(int ch_num) 568 { 569 switch (ch_num) { 570 case IPUV3_CHANNEL_G_MEM_IC_PRP_VF: return 0; 571 case IPUV3_CHANNEL_G_MEM_IC_PP: return 1; 572 case IPUV3_CHANNEL_MEM_FG_SYNC: return 2; 573 case IPUV3_CHANNEL_MEM_FG_ASYNC: return 3; 574 case IPUV3_CHANNEL_MEM_BG_SYNC: return 4; 575 case IPUV3_CHANNEL_MEM_BG_ASYNC: return 5; 576 case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB: return 6; 577 default: 578 return -EINVAL; 579 } 580 } 581 582 static void ipu_cpmem_set_separate_alpha(struct ipuv3_channel *ch) 583 { 584 struct ipu_soc *ipu = ch->ipu; 585 int albm; 586 u32 val; 587 588 albm = ipu_channel_albm(ch->num); 589 if (albm < 0) 590 return; 591 592 ipu_ch_param_write_field(ch, IPU_FIELD_ALU, 1); 593 ipu_ch_param_write_field(ch, IPU_FIELD_ALBM, albm); 594 ipu_ch_param_write_field(ch, IPU_FIELD_CRE, 1); 595 596 val = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA); 597 val |= BIT(ch->num); 598 ipu_idmac_write(ipu, val, IDMAC_SEP_ALPHA); 599 } 600 601 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc) 602 { 603 switch (drm_fourcc) { 604 case DRM_FORMAT_YUV420: 605 case DRM_FORMAT_YVU420: 606 /* pix format */ 607 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 2); 608 /* burst size */ 609 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 610 break; 611 case DRM_FORMAT_YUV422: 612 case DRM_FORMAT_YVU422: 613 /* pix format */ 614 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 1); 615 /* burst size */ 616 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 617 break; 618 case DRM_FORMAT_YUV444: 619 case DRM_FORMAT_YVU444: 620 /* pix format */ 621 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0); 622 /* burst size */ 623 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 624 break; 625 case DRM_FORMAT_NV12: 626 /* pix format */ 627 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 4); 628 /* burst size */ 629 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 630 break; 631 case DRM_FORMAT_NV16: 632 /* pix format */ 633 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 3); 634 /* burst size */ 635 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 636 break; 637 case DRM_FORMAT_UYVY: 638 /* bits/pixel */ 639 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); 640 /* pix format */ 641 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA); 642 /* burst size */ 643 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 644 break; 645 case DRM_FORMAT_YUYV: 646 /* bits/pixel */ 647 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); 648 /* pix format */ 649 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8); 650 /* burst size */ 651 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31); 652 break; 653 case DRM_FORMAT_ABGR8888: 654 case DRM_FORMAT_XBGR8888: 655 ipu_cpmem_set_format_rgb(ch, &def_xbgr_32); 656 break; 657 case DRM_FORMAT_ARGB8888: 658 case DRM_FORMAT_XRGB8888: 659 ipu_cpmem_set_format_rgb(ch, &def_xrgb_32); 660 break; 661 case DRM_FORMAT_RGBA8888: 662 case DRM_FORMAT_RGBX8888: 663 case DRM_FORMAT_RGBX8888_A8: 664 ipu_cpmem_set_format_rgb(ch, &def_rgbx_32); 665 break; 666 case DRM_FORMAT_BGRA8888: 667 case DRM_FORMAT_BGRX8888: 668 case DRM_FORMAT_BGRX8888_A8: 669 ipu_cpmem_set_format_rgb(ch, &def_bgrx_32); 670 break; 671 case DRM_FORMAT_BGR888: 672 case DRM_FORMAT_BGR888_A8: 673 ipu_cpmem_set_format_rgb(ch, &def_bgr_24); 674 break; 675 case DRM_FORMAT_RGB888: 676 case DRM_FORMAT_RGB888_A8: 677 ipu_cpmem_set_format_rgb(ch, &def_rgb_24); 678 break; 679 case DRM_FORMAT_RGB565: 680 case DRM_FORMAT_RGB565_A8: 681 ipu_cpmem_set_format_rgb(ch, &def_rgb_16); 682 break; 683 case DRM_FORMAT_BGR565: 684 case DRM_FORMAT_BGR565_A8: 685 ipu_cpmem_set_format_rgb(ch, &def_bgr_16); 686 break; 687 case DRM_FORMAT_ARGB1555: 688 ipu_cpmem_set_format_rgb(ch, &def_argb_16); 689 break; 690 case DRM_FORMAT_ABGR1555: 691 ipu_cpmem_set_format_rgb(ch, &def_abgr_16); 692 break; 693 case DRM_FORMAT_RGBA5551: 694 ipu_cpmem_set_format_rgb(ch, &def_rgba_16); 695 break; 696 case DRM_FORMAT_BGRA5551: 697 ipu_cpmem_set_format_rgb(ch, &def_bgra_16); 698 break; 699 case DRM_FORMAT_ARGB4444: 700 ipu_cpmem_set_format_rgb(ch, &def_argb_16_4444); 701 break; 702 default: 703 return -EINVAL; 704 } 705 706 switch (drm_fourcc) { 707 case DRM_FORMAT_RGB565_A8: 708 case DRM_FORMAT_BGR565_A8: 709 case DRM_FORMAT_RGB888_A8: 710 case DRM_FORMAT_BGR888_A8: 711 case DRM_FORMAT_RGBX8888_A8: 712 case DRM_FORMAT_BGRX8888_A8: 713 ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7); 714 ipu_cpmem_set_separate_alpha(ch); 715 break; 716 default: 717 break; 718 } 719 720 return 0; 721 } 722 EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt); 723 724 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image) 725 { 726 struct v4l2_pix_format *pix = &image->pix; 727 int offset, u_offset, v_offset; 728 int ret = 0; 729 730 pr_debug("%s: resolution: %dx%d stride: %d\n", 731 __func__, pix->width, pix->height, 732 pix->bytesperline); 733 734 ipu_cpmem_set_resolution(ch, image->rect.width, image->rect.height); 735 ipu_cpmem_set_stride(ch, pix->bytesperline); 736 737 ipu_cpmem_set_fmt(ch, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat)); 738 739 switch (pix->pixelformat) { 740 case V4L2_PIX_FMT_YUV420: 741 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 742 u_offset = U_OFFSET(pix, image->rect.left, 743 image->rect.top) - offset; 744 v_offset = V_OFFSET(pix, image->rect.left, 745 image->rect.top) - offset; 746 747 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2, 748 u_offset, v_offset); 749 break; 750 case V4L2_PIX_FMT_YVU420: 751 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 752 u_offset = U_OFFSET(pix, image->rect.left, 753 image->rect.top) - offset; 754 v_offset = V_OFFSET(pix, image->rect.left, 755 image->rect.top) - offset; 756 757 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2, 758 v_offset, u_offset); 759 break; 760 case V4L2_PIX_FMT_YUV422P: 761 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 762 u_offset = U2_OFFSET(pix, image->rect.left, 763 image->rect.top) - offset; 764 v_offset = V2_OFFSET(pix, image->rect.left, 765 image->rect.top) - offset; 766 767 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2, 768 u_offset, v_offset); 769 break; 770 case V4L2_PIX_FMT_NV12: 771 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 772 u_offset = UV_OFFSET(pix, image->rect.left, 773 image->rect.top) - offset; 774 v_offset = 0; 775 776 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline, 777 u_offset, v_offset); 778 break; 779 case V4L2_PIX_FMT_NV16: 780 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 781 u_offset = UV2_OFFSET(pix, image->rect.left, 782 image->rect.top) - offset; 783 v_offset = 0; 784 785 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline, 786 u_offset, v_offset); 787 break; 788 case V4L2_PIX_FMT_UYVY: 789 case V4L2_PIX_FMT_YUYV: 790 case V4L2_PIX_FMT_RGB565: 791 offset = image->rect.left * 2 + 792 image->rect.top * pix->bytesperline; 793 break; 794 case V4L2_PIX_FMT_RGB32: 795 case V4L2_PIX_FMT_BGR32: 796 case V4L2_PIX_FMT_XRGB32: 797 case V4L2_PIX_FMT_XBGR32: 798 offset = image->rect.left * 4 + 799 image->rect.top * pix->bytesperline; 800 break; 801 case V4L2_PIX_FMT_RGB24: 802 case V4L2_PIX_FMT_BGR24: 803 offset = image->rect.left * 3 + 804 image->rect.top * pix->bytesperline; 805 break; 806 case V4L2_PIX_FMT_SBGGR8: 807 case V4L2_PIX_FMT_SGBRG8: 808 case V4L2_PIX_FMT_SGRBG8: 809 case V4L2_PIX_FMT_SRGGB8: 810 case V4L2_PIX_FMT_GREY: 811 offset = image->rect.left + image->rect.top * pix->bytesperline; 812 break; 813 case V4L2_PIX_FMT_SBGGR16: 814 case V4L2_PIX_FMT_SGBRG16: 815 case V4L2_PIX_FMT_SGRBG16: 816 case V4L2_PIX_FMT_SRGGB16: 817 case V4L2_PIX_FMT_Y16: 818 offset = image->rect.left * 2 + 819 image->rect.top * pix->bytesperline; 820 break; 821 default: 822 /* This should not happen */ 823 WARN_ON(1); 824 offset = 0; 825 ret = -EINVAL; 826 } 827 828 ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset); 829 ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset); 830 831 return ret; 832 } 833 EXPORT_SYMBOL_GPL(ipu_cpmem_set_image); 834 835 void ipu_cpmem_dump(struct ipuv3_channel *ch) 836 { 837 struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch); 838 struct ipu_soc *ipu = ch->ipu; 839 int chno = ch->num; 840 841 dev_dbg(ipu->dev, "ch %d word 0 - %08X %08X %08X %08X %08X\n", chno, 842 readl(&p->word[0].data[0]), 843 readl(&p->word[0].data[1]), 844 readl(&p->word[0].data[2]), 845 readl(&p->word[0].data[3]), 846 readl(&p->word[0].data[4])); 847 dev_dbg(ipu->dev, "ch %d word 1 - %08X %08X %08X %08X %08X\n", chno, 848 readl(&p->word[1].data[0]), 849 readl(&p->word[1].data[1]), 850 readl(&p->word[1].data[2]), 851 readl(&p->word[1].data[3]), 852 readl(&p->word[1].data[4])); 853 dev_dbg(ipu->dev, "PFS 0x%x, ", 854 ipu_ch_param_read_field(ch, IPU_FIELD_PFS)); 855 dev_dbg(ipu->dev, "BPP 0x%x, ", 856 ipu_ch_param_read_field(ch, IPU_FIELD_BPP)); 857 dev_dbg(ipu->dev, "NPB 0x%x\n", 858 ipu_ch_param_read_field(ch, IPU_FIELD_NPB)); 859 860 dev_dbg(ipu->dev, "FW %d, ", 861 ipu_ch_param_read_field(ch, IPU_FIELD_FW)); 862 dev_dbg(ipu->dev, "FH %d, ", 863 ipu_ch_param_read_field(ch, IPU_FIELD_FH)); 864 dev_dbg(ipu->dev, "EBA0 0x%x\n", 865 ipu_ch_param_read_field(ch, IPU_FIELD_EBA0) << 3); 866 dev_dbg(ipu->dev, "EBA1 0x%x\n", 867 ipu_ch_param_read_field(ch, IPU_FIELD_EBA1) << 3); 868 dev_dbg(ipu->dev, "Stride %d\n", 869 ipu_ch_param_read_field(ch, IPU_FIELD_SL)); 870 dev_dbg(ipu->dev, "scan_order %d\n", 871 ipu_ch_param_read_field(ch, IPU_FIELD_SO)); 872 dev_dbg(ipu->dev, "uv_stride %d\n", 873 ipu_ch_param_read_field(ch, IPU_FIELD_SLUV)); 874 dev_dbg(ipu->dev, "u_offset 0x%x\n", 875 ipu_ch_param_read_field(ch, IPU_FIELD_UBO) << 3); 876 dev_dbg(ipu->dev, "v_offset 0x%x\n", 877 ipu_ch_param_read_field(ch, IPU_FIELD_VBO) << 3); 878 879 dev_dbg(ipu->dev, "Width0 %d+1, ", 880 ipu_ch_param_read_field(ch, IPU_FIELD_WID0)); 881 dev_dbg(ipu->dev, "Width1 %d+1, ", 882 ipu_ch_param_read_field(ch, IPU_FIELD_WID1)); 883 dev_dbg(ipu->dev, "Width2 %d+1, ", 884 ipu_ch_param_read_field(ch, IPU_FIELD_WID2)); 885 dev_dbg(ipu->dev, "Width3 %d+1, ", 886 ipu_ch_param_read_field(ch, IPU_FIELD_WID3)); 887 dev_dbg(ipu->dev, "Offset0 %d, ", 888 ipu_ch_param_read_field(ch, IPU_FIELD_OFS0)); 889 dev_dbg(ipu->dev, "Offset1 %d, ", 890 ipu_ch_param_read_field(ch, IPU_FIELD_OFS1)); 891 dev_dbg(ipu->dev, "Offset2 %d, ", 892 ipu_ch_param_read_field(ch, IPU_FIELD_OFS2)); 893 dev_dbg(ipu->dev, "Offset3 %d\n", 894 ipu_ch_param_read_field(ch, IPU_FIELD_OFS3)); 895 } 896 EXPORT_SYMBOL_GPL(ipu_cpmem_dump); 897 898 int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base) 899 { 900 struct ipu_cpmem *cpmem; 901 902 cpmem = devm_kzalloc(dev, sizeof(*cpmem), GFP_KERNEL); 903 if (!cpmem) 904 return -ENOMEM; 905 906 ipu->cpmem_priv = cpmem; 907 908 spin_lock_init(&cpmem->lock); 909 cpmem->base = devm_ioremap(dev, base, SZ_128K); 910 if (!cpmem->base) 911 return -ENOMEM; 912 913 dev_dbg(dev, "CPMEM base: 0x%08lx remapped to %p\n", 914 base, cpmem->base); 915 cpmem->ipu = ipu; 916 917 return 0; 918 } 919 920 void ipu_cpmem_exit(struct ipu_soc *ipu) 921 { 922 } 923