1 /* 2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> 3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 */ 15 #include <linux/module.h> 16 #include <linux/export.h> 17 #include <linux/types.h> 18 #include <linux/reset.h> 19 #include <linux/platform_device.h> 20 #include <linux/err.h> 21 #include <linux/spinlock.h> 22 #include <linux/delay.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/clk.h> 26 #include <linux/list.h> 27 #include <linux/irq.h> 28 #include <linux/irqchip/chained_irq.h> 29 #include <linux/irqdomain.h> 30 #include <linux/of_device.h> 31 #include <linux/of_graph.h> 32 33 #include <drm/drm_fourcc.h> 34 35 #include <video/imx-ipu-v3.h> 36 #include "ipu-prv.h" 37 38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) 39 { 40 return readl(ipu->cm_reg + offset); 41 } 42 43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) 44 { 45 writel(value, ipu->cm_reg + offset); 46 } 47 48 int ipu_get_num(struct ipu_soc *ipu) 49 { 50 return ipu->id; 51 } 52 EXPORT_SYMBOL_GPL(ipu_get_num); 53 54 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync) 55 { 56 u32 val; 57 58 val = ipu_cm_read(ipu, IPU_SRM_PRI2); 59 val &= ~DP_S_SRM_MODE_MASK; 60 val |= sync ? DP_S_SRM_MODE_NEXT_FRAME : 61 DP_S_SRM_MODE_NOW; 62 ipu_cm_write(ipu, val, IPU_SRM_PRI2); 63 } 64 EXPORT_SYMBOL_GPL(ipu_srm_dp_update); 65 66 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc) 67 { 68 switch (drm_fourcc) { 69 case DRM_FORMAT_ARGB1555: 70 case DRM_FORMAT_ABGR1555: 71 case DRM_FORMAT_RGBA5551: 72 case DRM_FORMAT_BGRA5551: 73 case DRM_FORMAT_RGB565: 74 case DRM_FORMAT_BGR565: 75 case DRM_FORMAT_RGB888: 76 case DRM_FORMAT_BGR888: 77 case DRM_FORMAT_ARGB4444: 78 case DRM_FORMAT_XRGB8888: 79 case DRM_FORMAT_XBGR8888: 80 case DRM_FORMAT_RGBX8888: 81 case DRM_FORMAT_BGRX8888: 82 case DRM_FORMAT_ARGB8888: 83 case DRM_FORMAT_ABGR8888: 84 case DRM_FORMAT_RGBA8888: 85 case DRM_FORMAT_BGRA8888: 86 case DRM_FORMAT_RGB565_A8: 87 case DRM_FORMAT_BGR565_A8: 88 case DRM_FORMAT_RGB888_A8: 89 case DRM_FORMAT_BGR888_A8: 90 case DRM_FORMAT_RGBX8888_A8: 91 case DRM_FORMAT_BGRX8888_A8: 92 return IPUV3_COLORSPACE_RGB; 93 case DRM_FORMAT_YUYV: 94 case DRM_FORMAT_UYVY: 95 case DRM_FORMAT_YUV420: 96 case DRM_FORMAT_YVU420: 97 case DRM_FORMAT_YUV422: 98 case DRM_FORMAT_YVU422: 99 case DRM_FORMAT_YUV444: 100 case DRM_FORMAT_YVU444: 101 case DRM_FORMAT_NV12: 102 case DRM_FORMAT_NV21: 103 case DRM_FORMAT_NV16: 104 case DRM_FORMAT_NV61: 105 return IPUV3_COLORSPACE_YUV; 106 default: 107 return IPUV3_COLORSPACE_UNKNOWN; 108 } 109 } 110 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace); 111 112 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat) 113 { 114 switch (pixelformat) { 115 case V4L2_PIX_FMT_YUV420: 116 case V4L2_PIX_FMT_YVU420: 117 case V4L2_PIX_FMT_YUV422P: 118 case V4L2_PIX_FMT_UYVY: 119 case V4L2_PIX_FMT_YUYV: 120 case V4L2_PIX_FMT_NV12: 121 case V4L2_PIX_FMT_NV21: 122 case V4L2_PIX_FMT_NV16: 123 case V4L2_PIX_FMT_NV61: 124 return IPUV3_COLORSPACE_YUV; 125 case V4L2_PIX_FMT_RGB32: 126 case V4L2_PIX_FMT_BGR32: 127 case V4L2_PIX_FMT_RGB24: 128 case V4L2_PIX_FMT_BGR24: 129 case V4L2_PIX_FMT_RGB565: 130 return IPUV3_COLORSPACE_RGB; 131 default: 132 return IPUV3_COLORSPACE_UNKNOWN; 133 } 134 } 135 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace); 136 137 bool ipu_pixelformat_is_planar(u32 pixelformat) 138 { 139 switch (pixelformat) { 140 case V4L2_PIX_FMT_YUV420: 141 case V4L2_PIX_FMT_YVU420: 142 case V4L2_PIX_FMT_YUV422P: 143 case V4L2_PIX_FMT_NV12: 144 case V4L2_PIX_FMT_NV21: 145 case V4L2_PIX_FMT_NV16: 146 case V4L2_PIX_FMT_NV61: 147 return true; 148 } 149 150 return false; 151 } 152 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar); 153 154 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code) 155 { 156 switch (mbus_code & 0xf000) { 157 case 0x1000: 158 return IPUV3_COLORSPACE_RGB; 159 case 0x2000: 160 return IPUV3_COLORSPACE_YUV; 161 default: 162 return IPUV3_COLORSPACE_UNKNOWN; 163 } 164 } 165 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace); 166 167 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat) 168 { 169 switch (pixelformat) { 170 case V4L2_PIX_FMT_YUV420: 171 case V4L2_PIX_FMT_YVU420: 172 case V4L2_PIX_FMT_YUV422P: 173 case V4L2_PIX_FMT_NV12: 174 case V4L2_PIX_FMT_NV21: 175 case V4L2_PIX_FMT_NV16: 176 case V4L2_PIX_FMT_NV61: 177 /* 178 * for the planar YUV formats, the stride passed to 179 * cpmem must be the stride in bytes of the Y plane. 180 * And all the planar YUV formats have an 8-bit 181 * Y component. 182 */ 183 return (8 * pixel_stride) >> 3; 184 case V4L2_PIX_FMT_RGB565: 185 case V4L2_PIX_FMT_YUYV: 186 case V4L2_PIX_FMT_UYVY: 187 return (16 * pixel_stride) >> 3; 188 case V4L2_PIX_FMT_BGR24: 189 case V4L2_PIX_FMT_RGB24: 190 return (24 * pixel_stride) >> 3; 191 case V4L2_PIX_FMT_BGR32: 192 case V4L2_PIX_FMT_RGB32: 193 return (32 * pixel_stride) >> 3; 194 default: 195 break; 196 } 197 198 return -EINVAL; 199 } 200 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes); 201 202 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees, 203 bool hflip, bool vflip) 204 { 205 u32 r90, vf, hf; 206 207 switch (degrees) { 208 case 0: 209 vf = hf = r90 = 0; 210 break; 211 case 90: 212 vf = hf = 0; 213 r90 = 1; 214 break; 215 case 180: 216 vf = hf = 1; 217 r90 = 0; 218 break; 219 case 270: 220 vf = hf = r90 = 1; 221 break; 222 default: 223 return -EINVAL; 224 } 225 226 hf ^= (u32)hflip; 227 vf ^= (u32)vflip; 228 229 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf); 230 return 0; 231 } 232 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode); 233 234 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode, 235 bool hflip, bool vflip) 236 { 237 u32 r90, vf, hf; 238 239 r90 = ((u32)mode >> 2) & 0x1; 240 hf = ((u32)mode >> 1) & 0x1; 241 vf = ((u32)mode >> 0) & 0x1; 242 hf ^= (u32)hflip; 243 vf ^= (u32)vflip; 244 245 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) { 246 case IPU_ROTATE_NONE: 247 *degrees = 0; 248 break; 249 case IPU_ROTATE_90_RIGHT: 250 *degrees = 90; 251 break; 252 case IPU_ROTATE_180: 253 *degrees = 180; 254 break; 255 case IPU_ROTATE_90_LEFT: 256 *degrees = 270; 257 break; 258 default: 259 return -EINVAL; 260 } 261 262 return 0; 263 } 264 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees); 265 266 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) 267 { 268 struct ipuv3_channel *channel; 269 270 dev_dbg(ipu->dev, "%s %d\n", __func__, num); 271 272 if (num > 63) 273 return ERR_PTR(-ENODEV); 274 275 mutex_lock(&ipu->channel_lock); 276 277 list_for_each_entry(channel, &ipu->channels, list) { 278 if (channel->num == num) { 279 channel = ERR_PTR(-EBUSY); 280 goto out; 281 } 282 } 283 284 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 285 if (!channel) { 286 channel = ERR_PTR(-ENOMEM); 287 goto out; 288 } 289 290 channel->num = num; 291 channel->ipu = ipu; 292 list_add(&channel->list, &ipu->channels); 293 294 out: 295 mutex_unlock(&ipu->channel_lock); 296 297 return channel; 298 } 299 EXPORT_SYMBOL_GPL(ipu_idmac_get); 300 301 void ipu_idmac_put(struct ipuv3_channel *channel) 302 { 303 struct ipu_soc *ipu = channel->ipu; 304 305 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); 306 307 mutex_lock(&ipu->channel_lock); 308 309 list_del(&channel->list); 310 kfree(channel); 311 312 mutex_unlock(&ipu->channel_lock); 313 } 314 EXPORT_SYMBOL_GPL(ipu_idmac_put); 315 316 #define idma_mask(ch) (1 << ((ch) & 0x1f)) 317 318 /* 319 * This is an undocumented feature, a write one to a channel bit in 320 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's 321 * internal current buffer pointer so that transfers start from buffer 322 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM 323 * only says these are read-only registers). This operation is required 324 * for channel linking to work correctly, for instance video capture 325 * pipelines that carry out image rotations will fail after the first 326 * streaming unless this function is called for each channel before 327 * re-enabling the channels. 328 */ 329 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel) 330 { 331 struct ipu_soc *ipu = channel->ipu; 332 unsigned int chno = channel->num; 333 334 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno)); 335 } 336 337 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, 338 bool doublebuffer) 339 { 340 struct ipu_soc *ipu = channel->ipu; 341 unsigned long flags; 342 u32 reg; 343 344 spin_lock_irqsave(&ipu->lock, flags); 345 346 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); 347 if (doublebuffer) 348 reg |= idma_mask(channel->num); 349 else 350 reg &= ~idma_mask(channel->num); 351 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); 352 353 __ipu_idmac_reset_current_buffer(channel); 354 355 spin_unlock_irqrestore(&ipu->lock, flags); 356 } 357 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer); 358 359 static const struct { 360 int chnum; 361 u32 reg; 362 int shift; 363 } idmac_lock_en_info[] = { 364 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, }, 365 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, }, 366 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, }, 367 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, }, 368 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, }, 369 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, }, 370 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, }, 371 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, }, 372 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, }, 373 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, }, 374 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, }, 375 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, }, 376 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, }, 377 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, }, 378 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, }, 379 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, }, 380 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, }, 381 }; 382 383 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts) 384 { 385 struct ipu_soc *ipu = channel->ipu; 386 unsigned long flags; 387 u32 bursts, regval; 388 int i; 389 390 switch (num_bursts) { 391 case 0: 392 case 1: 393 bursts = 0x00; /* locking disabled */ 394 break; 395 case 2: 396 bursts = 0x01; 397 break; 398 case 4: 399 bursts = 0x02; 400 break; 401 case 8: 402 bursts = 0x03; 403 break; 404 default: 405 return -EINVAL; 406 } 407 408 /* 409 * IPUv3EX / i.MX51 has a different register layout, and on IPUv3M / 410 * i.MX53 channel arbitration locking doesn't seem to work properly. 411 * Allow enabling the lock feature on IPUv3H / i.MX6 only. 412 */ 413 if (bursts && ipu->ipu_type != IPUV3H) 414 return -EINVAL; 415 416 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) { 417 if (channel->num == idmac_lock_en_info[i].chnum) 418 break; 419 } 420 if (i >= ARRAY_SIZE(idmac_lock_en_info)) 421 return -EINVAL; 422 423 spin_lock_irqsave(&ipu->lock, flags); 424 425 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); 426 regval &= ~(0x03 << idmac_lock_en_info[i].shift); 427 regval |= (bursts << idmac_lock_en_info[i].shift); 428 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); 429 430 spin_unlock_irqrestore(&ipu->lock, flags); 431 432 return 0; 433 } 434 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable); 435 436 int ipu_module_enable(struct ipu_soc *ipu, u32 mask) 437 { 438 unsigned long lock_flags; 439 u32 val; 440 441 spin_lock_irqsave(&ipu->lock, lock_flags); 442 443 val = ipu_cm_read(ipu, IPU_DISP_GEN); 444 445 if (mask & IPU_CONF_DI0_EN) 446 val |= IPU_DI0_COUNTER_RELEASE; 447 if (mask & IPU_CONF_DI1_EN) 448 val |= IPU_DI1_COUNTER_RELEASE; 449 450 ipu_cm_write(ipu, val, IPU_DISP_GEN); 451 452 val = ipu_cm_read(ipu, IPU_CONF); 453 val |= mask; 454 ipu_cm_write(ipu, val, IPU_CONF); 455 456 spin_unlock_irqrestore(&ipu->lock, lock_flags); 457 458 return 0; 459 } 460 EXPORT_SYMBOL_GPL(ipu_module_enable); 461 462 int ipu_module_disable(struct ipu_soc *ipu, u32 mask) 463 { 464 unsigned long lock_flags; 465 u32 val; 466 467 spin_lock_irqsave(&ipu->lock, lock_flags); 468 469 val = ipu_cm_read(ipu, IPU_CONF); 470 val &= ~mask; 471 ipu_cm_write(ipu, val, IPU_CONF); 472 473 val = ipu_cm_read(ipu, IPU_DISP_GEN); 474 475 if (mask & IPU_CONF_DI0_EN) 476 val &= ~IPU_DI0_COUNTER_RELEASE; 477 if (mask & IPU_CONF_DI1_EN) 478 val &= ~IPU_DI1_COUNTER_RELEASE; 479 480 ipu_cm_write(ipu, val, IPU_DISP_GEN); 481 482 spin_unlock_irqrestore(&ipu->lock, lock_flags); 483 484 return 0; 485 } 486 EXPORT_SYMBOL_GPL(ipu_module_disable); 487 488 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel) 489 { 490 struct ipu_soc *ipu = channel->ipu; 491 unsigned int chno = channel->num; 492 493 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0; 494 } 495 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer); 496 497 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num) 498 { 499 struct ipu_soc *ipu = channel->ipu; 500 unsigned long flags; 501 u32 reg = 0; 502 503 spin_lock_irqsave(&ipu->lock, flags); 504 switch (buf_num) { 505 case 0: 506 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); 507 break; 508 case 1: 509 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); 510 break; 511 case 2: 512 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); 513 break; 514 } 515 spin_unlock_irqrestore(&ipu->lock, flags); 516 517 return ((reg & idma_mask(channel->num)) != 0); 518 } 519 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready); 520 521 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num) 522 { 523 struct ipu_soc *ipu = channel->ipu; 524 unsigned int chno = channel->num; 525 unsigned long flags; 526 527 spin_lock_irqsave(&ipu->lock, flags); 528 529 /* Mark buffer as ready. */ 530 if (buf_num == 0) 531 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); 532 else 533 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); 534 535 spin_unlock_irqrestore(&ipu->lock, flags); 536 } 537 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer); 538 539 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num) 540 { 541 struct ipu_soc *ipu = channel->ipu; 542 unsigned int chno = channel->num; 543 unsigned long flags; 544 545 spin_lock_irqsave(&ipu->lock, flags); 546 547 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */ 548 switch (buf_num) { 549 case 0: 550 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); 551 break; 552 case 1: 553 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); 554 break; 555 case 2: 556 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno)); 557 break; 558 default: 559 break; 560 } 561 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ 562 563 spin_unlock_irqrestore(&ipu->lock, flags); 564 } 565 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer); 566 567 int ipu_idmac_enable_channel(struct ipuv3_channel *channel) 568 { 569 struct ipu_soc *ipu = channel->ipu; 570 u32 val; 571 unsigned long flags; 572 573 spin_lock_irqsave(&ipu->lock, flags); 574 575 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); 576 val |= idma_mask(channel->num); 577 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); 578 579 spin_unlock_irqrestore(&ipu->lock, flags); 580 581 return 0; 582 } 583 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel); 584 585 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno) 586 { 587 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno)); 588 } 589 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy); 590 591 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms) 592 { 593 struct ipu_soc *ipu = channel->ipu; 594 unsigned long timeout; 595 596 timeout = jiffies + msecs_to_jiffies(ms); 597 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & 598 idma_mask(channel->num)) { 599 if (time_after(jiffies, timeout)) 600 return -ETIMEDOUT; 601 cpu_relax(); 602 } 603 604 return 0; 605 } 606 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy); 607 608 int ipu_idmac_disable_channel(struct ipuv3_channel *channel) 609 { 610 struct ipu_soc *ipu = channel->ipu; 611 u32 val; 612 unsigned long flags; 613 614 spin_lock_irqsave(&ipu->lock, flags); 615 616 /* Disable DMA channel(s) */ 617 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); 618 val &= ~idma_mask(channel->num); 619 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); 620 621 __ipu_idmac_reset_current_buffer(channel); 622 623 /* Set channel buffers NOT to be ready */ 624 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ 625 626 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & 627 idma_mask(channel->num)) { 628 ipu_cm_write(ipu, idma_mask(channel->num), 629 IPU_CHA_BUF0_RDY(channel->num)); 630 } 631 632 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & 633 idma_mask(channel->num)) { 634 ipu_cm_write(ipu, idma_mask(channel->num), 635 IPU_CHA_BUF1_RDY(channel->num)); 636 } 637 638 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ 639 640 /* Reset the double buffer */ 641 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); 642 val &= ~idma_mask(channel->num); 643 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); 644 645 spin_unlock_irqrestore(&ipu->lock, flags); 646 647 return 0; 648 } 649 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel); 650 651 /* 652 * The imx6 rev. D TRM says that enabling the WM feature will increase 653 * a channel's priority. Refer to Table 36-8 Calculated priority value. 654 * The sub-module that is the sink or source for the channel must enable 655 * watermark signal for this to take effect (SMFC_WM for instance). 656 */ 657 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable) 658 { 659 struct ipu_soc *ipu = channel->ipu; 660 unsigned long flags; 661 u32 val; 662 663 spin_lock_irqsave(&ipu->lock, flags); 664 665 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); 666 if (enable) 667 val |= 1 << (channel->num % 32); 668 else 669 val &= ~(1 << (channel->num % 32)); 670 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); 671 672 spin_unlock_irqrestore(&ipu->lock, flags); 673 } 674 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark); 675 676 static int ipu_memory_reset(struct ipu_soc *ipu) 677 { 678 unsigned long timeout; 679 680 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); 681 682 timeout = jiffies + msecs_to_jiffies(1000); 683 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { 684 if (time_after(jiffies, timeout)) 685 return -ETIME; 686 cpu_relax(); 687 } 688 689 return 0; 690 } 691 692 /* 693 * Set the source mux for the given CSI. Selects either parallel or 694 * MIPI CSI2 sources. 695 */ 696 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2) 697 { 698 unsigned long flags; 699 u32 val, mask; 700 701 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE : 702 IPU_CONF_CSI0_DATA_SOURCE; 703 704 spin_lock_irqsave(&ipu->lock, flags); 705 706 val = ipu_cm_read(ipu, IPU_CONF); 707 if (mipi_csi2) 708 val |= mask; 709 else 710 val &= ~mask; 711 ipu_cm_write(ipu, val, IPU_CONF); 712 713 spin_unlock_irqrestore(&ipu->lock, flags); 714 } 715 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux); 716 717 /* 718 * Set the source mux for the IC. Selects either CSI[01] or the VDI. 719 */ 720 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) 721 { 722 unsigned long flags; 723 u32 val; 724 725 spin_lock_irqsave(&ipu->lock, flags); 726 727 val = ipu_cm_read(ipu, IPU_CONF); 728 if (vdi) 729 val |= IPU_CONF_IC_INPUT; 730 else 731 val &= ~IPU_CONF_IC_INPUT; 732 733 if (csi_id == 1) 734 val |= IPU_CONF_CSI_SEL; 735 else 736 val &= ~IPU_CONF_CSI_SEL; 737 738 ipu_cm_write(ipu, val, IPU_CONF); 739 740 spin_unlock_irqrestore(&ipu->lock, flags); 741 } 742 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux); 743 744 745 /* Frame Synchronization Unit Channel Linking */ 746 747 struct fsu_link_reg_info { 748 int chno; 749 u32 reg; 750 u32 mask; 751 u32 val; 752 }; 753 754 struct fsu_link_info { 755 struct fsu_link_reg_info src; 756 struct fsu_link_reg_info sink; 757 }; 758 759 static const struct fsu_link_info fsu_link_info[] = { 760 { 761 .src = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2, 762 FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC }, 763 .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1, 764 FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC }, 765 }, { 766 .src = { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2, 767 FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF }, 768 .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1, 769 FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF }, 770 }, { 771 .src = { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2, 772 FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP }, 773 .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1, 774 FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP }, 775 }, { 776 .src = { IPUV3_CHANNEL_CSI_DIRECT, 0 }, 777 .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1, 778 FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT }, 779 }, 780 }; 781 782 static const struct fsu_link_info *find_fsu_link_info(int src, int sink) 783 { 784 int i; 785 786 for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) { 787 if (src == fsu_link_info[i].src.chno && 788 sink == fsu_link_info[i].sink.chno) 789 return &fsu_link_info[i]; 790 } 791 792 return NULL; 793 } 794 795 /* 796 * Links a source channel to a sink channel in the FSU. 797 */ 798 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch) 799 { 800 const struct fsu_link_info *link; 801 u32 src_reg, sink_reg; 802 unsigned long flags; 803 804 link = find_fsu_link_info(src_ch, sink_ch); 805 if (!link) 806 return -EINVAL; 807 808 spin_lock_irqsave(&ipu->lock, flags); 809 810 if (link->src.mask) { 811 src_reg = ipu_cm_read(ipu, link->src.reg); 812 src_reg &= ~link->src.mask; 813 src_reg |= link->src.val; 814 ipu_cm_write(ipu, src_reg, link->src.reg); 815 } 816 817 if (link->sink.mask) { 818 sink_reg = ipu_cm_read(ipu, link->sink.reg); 819 sink_reg &= ~link->sink.mask; 820 sink_reg |= link->sink.val; 821 ipu_cm_write(ipu, sink_reg, link->sink.reg); 822 } 823 824 spin_unlock_irqrestore(&ipu->lock, flags); 825 return 0; 826 } 827 EXPORT_SYMBOL_GPL(ipu_fsu_link); 828 829 /* 830 * Unlinks source and sink channels in the FSU. 831 */ 832 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch) 833 { 834 const struct fsu_link_info *link; 835 u32 src_reg, sink_reg; 836 unsigned long flags; 837 838 link = find_fsu_link_info(src_ch, sink_ch); 839 if (!link) 840 return -EINVAL; 841 842 spin_lock_irqsave(&ipu->lock, flags); 843 844 if (link->src.mask) { 845 src_reg = ipu_cm_read(ipu, link->src.reg); 846 src_reg &= ~link->src.mask; 847 ipu_cm_write(ipu, src_reg, link->src.reg); 848 } 849 850 if (link->sink.mask) { 851 sink_reg = ipu_cm_read(ipu, link->sink.reg); 852 sink_reg &= ~link->sink.mask; 853 ipu_cm_write(ipu, sink_reg, link->sink.reg); 854 } 855 856 spin_unlock_irqrestore(&ipu->lock, flags); 857 return 0; 858 } 859 EXPORT_SYMBOL_GPL(ipu_fsu_unlink); 860 861 /* Link IDMAC channels in the FSU */ 862 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink) 863 { 864 return ipu_fsu_link(src->ipu, src->num, sink->num); 865 } 866 EXPORT_SYMBOL_GPL(ipu_idmac_link); 867 868 /* Unlink IDMAC channels in the FSU */ 869 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink) 870 { 871 return ipu_fsu_unlink(src->ipu, src->num, sink->num); 872 } 873 EXPORT_SYMBOL_GPL(ipu_idmac_unlink); 874 875 struct ipu_devtype { 876 const char *name; 877 unsigned long cm_ofs; 878 unsigned long cpmem_ofs; 879 unsigned long srm_ofs; 880 unsigned long tpm_ofs; 881 unsigned long csi0_ofs; 882 unsigned long csi1_ofs; 883 unsigned long ic_ofs; 884 unsigned long disp0_ofs; 885 unsigned long disp1_ofs; 886 unsigned long dc_tmpl_ofs; 887 unsigned long vdi_ofs; 888 enum ipuv3_type type; 889 }; 890 891 static struct ipu_devtype ipu_type_imx51 = { 892 .name = "IPUv3EX", 893 .cm_ofs = 0x1e000000, 894 .cpmem_ofs = 0x1f000000, 895 .srm_ofs = 0x1f040000, 896 .tpm_ofs = 0x1f060000, 897 .csi0_ofs = 0x1f030000, 898 .csi1_ofs = 0x1f038000, 899 .ic_ofs = 0x1e020000, 900 .disp0_ofs = 0x1e040000, 901 .disp1_ofs = 0x1e048000, 902 .dc_tmpl_ofs = 0x1f080000, 903 .vdi_ofs = 0x1e068000, 904 .type = IPUV3EX, 905 }; 906 907 static struct ipu_devtype ipu_type_imx53 = { 908 .name = "IPUv3M", 909 .cm_ofs = 0x06000000, 910 .cpmem_ofs = 0x07000000, 911 .srm_ofs = 0x07040000, 912 .tpm_ofs = 0x07060000, 913 .csi0_ofs = 0x07030000, 914 .csi1_ofs = 0x07038000, 915 .ic_ofs = 0x06020000, 916 .disp0_ofs = 0x06040000, 917 .disp1_ofs = 0x06048000, 918 .dc_tmpl_ofs = 0x07080000, 919 .vdi_ofs = 0x06068000, 920 .type = IPUV3M, 921 }; 922 923 static struct ipu_devtype ipu_type_imx6q = { 924 .name = "IPUv3H", 925 .cm_ofs = 0x00200000, 926 .cpmem_ofs = 0x00300000, 927 .srm_ofs = 0x00340000, 928 .tpm_ofs = 0x00360000, 929 .csi0_ofs = 0x00230000, 930 .csi1_ofs = 0x00238000, 931 .ic_ofs = 0x00220000, 932 .disp0_ofs = 0x00240000, 933 .disp1_ofs = 0x00248000, 934 .dc_tmpl_ofs = 0x00380000, 935 .vdi_ofs = 0x00268000, 936 .type = IPUV3H, 937 }; 938 939 static const struct of_device_id imx_ipu_dt_ids[] = { 940 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, }, 941 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, }, 942 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, }, 943 { .compatible = "fsl,imx6qp-ipu", .data = &ipu_type_imx6q, }, 944 { /* sentinel */ } 945 }; 946 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids); 947 948 static int ipu_submodules_init(struct ipu_soc *ipu, 949 struct platform_device *pdev, unsigned long ipu_base, 950 struct clk *ipu_clk) 951 { 952 char *unit; 953 int ret; 954 struct device *dev = &pdev->dev; 955 const struct ipu_devtype *devtype = ipu->devtype; 956 957 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); 958 if (ret) { 959 unit = "cpmem"; 960 goto err_cpmem; 961 } 962 963 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, 964 IPU_CONF_CSI0_EN, ipu_clk); 965 if (ret) { 966 unit = "csi0"; 967 goto err_csi_0; 968 } 969 970 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, 971 IPU_CONF_CSI1_EN, ipu_clk); 972 if (ret) { 973 unit = "csi1"; 974 goto err_csi_1; 975 } 976 977 ret = ipu_ic_init(ipu, dev, 978 ipu_base + devtype->ic_ofs, 979 ipu_base + devtype->tpm_ofs); 980 if (ret) { 981 unit = "ic"; 982 goto err_ic; 983 } 984 985 ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs, 986 IPU_CONF_VDI_EN | IPU_CONF_ISP_EN | 987 IPU_CONF_IC_INPUT); 988 if (ret) { 989 unit = "vdi"; 990 goto err_vdi; 991 } 992 993 ret = ipu_image_convert_init(ipu, dev); 994 if (ret) { 995 unit = "image_convert"; 996 goto err_image_convert; 997 } 998 999 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, 1000 IPU_CONF_DI0_EN, ipu_clk); 1001 if (ret) { 1002 unit = "di0"; 1003 goto err_di_0; 1004 } 1005 1006 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, 1007 IPU_CONF_DI1_EN, ipu_clk); 1008 if (ret) { 1009 unit = "di1"; 1010 goto err_di_1; 1011 } 1012 1013 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + 1014 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs); 1015 if (ret) { 1016 unit = "dc_template"; 1017 goto err_dc; 1018 } 1019 1020 ret = ipu_dmfc_init(ipu, dev, ipu_base + 1021 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk); 1022 if (ret) { 1023 unit = "dmfc"; 1024 goto err_dmfc; 1025 } 1026 1027 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); 1028 if (ret) { 1029 unit = "dp"; 1030 goto err_dp; 1031 } 1032 1033 ret = ipu_smfc_init(ipu, dev, ipu_base + 1034 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS); 1035 if (ret) { 1036 unit = "smfc"; 1037 goto err_smfc; 1038 } 1039 1040 return 0; 1041 1042 err_smfc: 1043 ipu_dp_exit(ipu); 1044 err_dp: 1045 ipu_dmfc_exit(ipu); 1046 err_dmfc: 1047 ipu_dc_exit(ipu); 1048 err_dc: 1049 ipu_di_exit(ipu, 1); 1050 err_di_1: 1051 ipu_di_exit(ipu, 0); 1052 err_di_0: 1053 ipu_image_convert_exit(ipu); 1054 err_image_convert: 1055 ipu_vdi_exit(ipu); 1056 err_vdi: 1057 ipu_ic_exit(ipu); 1058 err_ic: 1059 ipu_csi_exit(ipu, 1); 1060 err_csi_1: 1061 ipu_csi_exit(ipu, 0); 1062 err_csi_0: 1063 ipu_cpmem_exit(ipu); 1064 err_cpmem: 1065 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret); 1066 return ret; 1067 } 1068 1069 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) 1070 { 1071 unsigned long status; 1072 int i, bit, irq; 1073 1074 for (i = 0; i < num_regs; i++) { 1075 1076 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); 1077 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); 1078 1079 for_each_set_bit(bit, &status, 32) { 1080 irq = irq_linear_revmap(ipu->domain, 1081 regs[i] * 32 + bit); 1082 if (irq) 1083 generic_handle_irq(irq); 1084 } 1085 } 1086 } 1087 1088 static void ipu_irq_handler(struct irq_desc *desc) 1089 { 1090 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); 1091 struct irq_chip *chip = irq_desc_get_chip(desc); 1092 static const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14}; 1093 1094 chained_irq_enter(chip, desc); 1095 1096 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); 1097 1098 chained_irq_exit(chip, desc); 1099 } 1100 1101 static void ipu_err_irq_handler(struct irq_desc *desc) 1102 { 1103 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); 1104 struct irq_chip *chip = irq_desc_get_chip(desc); 1105 static const int int_reg[] = { 4, 5, 8, 9}; 1106 1107 chained_irq_enter(chip, desc); 1108 1109 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); 1110 1111 chained_irq_exit(chip, desc); 1112 } 1113 1114 int ipu_map_irq(struct ipu_soc *ipu, int irq) 1115 { 1116 int virq; 1117 1118 virq = irq_linear_revmap(ipu->domain, irq); 1119 if (!virq) 1120 virq = irq_create_mapping(ipu->domain, irq); 1121 1122 return virq; 1123 } 1124 EXPORT_SYMBOL_GPL(ipu_map_irq); 1125 1126 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, 1127 enum ipu_channel_irq irq_type) 1128 { 1129 return ipu_map_irq(ipu, irq_type + channel->num); 1130 } 1131 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq); 1132 1133 static void ipu_submodules_exit(struct ipu_soc *ipu) 1134 { 1135 ipu_smfc_exit(ipu); 1136 ipu_dp_exit(ipu); 1137 ipu_dmfc_exit(ipu); 1138 ipu_dc_exit(ipu); 1139 ipu_di_exit(ipu, 1); 1140 ipu_di_exit(ipu, 0); 1141 ipu_image_convert_exit(ipu); 1142 ipu_vdi_exit(ipu); 1143 ipu_ic_exit(ipu); 1144 ipu_csi_exit(ipu, 1); 1145 ipu_csi_exit(ipu, 0); 1146 ipu_cpmem_exit(ipu); 1147 } 1148 1149 static int platform_remove_devices_fn(struct device *dev, void *unused) 1150 { 1151 struct platform_device *pdev = to_platform_device(dev); 1152 1153 platform_device_unregister(pdev); 1154 1155 return 0; 1156 } 1157 1158 static void platform_device_unregister_children(struct platform_device *pdev) 1159 { 1160 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn); 1161 } 1162 1163 struct ipu_platform_reg { 1164 struct ipu_client_platformdata pdata; 1165 const char *name; 1166 }; 1167 1168 /* These must be in the order of the corresponding device tree port nodes */ 1169 static struct ipu_platform_reg client_reg[] = { 1170 { 1171 .pdata = { 1172 .csi = 0, 1173 .dma[0] = IPUV3_CHANNEL_CSI0, 1174 .dma[1] = -EINVAL, 1175 }, 1176 .name = "imx-ipuv3-csi", 1177 }, { 1178 .pdata = { 1179 .csi = 1, 1180 .dma[0] = IPUV3_CHANNEL_CSI1, 1181 .dma[1] = -EINVAL, 1182 }, 1183 .name = "imx-ipuv3-csi", 1184 }, { 1185 .pdata = { 1186 .di = 0, 1187 .dc = 5, 1188 .dp = IPU_DP_FLOW_SYNC_BG, 1189 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC, 1190 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC, 1191 }, 1192 .name = "imx-ipuv3-crtc", 1193 }, { 1194 .pdata = { 1195 .di = 1, 1196 .dc = 1, 1197 .dp = -EINVAL, 1198 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC, 1199 .dma[1] = -EINVAL, 1200 }, 1201 .name = "imx-ipuv3-crtc", 1202 }, 1203 }; 1204 1205 static DEFINE_MUTEX(ipu_client_id_mutex); 1206 static int ipu_client_id; 1207 1208 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) 1209 { 1210 struct device *dev = ipu->dev; 1211 unsigned i; 1212 int id, ret; 1213 1214 mutex_lock(&ipu_client_id_mutex); 1215 id = ipu_client_id; 1216 ipu_client_id += ARRAY_SIZE(client_reg); 1217 mutex_unlock(&ipu_client_id_mutex); 1218 1219 for (i = 0; i < ARRAY_SIZE(client_reg); i++) { 1220 struct ipu_platform_reg *reg = &client_reg[i]; 1221 struct platform_device *pdev; 1222 struct device_node *of_node; 1223 1224 /* Associate subdevice with the corresponding port node */ 1225 of_node = of_graph_get_port_by_id(dev->of_node, i); 1226 if (!of_node) { 1227 dev_info(dev, 1228 "no port@%d node in %pOF, not using %s%d\n", 1229 i, dev->of_node, 1230 (i / 2) ? "DI" : "CSI", i % 2); 1231 continue; 1232 } 1233 1234 pdev = platform_device_alloc(reg->name, id++); 1235 if (!pdev) { 1236 ret = -ENOMEM; 1237 goto err_register; 1238 } 1239 1240 pdev->dev.parent = dev; 1241 1242 reg->pdata.of_node = of_node; 1243 ret = platform_device_add_data(pdev, ®->pdata, 1244 sizeof(reg->pdata)); 1245 if (!ret) 1246 ret = platform_device_add(pdev); 1247 if (ret) { 1248 platform_device_put(pdev); 1249 goto err_register; 1250 } 1251 } 1252 1253 return 0; 1254 1255 err_register: 1256 platform_device_unregister_children(to_platform_device(dev)); 1257 1258 return ret; 1259 } 1260 1261 1262 static int ipu_irq_init(struct ipu_soc *ipu) 1263 { 1264 struct irq_chip_generic *gc; 1265 struct irq_chip_type *ct; 1266 unsigned long unused[IPU_NUM_IRQS / 32] = { 1267 0x400100d0, 0xffe000fd, 1268 0x400100d0, 0xffe000fd, 1269 0x400100d0, 0xffe000fd, 1270 0x4077ffff, 0xffe7e1fd, 1271 0x23fffffe, 0x8880fff0, 1272 0xf98fe7d0, 0xfff81fff, 1273 0x400100d0, 0xffe000fd, 1274 0x00000000, 1275 }; 1276 int ret, i; 1277 1278 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, 1279 &irq_generic_chip_ops, ipu); 1280 if (!ipu->domain) { 1281 dev_err(ipu->dev, "failed to add irq domain\n"); 1282 return -ENODEV; 1283 } 1284 1285 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", 1286 handle_level_irq, 0, 0, 0); 1287 if (ret < 0) { 1288 dev_err(ipu->dev, "failed to alloc generic irq chips\n"); 1289 irq_domain_remove(ipu->domain); 1290 return ret; 1291 } 1292 1293 /* Mask and clear all interrupts */ 1294 for (i = 0; i < IPU_NUM_IRQS; i += 32) { 1295 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32)); 1296 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32)); 1297 } 1298 1299 for (i = 0; i < IPU_NUM_IRQS; i += 32) { 1300 gc = irq_get_domain_generic_chip(ipu->domain, i); 1301 gc->reg_base = ipu->cm_reg; 1302 gc->unused = unused[i / 32]; 1303 ct = gc->chip_types; 1304 ct->chip.irq_ack = irq_gc_ack_set_bit; 1305 ct->chip.irq_mask = irq_gc_mask_clr_bit; 1306 ct->chip.irq_unmask = irq_gc_mask_set_bit; 1307 ct->regs.ack = IPU_INT_STAT(i / 32); 1308 ct->regs.mask = IPU_INT_CTRL(i / 32); 1309 } 1310 1311 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu); 1312 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler, 1313 ipu); 1314 1315 return 0; 1316 } 1317 1318 static void ipu_irq_exit(struct ipu_soc *ipu) 1319 { 1320 int i, irq; 1321 1322 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL); 1323 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL); 1324 1325 /* TODO: remove irq_domain_generic_chips */ 1326 1327 for (i = 0; i < IPU_NUM_IRQS; i++) { 1328 irq = irq_linear_revmap(ipu->domain, i); 1329 if (irq) 1330 irq_dispose_mapping(irq); 1331 } 1332 1333 irq_domain_remove(ipu->domain); 1334 } 1335 1336 void ipu_dump(struct ipu_soc *ipu) 1337 { 1338 int i; 1339 1340 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", 1341 ipu_cm_read(ipu, IPU_CONF)); 1342 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", 1343 ipu_idmac_read(ipu, IDMAC_CONF)); 1344 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n", 1345 ipu_idmac_read(ipu, IDMAC_CHA_EN(0))); 1346 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n", 1347 ipu_idmac_read(ipu, IDMAC_CHA_EN(32))); 1348 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n", 1349 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0))); 1350 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n", 1351 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32))); 1352 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n", 1353 ipu_idmac_read(ipu, IDMAC_BAND_EN(0))); 1354 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n", 1355 ipu_idmac_read(ipu, IDMAC_BAND_EN(32))); 1356 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", 1357 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0))); 1358 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", 1359 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32))); 1360 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n", 1361 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1)); 1362 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n", 1363 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2)); 1364 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n", 1365 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3)); 1366 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n", 1367 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1)); 1368 for (i = 0; i < 15; i++) 1369 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i, 1370 ipu_cm_read(ipu, IPU_INT_CTRL(i))); 1371 } 1372 EXPORT_SYMBOL_GPL(ipu_dump); 1373 1374 static int ipu_probe(struct platform_device *pdev) 1375 { 1376 struct device_node *np = pdev->dev.of_node; 1377 struct ipu_soc *ipu; 1378 struct resource *res; 1379 unsigned long ipu_base; 1380 int ret, irq_sync, irq_err; 1381 const struct ipu_devtype *devtype; 1382 1383 devtype = of_device_get_match_data(&pdev->dev); 1384 if (!devtype) 1385 return -EINVAL; 1386 1387 irq_sync = platform_get_irq(pdev, 0); 1388 irq_err = platform_get_irq(pdev, 1); 1389 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1390 1391 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n", 1392 irq_sync, irq_err); 1393 1394 if (!res || irq_sync < 0 || irq_err < 0) 1395 return -ENODEV; 1396 1397 ipu_base = res->start; 1398 1399 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); 1400 if (!ipu) 1401 return -ENODEV; 1402 1403 ipu->id = of_alias_get_id(np, "ipu"); 1404 1405 if (of_device_is_compatible(np, "fsl,imx6qp-ipu") && 1406 IS_ENABLED(CONFIG_DRM)) { 1407 ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev, 1408 "fsl,prg", ipu->id); 1409 if (!ipu->prg_priv) 1410 return -EPROBE_DEFER; 1411 } 1412 1413 ipu->devtype = devtype; 1414 ipu->ipu_type = devtype->type; 1415 1416 spin_lock_init(&ipu->lock); 1417 mutex_init(&ipu->channel_lock); 1418 INIT_LIST_HEAD(&ipu->channels); 1419 1420 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n", 1421 ipu_base + devtype->cm_ofs); 1422 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n", 1423 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS); 1424 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n", 1425 ipu_base + devtype->cpmem_ofs); 1426 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n", 1427 ipu_base + devtype->csi0_ofs); 1428 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n", 1429 ipu_base + devtype->csi1_ofs); 1430 dev_dbg(&pdev->dev, "ic: 0x%08lx\n", 1431 ipu_base + devtype->ic_ofs); 1432 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n", 1433 ipu_base + devtype->disp0_ofs); 1434 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n", 1435 ipu_base + devtype->disp1_ofs); 1436 dev_dbg(&pdev->dev, "srm: 0x%08lx\n", 1437 ipu_base + devtype->srm_ofs); 1438 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n", 1439 ipu_base + devtype->tpm_ofs); 1440 dev_dbg(&pdev->dev, "dc: 0x%08lx\n", 1441 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS); 1442 dev_dbg(&pdev->dev, "ic: 0x%08lx\n", 1443 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS); 1444 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n", 1445 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS); 1446 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n", 1447 ipu_base + devtype->vdi_ofs); 1448 1449 ipu->cm_reg = devm_ioremap(&pdev->dev, 1450 ipu_base + devtype->cm_ofs, PAGE_SIZE); 1451 ipu->idmac_reg = devm_ioremap(&pdev->dev, 1452 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS, 1453 PAGE_SIZE); 1454 1455 if (!ipu->cm_reg || !ipu->idmac_reg) 1456 return -ENOMEM; 1457 1458 ipu->clk = devm_clk_get(&pdev->dev, "bus"); 1459 if (IS_ERR(ipu->clk)) { 1460 ret = PTR_ERR(ipu->clk); 1461 dev_err(&pdev->dev, "clk_get failed with %d", ret); 1462 return ret; 1463 } 1464 1465 platform_set_drvdata(pdev, ipu); 1466 1467 ret = clk_prepare_enable(ipu->clk); 1468 if (ret) { 1469 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); 1470 return ret; 1471 } 1472 1473 ipu->dev = &pdev->dev; 1474 ipu->irq_sync = irq_sync; 1475 ipu->irq_err = irq_err; 1476 1477 ret = device_reset(&pdev->dev); 1478 if (ret) { 1479 dev_err(&pdev->dev, "failed to reset: %d\n", ret); 1480 goto out_failed_reset; 1481 } 1482 ret = ipu_memory_reset(ipu); 1483 if (ret) 1484 goto out_failed_reset; 1485 1486 ret = ipu_irq_init(ipu); 1487 if (ret) 1488 goto out_failed_irq; 1489 1490 /* Set MCU_T to divide MCU access window into 2 */ 1491 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), 1492 IPU_DISP_GEN); 1493 1494 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); 1495 if (ret) 1496 goto failed_submodules_init; 1497 1498 ret = ipu_add_client_devices(ipu, ipu_base); 1499 if (ret) { 1500 dev_err(&pdev->dev, "adding client devices failed with %d\n", 1501 ret); 1502 goto failed_add_clients; 1503 } 1504 1505 dev_info(&pdev->dev, "%s probed\n", devtype->name); 1506 1507 return 0; 1508 1509 failed_add_clients: 1510 ipu_submodules_exit(ipu); 1511 failed_submodules_init: 1512 ipu_irq_exit(ipu); 1513 out_failed_irq: 1514 out_failed_reset: 1515 clk_disable_unprepare(ipu->clk); 1516 return ret; 1517 } 1518 1519 static int ipu_remove(struct platform_device *pdev) 1520 { 1521 struct ipu_soc *ipu = platform_get_drvdata(pdev); 1522 1523 platform_device_unregister_children(pdev); 1524 ipu_submodules_exit(ipu); 1525 ipu_irq_exit(ipu); 1526 1527 clk_disable_unprepare(ipu->clk); 1528 1529 return 0; 1530 } 1531 1532 static struct platform_driver imx_ipu_driver = { 1533 .driver = { 1534 .name = "imx-ipuv3", 1535 .of_match_table = imx_ipu_dt_ids, 1536 }, 1537 .probe = ipu_probe, 1538 .remove = ipu_remove, 1539 }; 1540 1541 static struct platform_driver * const drivers[] = { 1542 #if IS_ENABLED(CONFIG_DRM) 1543 &ipu_pre_drv, 1544 &ipu_prg_drv, 1545 #endif 1546 &imx_ipu_driver, 1547 }; 1548 1549 static int __init imx_ipu_init(void) 1550 { 1551 return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 1552 } 1553 module_init(imx_ipu_init); 1554 1555 static void __exit imx_ipu_exit(void) 1556 { 1557 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 1558 } 1559 module_exit(imx_ipu_exit); 1560 1561 MODULE_ALIAS("platform:imx-ipuv3"); 1562 MODULE_DESCRIPTION("i.MX IPU v3 driver"); 1563 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 1564 MODULE_LICENSE("GPL"); 1565