1 /* 2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> 3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 */ 15 #include <linux/module.h> 16 #include <linux/export.h> 17 #include <linux/types.h> 18 #include <linux/reset.h> 19 #include <linux/platform_device.h> 20 #include <linux/err.h> 21 #include <linux/spinlock.h> 22 #include <linux/delay.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/clk.h> 26 #include <linux/list.h> 27 #include <linux/irq.h> 28 #include <linux/irqchip/chained_irq.h> 29 #include <linux/irqdomain.h> 30 #include <linux/of_device.h> 31 #include <linux/of_graph.h> 32 33 #include <drm/drm_fourcc.h> 34 35 #include <video/imx-ipu-v3.h> 36 #include "ipu-prv.h" 37 38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) 39 { 40 return readl(ipu->cm_reg + offset); 41 } 42 43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) 44 { 45 writel(value, ipu->cm_reg + offset); 46 } 47 48 void ipu_srm_dp_sync_update(struct ipu_soc *ipu) 49 { 50 u32 val; 51 52 val = ipu_cm_read(ipu, IPU_SRM_PRI2); 53 val |= 0x8; 54 ipu_cm_write(ipu, val, IPU_SRM_PRI2); 55 } 56 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update); 57 58 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc) 59 { 60 switch (drm_fourcc) { 61 case DRM_FORMAT_ARGB1555: 62 case DRM_FORMAT_ABGR1555: 63 case DRM_FORMAT_RGBA5551: 64 case DRM_FORMAT_BGRA5551: 65 case DRM_FORMAT_RGB565: 66 case DRM_FORMAT_BGR565: 67 case DRM_FORMAT_RGB888: 68 case DRM_FORMAT_BGR888: 69 case DRM_FORMAT_ARGB4444: 70 case DRM_FORMAT_XRGB8888: 71 case DRM_FORMAT_XBGR8888: 72 case DRM_FORMAT_RGBX8888: 73 case DRM_FORMAT_BGRX8888: 74 case DRM_FORMAT_ARGB8888: 75 case DRM_FORMAT_ABGR8888: 76 case DRM_FORMAT_RGBA8888: 77 case DRM_FORMAT_BGRA8888: 78 return IPUV3_COLORSPACE_RGB; 79 case DRM_FORMAT_YUYV: 80 case DRM_FORMAT_UYVY: 81 case DRM_FORMAT_YUV420: 82 case DRM_FORMAT_YVU420: 83 case DRM_FORMAT_YUV422: 84 case DRM_FORMAT_YVU422: 85 case DRM_FORMAT_NV12: 86 case DRM_FORMAT_NV21: 87 case DRM_FORMAT_NV16: 88 case DRM_FORMAT_NV61: 89 return IPUV3_COLORSPACE_YUV; 90 default: 91 return IPUV3_COLORSPACE_UNKNOWN; 92 } 93 } 94 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace); 95 96 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat) 97 { 98 switch (pixelformat) { 99 case V4L2_PIX_FMT_YUV420: 100 case V4L2_PIX_FMT_YVU420: 101 case V4L2_PIX_FMT_YUV422P: 102 case V4L2_PIX_FMT_UYVY: 103 case V4L2_PIX_FMT_YUYV: 104 case V4L2_PIX_FMT_NV12: 105 case V4L2_PIX_FMT_NV21: 106 case V4L2_PIX_FMT_NV16: 107 case V4L2_PIX_FMT_NV61: 108 return IPUV3_COLORSPACE_YUV; 109 case V4L2_PIX_FMT_RGB32: 110 case V4L2_PIX_FMT_BGR32: 111 case V4L2_PIX_FMT_RGB24: 112 case V4L2_PIX_FMT_BGR24: 113 case V4L2_PIX_FMT_RGB565: 114 return IPUV3_COLORSPACE_RGB; 115 default: 116 return IPUV3_COLORSPACE_UNKNOWN; 117 } 118 } 119 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace); 120 121 bool ipu_pixelformat_is_planar(u32 pixelformat) 122 { 123 switch (pixelformat) { 124 case V4L2_PIX_FMT_YUV420: 125 case V4L2_PIX_FMT_YVU420: 126 case V4L2_PIX_FMT_YUV422P: 127 case V4L2_PIX_FMT_NV12: 128 case V4L2_PIX_FMT_NV21: 129 case V4L2_PIX_FMT_NV16: 130 case V4L2_PIX_FMT_NV61: 131 return true; 132 } 133 134 return false; 135 } 136 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar); 137 138 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code) 139 { 140 switch (mbus_code & 0xf000) { 141 case 0x1000: 142 return IPUV3_COLORSPACE_RGB; 143 case 0x2000: 144 return IPUV3_COLORSPACE_YUV; 145 default: 146 return IPUV3_COLORSPACE_UNKNOWN; 147 } 148 } 149 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace); 150 151 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat) 152 { 153 switch (pixelformat) { 154 case V4L2_PIX_FMT_YUV420: 155 case V4L2_PIX_FMT_YVU420: 156 case V4L2_PIX_FMT_YUV422P: 157 case V4L2_PIX_FMT_NV12: 158 case V4L2_PIX_FMT_NV21: 159 case V4L2_PIX_FMT_NV16: 160 case V4L2_PIX_FMT_NV61: 161 /* 162 * for the planar YUV formats, the stride passed to 163 * cpmem must be the stride in bytes of the Y plane. 164 * And all the planar YUV formats have an 8-bit 165 * Y component. 166 */ 167 return (8 * pixel_stride) >> 3; 168 case V4L2_PIX_FMT_RGB565: 169 case V4L2_PIX_FMT_YUYV: 170 case V4L2_PIX_FMT_UYVY: 171 return (16 * pixel_stride) >> 3; 172 case V4L2_PIX_FMT_BGR24: 173 case V4L2_PIX_FMT_RGB24: 174 return (24 * pixel_stride) >> 3; 175 case V4L2_PIX_FMT_BGR32: 176 case V4L2_PIX_FMT_RGB32: 177 return (32 * pixel_stride) >> 3; 178 default: 179 break; 180 } 181 182 return -EINVAL; 183 } 184 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes); 185 186 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees, 187 bool hflip, bool vflip) 188 { 189 u32 r90, vf, hf; 190 191 switch (degrees) { 192 case 0: 193 vf = hf = r90 = 0; 194 break; 195 case 90: 196 vf = hf = 0; 197 r90 = 1; 198 break; 199 case 180: 200 vf = hf = 1; 201 r90 = 0; 202 break; 203 case 270: 204 vf = hf = r90 = 1; 205 break; 206 default: 207 return -EINVAL; 208 } 209 210 hf ^= (u32)hflip; 211 vf ^= (u32)vflip; 212 213 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf); 214 return 0; 215 } 216 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode); 217 218 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode, 219 bool hflip, bool vflip) 220 { 221 u32 r90, vf, hf; 222 223 r90 = ((u32)mode >> 2) & 0x1; 224 hf = ((u32)mode >> 1) & 0x1; 225 vf = ((u32)mode >> 0) & 0x1; 226 hf ^= (u32)hflip; 227 vf ^= (u32)vflip; 228 229 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) { 230 case IPU_ROTATE_NONE: 231 *degrees = 0; 232 break; 233 case IPU_ROTATE_90_RIGHT: 234 *degrees = 90; 235 break; 236 case IPU_ROTATE_180: 237 *degrees = 180; 238 break; 239 case IPU_ROTATE_90_LEFT: 240 *degrees = 270; 241 break; 242 default: 243 return -EINVAL; 244 } 245 246 return 0; 247 } 248 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees); 249 250 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) 251 { 252 struct ipuv3_channel *channel; 253 254 dev_dbg(ipu->dev, "%s %d\n", __func__, num); 255 256 if (num > 63) 257 return ERR_PTR(-ENODEV); 258 259 mutex_lock(&ipu->channel_lock); 260 261 channel = &ipu->channel[num]; 262 263 if (channel->busy) { 264 channel = ERR_PTR(-EBUSY); 265 goto out; 266 } 267 268 channel->busy = true; 269 channel->num = num; 270 271 out: 272 mutex_unlock(&ipu->channel_lock); 273 274 return channel; 275 } 276 EXPORT_SYMBOL_GPL(ipu_idmac_get); 277 278 void ipu_idmac_put(struct ipuv3_channel *channel) 279 { 280 struct ipu_soc *ipu = channel->ipu; 281 282 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); 283 284 mutex_lock(&ipu->channel_lock); 285 286 channel->busy = false; 287 288 mutex_unlock(&ipu->channel_lock); 289 } 290 EXPORT_SYMBOL_GPL(ipu_idmac_put); 291 292 #define idma_mask(ch) (1 << ((ch) & 0x1f)) 293 294 /* 295 * This is an undocumented feature, a write one to a channel bit in 296 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's 297 * internal current buffer pointer so that transfers start from buffer 298 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM 299 * only says these are read-only registers). This operation is required 300 * for channel linking to work correctly, for instance video capture 301 * pipelines that carry out image rotations will fail after the first 302 * streaming unless this function is called for each channel before 303 * re-enabling the channels. 304 */ 305 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel) 306 { 307 struct ipu_soc *ipu = channel->ipu; 308 unsigned int chno = channel->num; 309 310 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno)); 311 } 312 313 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, 314 bool doublebuffer) 315 { 316 struct ipu_soc *ipu = channel->ipu; 317 unsigned long flags; 318 u32 reg; 319 320 spin_lock_irqsave(&ipu->lock, flags); 321 322 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); 323 if (doublebuffer) 324 reg |= idma_mask(channel->num); 325 else 326 reg &= ~idma_mask(channel->num); 327 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); 328 329 __ipu_idmac_reset_current_buffer(channel); 330 331 spin_unlock_irqrestore(&ipu->lock, flags); 332 } 333 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer); 334 335 static const struct { 336 int chnum; 337 u32 reg; 338 int shift; 339 } idmac_lock_en_info[] = { 340 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, }, 341 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, }, 342 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, }, 343 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, }, 344 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, }, 345 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, }, 346 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, }, 347 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, }, 348 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, }, 349 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, }, 350 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, }, 351 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, }, 352 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, }, 353 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, }, 354 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, }, 355 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, }, 356 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, }, 357 }; 358 359 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts) 360 { 361 struct ipu_soc *ipu = channel->ipu; 362 unsigned long flags; 363 u32 bursts, regval; 364 int i; 365 366 switch (num_bursts) { 367 case 0: 368 case 1: 369 bursts = 0x00; /* locking disabled */ 370 break; 371 case 2: 372 bursts = 0x01; 373 break; 374 case 4: 375 bursts = 0x02; 376 break; 377 case 8: 378 bursts = 0x03; 379 break; 380 default: 381 return -EINVAL; 382 } 383 384 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) { 385 if (channel->num == idmac_lock_en_info[i].chnum) 386 break; 387 } 388 if (i >= ARRAY_SIZE(idmac_lock_en_info)) 389 return -EINVAL; 390 391 spin_lock_irqsave(&ipu->lock, flags); 392 393 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); 394 regval &= ~(0x03 << idmac_lock_en_info[i].shift); 395 regval |= (bursts << idmac_lock_en_info[i].shift); 396 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); 397 398 spin_unlock_irqrestore(&ipu->lock, flags); 399 400 return 0; 401 } 402 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable); 403 404 int ipu_module_enable(struct ipu_soc *ipu, u32 mask) 405 { 406 unsigned long lock_flags; 407 u32 val; 408 409 spin_lock_irqsave(&ipu->lock, lock_flags); 410 411 val = ipu_cm_read(ipu, IPU_DISP_GEN); 412 413 if (mask & IPU_CONF_DI0_EN) 414 val |= IPU_DI0_COUNTER_RELEASE; 415 if (mask & IPU_CONF_DI1_EN) 416 val |= IPU_DI1_COUNTER_RELEASE; 417 418 ipu_cm_write(ipu, val, IPU_DISP_GEN); 419 420 val = ipu_cm_read(ipu, IPU_CONF); 421 val |= mask; 422 ipu_cm_write(ipu, val, IPU_CONF); 423 424 spin_unlock_irqrestore(&ipu->lock, lock_flags); 425 426 return 0; 427 } 428 EXPORT_SYMBOL_GPL(ipu_module_enable); 429 430 int ipu_module_disable(struct ipu_soc *ipu, u32 mask) 431 { 432 unsigned long lock_flags; 433 u32 val; 434 435 spin_lock_irqsave(&ipu->lock, lock_flags); 436 437 val = ipu_cm_read(ipu, IPU_CONF); 438 val &= ~mask; 439 ipu_cm_write(ipu, val, IPU_CONF); 440 441 val = ipu_cm_read(ipu, IPU_DISP_GEN); 442 443 if (mask & IPU_CONF_DI0_EN) 444 val &= ~IPU_DI0_COUNTER_RELEASE; 445 if (mask & IPU_CONF_DI1_EN) 446 val &= ~IPU_DI1_COUNTER_RELEASE; 447 448 ipu_cm_write(ipu, val, IPU_DISP_GEN); 449 450 spin_unlock_irqrestore(&ipu->lock, lock_flags); 451 452 return 0; 453 } 454 EXPORT_SYMBOL_GPL(ipu_module_disable); 455 456 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel) 457 { 458 struct ipu_soc *ipu = channel->ipu; 459 unsigned int chno = channel->num; 460 461 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0; 462 } 463 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer); 464 465 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num) 466 { 467 struct ipu_soc *ipu = channel->ipu; 468 unsigned long flags; 469 u32 reg = 0; 470 471 spin_lock_irqsave(&ipu->lock, flags); 472 switch (buf_num) { 473 case 0: 474 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); 475 break; 476 case 1: 477 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); 478 break; 479 case 2: 480 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); 481 break; 482 } 483 spin_unlock_irqrestore(&ipu->lock, flags); 484 485 return ((reg & idma_mask(channel->num)) != 0); 486 } 487 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready); 488 489 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num) 490 { 491 struct ipu_soc *ipu = channel->ipu; 492 unsigned int chno = channel->num; 493 unsigned long flags; 494 495 spin_lock_irqsave(&ipu->lock, flags); 496 497 /* Mark buffer as ready. */ 498 if (buf_num == 0) 499 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); 500 else 501 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); 502 503 spin_unlock_irqrestore(&ipu->lock, flags); 504 } 505 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer); 506 507 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num) 508 { 509 struct ipu_soc *ipu = channel->ipu; 510 unsigned int chno = channel->num; 511 unsigned long flags; 512 513 spin_lock_irqsave(&ipu->lock, flags); 514 515 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */ 516 switch (buf_num) { 517 case 0: 518 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); 519 break; 520 case 1: 521 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); 522 break; 523 case 2: 524 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno)); 525 break; 526 default: 527 break; 528 } 529 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ 530 531 spin_unlock_irqrestore(&ipu->lock, flags); 532 } 533 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer); 534 535 int ipu_idmac_enable_channel(struct ipuv3_channel *channel) 536 { 537 struct ipu_soc *ipu = channel->ipu; 538 u32 val; 539 unsigned long flags; 540 541 spin_lock_irqsave(&ipu->lock, flags); 542 543 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); 544 val |= idma_mask(channel->num); 545 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); 546 547 spin_unlock_irqrestore(&ipu->lock, flags); 548 549 return 0; 550 } 551 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel); 552 553 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno) 554 { 555 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno)); 556 } 557 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy); 558 559 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms) 560 { 561 struct ipu_soc *ipu = channel->ipu; 562 unsigned long timeout; 563 564 timeout = jiffies + msecs_to_jiffies(ms); 565 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & 566 idma_mask(channel->num)) { 567 if (time_after(jiffies, timeout)) 568 return -ETIMEDOUT; 569 cpu_relax(); 570 } 571 572 return 0; 573 } 574 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy); 575 576 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms) 577 { 578 unsigned long timeout; 579 580 timeout = jiffies + msecs_to_jiffies(ms); 581 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32)); 582 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) { 583 if (time_after(jiffies, timeout)) 584 return -ETIMEDOUT; 585 cpu_relax(); 586 } 587 588 return 0; 589 } 590 EXPORT_SYMBOL_GPL(ipu_wait_interrupt); 591 592 int ipu_idmac_disable_channel(struct ipuv3_channel *channel) 593 { 594 struct ipu_soc *ipu = channel->ipu; 595 u32 val; 596 unsigned long flags; 597 598 spin_lock_irqsave(&ipu->lock, flags); 599 600 /* Disable DMA channel(s) */ 601 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); 602 val &= ~idma_mask(channel->num); 603 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); 604 605 __ipu_idmac_reset_current_buffer(channel); 606 607 /* Set channel buffers NOT to be ready */ 608 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ 609 610 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & 611 idma_mask(channel->num)) { 612 ipu_cm_write(ipu, idma_mask(channel->num), 613 IPU_CHA_BUF0_RDY(channel->num)); 614 } 615 616 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & 617 idma_mask(channel->num)) { 618 ipu_cm_write(ipu, idma_mask(channel->num), 619 IPU_CHA_BUF1_RDY(channel->num)); 620 } 621 622 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ 623 624 /* Reset the double buffer */ 625 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); 626 val &= ~idma_mask(channel->num); 627 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); 628 629 spin_unlock_irqrestore(&ipu->lock, flags); 630 631 return 0; 632 } 633 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel); 634 635 /* 636 * The imx6 rev. D TRM says that enabling the WM feature will increase 637 * a channel's priority. Refer to Table 36-8 Calculated priority value. 638 * The sub-module that is the sink or source for the channel must enable 639 * watermark signal for this to take effect (SMFC_WM for instance). 640 */ 641 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable) 642 { 643 struct ipu_soc *ipu = channel->ipu; 644 unsigned long flags; 645 u32 val; 646 647 spin_lock_irqsave(&ipu->lock, flags); 648 649 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); 650 if (enable) 651 val |= 1 << (channel->num % 32); 652 else 653 val &= ~(1 << (channel->num % 32)); 654 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); 655 656 spin_unlock_irqrestore(&ipu->lock, flags); 657 } 658 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark); 659 660 static int ipu_memory_reset(struct ipu_soc *ipu) 661 { 662 unsigned long timeout; 663 664 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); 665 666 timeout = jiffies + msecs_to_jiffies(1000); 667 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { 668 if (time_after(jiffies, timeout)) 669 return -ETIME; 670 cpu_relax(); 671 } 672 673 return 0; 674 } 675 676 /* 677 * Set the source mux for the given CSI. Selects either parallel or 678 * MIPI CSI2 sources. 679 */ 680 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2) 681 { 682 unsigned long flags; 683 u32 val, mask; 684 685 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE : 686 IPU_CONF_CSI0_DATA_SOURCE; 687 688 spin_lock_irqsave(&ipu->lock, flags); 689 690 val = ipu_cm_read(ipu, IPU_CONF); 691 if (mipi_csi2) 692 val |= mask; 693 else 694 val &= ~mask; 695 ipu_cm_write(ipu, val, IPU_CONF); 696 697 spin_unlock_irqrestore(&ipu->lock, flags); 698 } 699 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux); 700 701 /* 702 * Set the source mux for the IC. Selects either CSI[01] or the VDI. 703 */ 704 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) 705 { 706 unsigned long flags; 707 u32 val; 708 709 spin_lock_irqsave(&ipu->lock, flags); 710 711 val = ipu_cm_read(ipu, IPU_CONF); 712 if (vdi) { 713 val |= IPU_CONF_IC_INPUT; 714 } else { 715 val &= ~IPU_CONF_IC_INPUT; 716 if (csi_id == 1) 717 val |= IPU_CONF_CSI_SEL; 718 else 719 val &= ~IPU_CONF_CSI_SEL; 720 } 721 ipu_cm_write(ipu, val, IPU_CONF); 722 723 spin_unlock_irqrestore(&ipu->lock, flags); 724 } 725 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux); 726 727 struct ipu_devtype { 728 const char *name; 729 unsigned long cm_ofs; 730 unsigned long cpmem_ofs; 731 unsigned long srm_ofs; 732 unsigned long tpm_ofs; 733 unsigned long csi0_ofs; 734 unsigned long csi1_ofs; 735 unsigned long ic_ofs; 736 unsigned long disp0_ofs; 737 unsigned long disp1_ofs; 738 unsigned long dc_tmpl_ofs; 739 unsigned long vdi_ofs; 740 enum ipuv3_type type; 741 }; 742 743 static struct ipu_devtype ipu_type_imx51 = { 744 .name = "IPUv3EX", 745 .cm_ofs = 0x1e000000, 746 .cpmem_ofs = 0x1f000000, 747 .srm_ofs = 0x1f040000, 748 .tpm_ofs = 0x1f060000, 749 .csi0_ofs = 0x1f030000, 750 .csi1_ofs = 0x1f038000, 751 .ic_ofs = 0x1e020000, 752 .disp0_ofs = 0x1e040000, 753 .disp1_ofs = 0x1e048000, 754 .dc_tmpl_ofs = 0x1f080000, 755 .vdi_ofs = 0x1e068000, 756 .type = IPUV3EX, 757 }; 758 759 static struct ipu_devtype ipu_type_imx53 = { 760 .name = "IPUv3M", 761 .cm_ofs = 0x06000000, 762 .cpmem_ofs = 0x07000000, 763 .srm_ofs = 0x07040000, 764 .tpm_ofs = 0x07060000, 765 .csi0_ofs = 0x07030000, 766 .csi1_ofs = 0x07038000, 767 .ic_ofs = 0x06020000, 768 .disp0_ofs = 0x06040000, 769 .disp1_ofs = 0x06048000, 770 .dc_tmpl_ofs = 0x07080000, 771 .vdi_ofs = 0x06068000, 772 .type = IPUV3M, 773 }; 774 775 static struct ipu_devtype ipu_type_imx6q = { 776 .name = "IPUv3H", 777 .cm_ofs = 0x00200000, 778 .cpmem_ofs = 0x00300000, 779 .srm_ofs = 0x00340000, 780 .tpm_ofs = 0x00360000, 781 .csi0_ofs = 0x00230000, 782 .csi1_ofs = 0x00238000, 783 .ic_ofs = 0x00220000, 784 .disp0_ofs = 0x00240000, 785 .disp1_ofs = 0x00248000, 786 .dc_tmpl_ofs = 0x00380000, 787 .vdi_ofs = 0x00268000, 788 .type = IPUV3H, 789 }; 790 791 static const struct of_device_id imx_ipu_dt_ids[] = { 792 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, }, 793 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, }, 794 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, }, 795 { /* sentinel */ } 796 }; 797 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids); 798 799 static int ipu_submodules_init(struct ipu_soc *ipu, 800 struct platform_device *pdev, unsigned long ipu_base, 801 struct clk *ipu_clk) 802 { 803 char *unit; 804 int ret; 805 struct device *dev = &pdev->dev; 806 const struct ipu_devtype *devtype = ipu->devtype; 807 808 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); 809 if (ret) { 810 unit = "cpmem"; 811 goto err_cpmem; 812 } 813 814 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, 815 IPU_CONF_CSI0_EN, ipu_clk); 816 if (ret) { 817 unit = "csi0"; 818 goto err_csi_0; 819 } 820 821 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, 822 IPU_CONF_CSI1_EN, ipu_clk); 823 if (ret) { 824 unit = "csi1"; 825 goto err_csi_1; 826 } 827 828 ret = ipu_ic_init(ipu, dev, 829 ipu_base + devtype->ic_ofs, 830 ipu_base + devtype->tpm_ofs); 831 if (ret) { 832 unit = "ic"; 833 goto err_ic; 834 } 835 836 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, 837 IPU_CONF_DI0_EN, ipu_clk); 838 if (ret) { 839 unit = "di0"; 840 goto err_di_0; 841 } 842 843 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, 844 IPU_CONF_DI1_EN, ipu_clk); 845 if (ret) { 846 unit = "di1"; 847 goto err_di_1; 848 } 849 850 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + 851 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs); 852 if (ret) { 853 unit = "dc_template"; 854 goto err_dc; 855 } 856 857 ret = ipu_dmfc_init(ipu, dev, ipu_base + 858 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk); 859 if (ret) { 860 unit = "dmfc"; 861 goto err_dmfc; 862 } 863 864 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); 865 if (ret) { 866 unit = "dp"; 867 goto err_dp; 868 } 869 870 ret = ipu_smfc_init(ipu, dev, ipu_base + 871 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS); 872 if (ret) { 873 unit = "smfc"; 874 goto err_smfc; 875 } 876 877 return 0; 878 879 err_smfc: 880 ipu_dp_exit(ipu); 881 err_dp: 882 ipu_dmfc_exit(ipu); 883 err_dmfc: 884 ipu_dc_exit(ipu); 885 err_dc: 886 ipu_di_exit(ipu, 1); 887 err_di_1: 888 ipu_di_exit(ipu, 0); 889 err_di_0: 890 ipu_ic_exit(ipu); 891 err_ic: 892 ipu_csi_exit(ipu, 1); 893 err_csi_1: 894 ipu_csi_exit(ipu, 0); 895 err_csi_0: 896 ipu_cpmem_exit(ipu); 897 err_cpmem: 898 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret); 899 return ret; 900 } 901 902 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) 903 { 904 unsigned long status; 905 int i, bit, irq; 906 907 for (i = 0; i < num_regs; i++) { 908 909 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); 910 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); 911 912 for_each_set_bit(bit, &status, 32) { 913 irq = irq_linear_revmap(ipu->domain, 914 regs[i] * 32 + bit); 915 if (irq) 916 generic_handle_irq(irq); 917 } 918 } 919 } 920 921 static void ipu_irq_handler(struct irq_desc *desc) 922 { 923 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); 924 struct irq_chip *chip = irq_desc_get_chip(desc); 925 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14}; 926 927 chained_irq_enter(chip, desc); 928 929 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); 930 931 chained_irq_exit(chip, desc); 932 } 933 934 static void ipu_err_irq_handler(struct irq_desc *desc) 935 { 936 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); 937 struct irq_chip *chip = irq_desc_get_chip(desc); 938 const int int_reg[] = { 4, 5, 8, 9}; 939 940 chained_irq_enter(chip, desc); 941 942 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); 943 944 chained_irq_exit(chip, desc); 945 } 946 947 int ipu_map_irq(struct ipu_soc *ipu, int irq) 948 { 949 int virq; 950 951 virq = irq_linear_revmap(ipu->domain, irq); 952 if (!virq) 953 virq = irq_create_mapping(ipu->domain, irq); 954 955 return virq; 956 } 957 EXPORT_SYMBOL_GPL(ipu_map_irq); 958 959 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, 960 enum ipu_channel_irq irq_type) 961 { 962 return ipu_map_irq(ipu, irq_type + channel->num); 963 } 964 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq); 965 966 static void ipu_submodules_exit(struct ipu_soc *ipu) 967 { 968 ipu_smfc_exit(ipu); 969 ipu_dp_exit(ipu); 970 ipu_dmfc_exit(ipu); 971 ipu_dc_exit(ipu); 972 ipu_di_exit(ipu, 1); 973 ipu_di_exit(ipu, 0); 974 ipu_ic_exit(ipu); 975 ipu_csi_exit(ipu, 1); 976 ipu_csi_exit(ipu, 0); 977 ipu_cpmem_exit(ipu); 978 } 979 980 static int platform_remove_devices_fn(struct device *dev, void *unused) 981 { 982 struct platform_device *pdev = to_platform_device(dev); 983 984 platform_device_unregister(pdev); 985 986 return 0; 987 } 988 989 static void platform_device_unregister_children(struct platform_device *pdev) 990 { 991 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn); 992 } 993 994 struct ipu_platform_reg { 995 struct ipu_client_platformdata pdata; 996 const char *name; 997 }; 998 999 /* These must be in the order of the corresponding device tree port nodes */ 1000 static struct ipu_platform_reg client_reg[] = { 1001 { 1002 .pdata = { 1003 .csi = 0, 1004 .dma[0] = IPUV3_CHANNEL_CSI0, 1005 .dma[1] = -EINVAL, 1006 }, 1007 .name = "imx-ipuv3-camera", 1008 }, { 1009 .pdata = { 1010 .csi = 1, 1011 .dma[0] = IPUV3_CHANNEL_CSI1, 1012 .dma[1] = -EINVAL, 1013 }, 1014 .name = "imx-ipuv3-camera", 1015 }, { 1016 .pdata = { 1017 .di = 0, 1018 .dc = 5, 1019 .dp = IPU_DP_FLOW_SYNC_BG, 1020 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC, 1021 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC, 1022 }, 1023 .name = "imx-ipuv3-crtc", 1024 }, { 1025 .pdata = { 1026 .di = 1, 1027 .dc = 1, 1028 .dp = -EINVAL, 1029 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC, 1030 .dma[1] = -EINVAL, 1031 }, 1032 .name = "imx-ipuv3-crtc", 1033 }, 1034 }; 1035 1036 static DEFINE_MUTEX(ipu_client_id_mutex); 1037 static int ipu_client_id; 1038 1039 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) 1040 { 1041 struct device *dev = ipu->dev; 1042 unsigned i; 1043 int id, ret; 1044 1045 mutex_lock(&ipu_client_id_mutex); 1046 id = ipu_client_id; 1047 ipu_client_id += ARRAY_SIZE(client_reg); 1048 mutex_unlock(&ipu_client_id_mutex); 1049 1050 for (i = 0; i < ARRAY_SIZE(client_reg); i++) { 1051 struct ipu_platform_reg *reg = &client_reg[i]; 1052 struct platform_device *pdev; 1053 struct device_node *of_node; 1054 1055 /* Associate subdevice with the corresponding port node */ 1056 of_node = of_graph_get_port_by_id(dev->of_node, i); 1057 if (!of_node) { 1058 dev_info(dev, 1059 "no port@%d node in %s, not using %s%d\n", 1060 i, dev->of_node->full_name, 1061 (i / 2) ? "DI" : "CSI", i % 2); 1062 continue; 1063 } 1064 1065 pdev = platform_device_alloc(reg->name, id++); 1066 if (!pdev) { 1067 ret = -ENOMEM; 1068 goto err_register; 1069 } 1070 1071 pdev->dev.parent = dev; 1072 1073 reg->pdata.of_node = of_node; 1074 ret = platform_device_add_data(pdev, ®->pdata, 1075 sizeof(reg->pdata)); 1076 if (!ret) 1077 ret = platform_device_add(pdev); 1078 if (ret) { 1079 platform_device_put(pdev); 1080 goto err_register; 1081 } 1082 1083 /* 1084 * Set of_node only after calling platform_device_add. Otherwise 1085 * the platform:imx-ipuv3-crtc modalias won't be used. 1086 */ 1087 pdev->dev.of_node = of_node; 1088 } 1089 1090 return 0; 1091 1092 err_register: 1093 platform_device_unregister_children(to_platform_device(dev)); 1094 1095 return ret; 1096 } 1097 1098 1099 static int ipu_irq_init(struct ipu_soc *ipu) 1100 { 1101 struct irq_chip_generic *gc; 1102 struct irq_chip_type *ct; 1103 unsigned long unused[IPU_NUM_IRQS / 32] = { 1104 0x400100d0, 0xffe000fd, 1105 0x400100d0, 0xffe000fd, 1106 0x400100d0, 0xffe000fd, 1107 0x4077ffff, 0xffe7e1fd, 1108 0x23fffffe, 0x8880fff0, 1109 0xf98fe7d0, 0xfff81fff, 1110 0x400100d0, 0xffe000fd, 1111 0x00000000, 1112 }; 1113 int ret, i; 1114 1115 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, 1116 &irq_generic_chip_ops, ipu); 1117 if (!ipu->domain) { 1118 dev_err(ipu->dev, "failed to add irq domain\n"); 1119 return -ENODEV; 1120 } 1121 1122 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", 1123 handle_level_irq, 0, 0, 0); 1124 if (ret < 0) { 1125 dev_err(ipu->dev, "failed to alloc generic irq chips\n"); 1126 irq_domain_remove(ipu->domain); 1127 return ret; 1128 } 1129 1130 for (i = 0; i < IPU_NUM_IRQS; i += 32) 1131 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32)); 1132 1133 for (i = 0; i < IPU_NUM_IRQS; i += 32) { 1134 gc = irq_get_domain_generic_chip(ipu->domain, i); 1135 gc->reg_base = ipu->cm_reg; 1136 gc->unused = unused[i / 32]; 1137 ct = gc->chip_types; 1138 ct->chip.irq_ack = irq_gc_ack_set_bit; 1139 ct->chip.irq_mask = irq_gc_mask_clr_bit; 1140 ct->chip.irq_unmask = irq_gc_mask_set_bit; 1141 ct->regs.ack = IPU_INT_STAT(i / 32); 1142 ct->regs.mask = IPU_INT_CTRL(i / 32); 1143 } 1144 1145 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu); 1146 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler, 1147 ipu); 1148 1149 return 0; 1150 } 1151 1152 static void ipu_irq_exit(struct ipu_soc *ipu) 1153 { 1154 int i, irq; 1155 1156 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL); 1157 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL); 1158 1159 /* TODO: remove irq_domain_generic_chips */ 1160 1161 for (i = 0; i < IPU_NUM_IRQS; i++) { 1162 irq = irq_linear_revmap(ipu->domain, i); 1163 if (irq) 1164 irq_dispose_mapping(irq); 1165 } 1166 1167 irq_domain_remove(ipu->domain); 1168 } 1169 1170 void ipu_dump(struct ipu_soc *ipu) 1171 { 1172 int i; 1173 1174 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", 1175 ipu_cm_read(ipu, IPU_CONF)); 1176 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", 1177 ipu_idmac_read(ipu, IDMAC_CONF)); 1178 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n", 1179 ipu_idmac_read(ipu, IDMAC_CHA_EN(0))); 1180 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n", 1181 ipu_idmac_read(ipu, IDMAC_CHA_EN(32))); 1182 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n", 1183 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0))); 1184 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n", 1185 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32))); 1186 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n", 1187 ipu_idmac_read(ipu, IDMAC_BAND_EN(0))); 1188 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n", 1189 ipu_idmac_read(ipu, IDMAC_BAND_EN(32))); 1190 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", 1191 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0))); 1192 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", 1193 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32))); 1194 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n", 1195 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1)); 1196 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n", 1197 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2)); 1198 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n", 1199 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3)); 1200 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n", 1201 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1)); 1202 for (i = 0; i < 15; i++) 1203 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i, 1204 ipu_cm_read(ipu, IPU_INT_CTRL(i))); 1205 } 1206 EXPORT_SYMBOL_GPL(ipu_dump); 1207 1208 static int ipu_probe(struct platform_device *pdev) 1209 { 1210 const struct of_device_id *of_id = 1211 of_match_device(imx_ipu_dt_ids, &pdev->dev); 1212 struct ipu_soc *ipu; 1213 struct resource *res; 1214 unsigned long ipu_base; 1215 int i, ret, irq_sync, irq_err; 1216 const struct ipu_devtype *devtype; 1217 1218 devtype = of_id->data; 1219 1220 irq_sync = platform_get_irq(pdev, 0); 1221 irq_err = platform_get_irq(pdev, 1); 1222 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1223 1224 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n", 1225 irq_sync, irq_err); 1226 1227 if (!res || irq_sync < 0 || irq_err < 0) 1228 return -ENODEV; 1229 1230 ipu_base = res->start; 1231 1232 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); 1233 if (!ipu) 1234 return -ENODEV; 1235 1236 for (i = 0; i < 64; i++) 1237 ipu->channel[i].ipu = ipu; 1238 ipu->devtype = devtype; 1239 ipu->ipu_type = devtype->type; 1240 1241 spin_lock_init(&ipu->lock); 1242 mutex_init(&ipu->channel_lock); 1243 1244 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n", 1245 ipu_base + devtype->cm_ofs); 1246 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n", 1247 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS); 1248 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n", 1249 ipu_base + devtype->cpmem_ofs); 1250 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n", 1251 ipu_base + devtype->csi0_ofs); 1252 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n", 1253 ipu_base + devtype->csi1_ofs); 1254 dev_dbg(&pdev->dev, "ic: 0x%08lx\n", 1255 ipu_base + devtype->ic_ofs); 1256 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n", 1257 ipu_base + devtype->disp0_ofs); 1258 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n", 1259 ipu_base + devtype->disp1_ofs); 1260 dev_dbg(&pdev->dev, "srm: 0x%08lx\n", 1261 ipu_base + devtype->srm_ofs); 1262 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n", 1263 ipu_base + devtype->tpm_ofs); 1264 dev_dbg(&pdev->dev, "dc: 0x%08lx\n", 1265 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS); 1266 dev_dbg(&pdev->dev, "ic: 0x%08lx\n", 1267 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS); 1268 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n", 1269 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS); 1270 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n", 1271 ipu_base + devtype->vdi_ofs); 1272 1273 ipu->cm_reg = devm_ioremap(&pdev->dev, 1274 ipu_base + devtype->cm_ofs, PAGE_SIZE); 1275 ipu->idmac_reg = devm_ioremap(&pdev->dev, 1276 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS, 1277 PAGE_SIZE); 1278 1279 if (!ipu->cm_reg || !ipu->idmac_reg) 1280 return -ENOMEM; 1281 1282 ipu->clk = devm_clk_get(&pdev->dev, "bus"); 1283 if (IS_ERR(ipu->clk)) { 1284 ret = PTR_ERR(ipu->clk); 1285 dev_err(&pdev->dev, "clk_get failed with %d", ret); 1286 return ret; 1287 } 1288 1289 platform_set_drvdata(pdev, ipu); 1290 1291 ret = clk_prepare_enable(ipu->clk); 1292 if (ret) { 1293 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); 1294 return ret; 1295 } 1296 1297 ipu->dev = &pdev->dev; 1298 ipu->irq_sync = irq_sync; 1299 ipu->irq_err = irq_err; 1300 1301 ret = device_reset(&pdev->dev); 1302 if (ret) { 1303 dev_err(&pdev->dev, "failed to reset: %d\n", ret); 1304 goto out_failed_reset; 1305 } 1306 ret = ipu_memory_reset(ipu); 1307 if (ret) 1308 goto out_failed_reset; 1309 1310 ret = ipu_irq_init(ipu); 1311 if (ret) 1312 goto out_failed_irq; 1313 1314 /* Set MCU_T to divide MCU access window into 2 */ 1315 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), 1316 IPU_DISP_GEN); 1317 1318 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); 1319 if (ret) 1320 goto failed_submodules_init; 1321 1322 ret = ipu_add_client_devices(ipu, ipu_base); 1323 if (ret) { 1324 dev_err(&pdev->dev, "adding client devices failed with %d\n", 1325 ret); 1326 goto failed_add_clients; 1327 } 1328 1329 dev_info(&pdev->dev, "%s probed\n", devtype->name); 1330 1331 return 0; 1332 1333 failed_add_clients: 1334 ipu_submodules_exit(ipu); 1335 failed_submodules_init: 1336 ipu_irq_exit(ipu); 1337 out_failed_irq: 1338 out_failed_reset: 1339 clk_disable_unprepare(ipu->clk); 1340 return ret; 1341 } 1342 1343 static int ipu_remove(struct platform_device *pdev) 1344 { 1345 struct ipu_soc *ipu = platform_get_drvdata(pdev); 1346 1347 platform_device_unregister_children(pdev); 1348 ipu_submodules_exit(ipu); 1349 ipu_irq_exit(ipu); 1350 1351 clk_disable_unprepare(ipu->clk); 1352 1353 return 0; 1354 } 1355 1356 static struct platform_driver imx_ipu_driver = { 1357 .driver = { 1358 .name = "imx-ipuv3", 1359 .of_match_table = imx_ipu_dt_ids, 1360 }, 1361 .probe = ipu_probe, 1362 .remove = ipu_remove, 1363 }; 1364 1365 module_platform_driver(imx_ipu_driver); 1366 1367 MODULE_ALIAS("platform:imx-ipuv3"); 1368 MODULE_DESCRIPTION("i.MX IPU v3 driver"); 1369 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 1370 MODULE_LICENSE("GPL"); 1371