1 /* 2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> 3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 */ 15 #include <linux/module.h> 16 #include <linux/export.h> 17 #include <linux/types.h> 18 #include <linux/reset.h> 19 #include <linux/platform_device.h> 20 #include <linux/err.h> 21 #include <linux/spinlock.h> 22 #include <linux/delay.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/clk.h> 26 #include <linux/list.h> 27 #include <linux/irq.h> 28 #include <linux/irqchip/chained_irq.h> 29 #include <linux/irqdomain.h> 30 #include <linux/of_device.h> 31 #include <linux/of_graph.h> 32 33 #include <drm/drm_fourcc.h> 34 35 #include <video/imx-ipu-v3.h> 36 #include "ipu-prv.h" 37 38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) 39 { 40 return readl(ipu->cm_reg + offset); 41 } 42 43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) 44 { 45 writel(value, ipu->cm_reg + offset); 46 } 47 48 int ipu_get_num(struct ipu_soc *ipu) 49 { 50 return ipu->id; 51 } 52 EXPORT_SYMBOL_GPL(ipu_get_num); 53 54 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync) 55 { 56 u32 val; 57 58 val = ipu_cm_read(ipu, IPU_SRM_PRI2); 59 val &= ~DP_S_SRM_MODE_MASK; 60 val |= sync ? DP_S_SRM_MODE_NEXT_FRAME : 61 DP_S_SRM_MODE_NOW; 62 ipu_cm_write(ipu, val, IPU_SRM_PRI2); 63 } 64 EXPORT_SYMBOL_GPL(ipu_srm_dp_update); 65 66 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc) 67 { 68 switch (drm_fourcc) { 69 case DRM_FORMAT_ARGB1555: 70 case DRM_FORMAT_ABGR1555: 71 case DRM_FORMAT_RGBA5551: 72 case DRM_FORMAT_BGRA5551: 73 case DRM_FORMAT_RGB565: 74 case DRM_FORMAT_BGR565: 75 case DRM_FORMAT_RGB888: 76 case DRM_FORMAT_BGR888: 77 case DRM_FORMAT_ARGB4444: 78 case DRM_FORMAT_XRGB8888: 79 case DRM_FORMAT_XBGR8888: 80 case DRM_FORMAT_RGBX8888: 81 case DRM_FORMAT_BGRX8888: 82 case DRM_FORMAT_ARGB8888: 83 case DRM_FORMAT_ABGR8888: 84 case DRM_FORMAT_RGBA8888: 85 case DRM_FORMAT_BGRA8888: 86 case DRM_FORMAT_RGB565_A8: 87 case DRM_FORMAT_BGR565_A8: 88 case DRM_FORMAT_RGB888_A8: 89 case DRM_FORMAT_BGR888_A8: 90 case DRM_FORMAT_RGBX8888_A8: 91 case DRM_FORMAT_BGRX8888_A8: 92 return IPUV3_COLORSPACE_RGB; 93 case DRM_FORMAT_YUYV: 94 case DRM_FORMAT_UYVY: 95 case DRM_FORMAT_YUV420: 96 case DRM_FORMAT_YVU420: 97 case DRM_FORMAT_YUV422: 98 case DRM_FORMAT_YVU422: 99 case DRM_FORMAT_YUV444: 100 case DRM_FORMAT_YVU444: 101 case DRM_FORMAT_NV12: 102 case DRM_FORMAT_NV21: 103 case DRM_FORMAT_NV16: 104 case DRM_FORMAT_NV61: 105 return IPUV3_COLORSPACE_YUV; 106 default: 107 return IPUV3_COLORSPACE_UNKNOWN; 108 } 109 } 110 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace); 111 112 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat) 113 { 114 switch (pixelformat) { 115 case V4L2_PIX_FMT_YUV420: 116 case V4L2_PIX_FMT_YVU420: 117 case V4L2_PIX_FMT_YUV422P: 118 case V4L2_PIX_FMT_UYVY: 119 case V4L2_PIX_FMT_YUYV: 120 case V4L2_PIX_FMT_NV12: 121 case V4L2_PIX_FMT_NV21: 122 case V4L2_PIX_FMT_NV16: 123 case V4L2_PIX_FMT_NV61: 124 return IPUV3_COLORSPACE_YUV; 125 case V4L2_PIX_FMT_RGB32: 126 case V4L2_PIX_FMT_BGR32: 127 case V4L2_PIX_FMT_RGB24: 128 case V4L2_PIX_FMT_BGR24: 129 case V4L2_PIX_FMT_RGB565: 130 return IPUV3_COLORSPACE_RGB; 131 default: 132 return IPUV3_COLORSPACE_UNKNOWN; 133 } 134 } 135 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace); 136 137 bool ipu_pixelformat_is_planar(u32 pixelformat) 138 { 139 switch (pixelformat) { 140 case V4L2_PIX_FMT_YUV420: 141 case V4L2_PIX_FMT_YVU420: 142 case V4L2_PIX_FMT_YUV422P: 143 case V4L2_PIX_FMT_NV12: 144 case V4L2_PIX_FMT_NV21: 145 case V4L2_PIX_FMT_NV16: 146 case V4L2_PIX_FMT_NV61: 147 return true; 148 } 149 150 return false; 151 } 152 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar); 153 154 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code) 155 { 156 switch (mbus_code & 0xf000) { 157 case 0x1000: 158 return IPUV3_COLORSPACE_RGB; 159 case 0x2000: 160 return IPUV3_COLORSPACE_YUV; 161 default: 162 return IPUV3_COLORSPACE_UNKNOWN; 163 } 164 } 165 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace); 166 167 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat) 168 { 169 switch (pixelformat) { 170 case V4L2_PIX_FMT_YUV420: 171 case V4L2_PIX_FMT_YVU420: 172 case V4L2_PIX_FMT_YUV422P: 173 case V4L2_PIX_FMT_NV12: 174 case V4L2_PIX_FMT_NV21: 175 case V4L2_PIX_FMT_NV16: 176 case V4L2_PIX_FMT_NV61: 177 /* 178 * for the planar YUV formats, the stride passed to 179 * cpmem must be the stride in bytes of the Y plane. 180 * And all the planar YUV formats have an 8-bit 181 * Y component. 182 */ 183 return (8 * pixel_stride) >> 3; 184 case V4L2_PIX_FMT_RGB565: 185 case V4L2_PIX_FMT_YUYV: 186 case V4L2_PIX_FMT_UYVY: 187 return (16 * pixel_stride) >> 3; 188 case V4L2_PIX_FMT_BGR24: 189 case V4L2_PIX_FMT_RGB24: 190 return (24 * pixel_stride) >> 3; 191 case V4L2_PIX_FMT_BGR32: 192 case V4L2_PIX_FMT_RGB32: 193 return (32 * pixel_stride) >> 3; 194 default: 195 break; 196 } 197 198 return -EINVAL; 199 } 200 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes); 201 202 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees, 203 bool hflip, bool vflip) 204 { 205 u32 r90, vf, hf; 206 207 switch (degrees) { 208 case 0: 209 vf = hf = r90 = 0; 210 break; 211 case 90: 212 vf = hf = 0; 213 r90 = 1; 214 break; 215 case 180: 216 vf = hf = 1; 217 r90 = 0; 218 break; 219 case 270: 220 vf = hf = r90 = 1; 221 break; 222 default: 223 return -EINVAL; 224 } 225 226 hf ^= (u32)hflip; 227 vf ^= (u32)vflip; 228 229 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf); 230 return 0; 231 } 232 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode); 233 234 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode, 235 bool hflip, bool vflip) 236 { 237 u32 r90, vf, hf; 238 239 r90 = ((u32)mode >> 2) & 0x1; 240 hf = ((u32)mode >> 1) & 0x1; 241 vf = ((u32)mode >> 0) & 0x1; 242 hf ^= (u32)hflip; 243 vf ^= (u32)vflip; 244 245 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) { 246 case IPU_ROTATE_NONE: 247 *degrees = 0; 248 break; 249 case IPU_ROTATE_90_RIGHT: 250 *degrees = 90; 251 break; 252 case IPU_ROTATE_180: 253 *degrees = 180; 254 break; 255 case IPU_ROTATE_90_LEFT: 256 *degrees = 270; 257 break; 258 default: 259 return -EINVAL; 260 } 261 262 return 0; 263 } 264 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees); 265 266 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) 267 { 268 struct ipuv3_channel *channel; 269 270 dev_dbg(ipu->dev, "%s %d\n", __func__, num); 271 272 if (num > 63) 273 return ERR_PTR(-ENODEV); 274 275 mutex_lock(&ipu->channel_lock); 276 277 list_for_each_entry(channel, &ipu->channels, list) { 278 if (channel->num == num) { 279 channel = ERR_PTR(-EBUSY); 280 goto out; 281 } 282 } 283 284 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 285 if (!channel) { 286 channel = ERR_PTR(-ENOMEM); 287 goto out; 288 } 289 290 channel->num = num; 291 channel->ipu = ipu; 292 list_add(&channel->list, &ipu->channels); 293 294 out: 295 mutex_unlock(&ipu->channel_lock); 296 297 return channel; 298 } 299 EXPORT_SYMBOL_GPL(ipu_idmac_get); 300 301 void ipu_idmac_put(struct ipuv3_channel *channel) 302 { 303 struct ipu_soc *ipu = channel->ipu; 304 305 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); 306 307 mutex_lock(&ipu->channel_lock); 308 309 list_del(&channel->list); 310 kfree(channel); 311 312 mutex_unlock(&ipu->channel_lock); 313 } 314 EXPORT_SYMBOL_GPL(ipu_idmac_put); 315 316 #define idma_mask(ch) (1 << ((ch) & 0x1f)) 317 318 /* 319 * This is an undocumented feature, a write one to a channel bit in 320 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's 321 * internal current buffer pointer so that transfers start from buffer 322 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM 323 * only says these are read-only registers). This operation is required 324 * for channel linking to work correctly, for instance video capture 325 * pipelines that carry out image rotations will fail after the first 326 * streaming unless this function is called for each channel before 327 * re-enabling the channels. 328 */ 329 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel) 330 { 331 struct ipu_soc *ipu = channel->ipu; 332 unsigned int chno = channel->num; 333 334 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno)); 335 } 336 337 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, 338 bool doublebuffer) 339 { 340 struct ipu_soc *ipu = channel->ipu; 341 unsigned long flags; 342 u32 reg; 343 344 spin_lock_irqsave(&ipu->lock, flags); 345 346 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); 347 if (doublebuffer) 348 reg |= idma_mask(channel->num); 349 else 350 reg &= ~idma_mask(channel->num); 351 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); 352 353 __ipu_idmac_reset_current_buffer(channel); 354 355 spin_unlock_irqrestore(&ipu->lock, flags); 356 } 357 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer); 358 359 static const struct { 360 int chnum; 361 u32 reg; 362 int shift; 363 } idmac_lock_en_info[] = { 364 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, }, 365 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, }, 366 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, }, 367 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, }, 368 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, }, 369 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, }, 370 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, }, 371 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, }, 372 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, }, 373 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, }, 374 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, }, 375 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, }, 376 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, }, 377 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, }, 378 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, }, 379 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, }, 380 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, }, 381 }; 382 383 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts) 384 { 385 struct ipu_soc *ipu = channel->ipu; 386 unsigned long flags; 387 u32 bursts, regval; 388 int i; 389 390 switch (num_bursts) { 391 case 0: 392 case 1: 393 bursts = 0x00; /* locking disabled */ 394 break; 395 case 2: 396 bursts = 0x01; 397 break; 398 case 4: 399 bursts = 0x02; 400 break; 401 case 8: 402 bursts = 0x03; 403 break; 404 default: 405 return -EINVAL; 406 } 407 408 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) { 409 if (channel->num == idmac_lock_en_info[i].chnum) 410 break; 411 } 412 if (i >= ARRAY_SIZE(idmac_lock_en_info)) 413 return -EINVAL; 414 415 spin_lock_irqsave(&ipu->lock, flags); 416 417 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); 418 regval &= ~(0x03 << idmac_lock_en_info[i].shift); 419 regval |= (bursts << idmac_lock_en_info[i].shift); 420 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); 421 422 spin_unlock_irqrestore(&ipu->lock, flags); 423 424 return 0; 425 } 426 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable); 427 428 int ipu_module_enable(struct ipu_soc *ipu, u32 mask) 429 { 430 unsigned long lock_flags; 431 u32 val; 432 433 spin_lock_irqsave(&ipu->lock, lock_flags); 434 435 val = ipu_cm_read(ipu, IPU_DISP_GEN); 436 437 if (mask & IPU_CONF_DI0_EN) 438 val |= IPU_DI0_COUNTER_RELEASE; 439 if (mask & IPU_CONF_DI1_EN) 440 val |= IPU_DI1_COUNTER_RELEASE; 441 442 ipu_cm_write(ipu, val, IPU_DISP_GEN); 443 444 val = ipu_cm_read(ipu, IPU_CONF); 445 val |= mask; 446 ipu_cm_write(ipu, val, IPU_CONF); 447 448 spin_unlock_irqrestore(&ipu->lock, lock_flags); 449 450 return 0; 451 } 452 EXPORT_SYMBOL_GPL(ipu_module_enable); 453 454 int ipu_module_disable(struct ipu_soc *ipu, u32 mask) 455 { 456 unsigned long lock_flags; 457 u32 val; 458 459 spin_lock_irqsave(&ipu->lock, lock_flags); 460 461 val = ipu_cm_read(ipu, IPU_CONF); 462 val &= ~mask; 463 ipu_cm_write(ipu, val, IPU_CONF); 464 465 val = ipu_cm_read(ipu, IPU_DISP_GEN); 466 467 if (mask & IPU_CONF_DI0_EN) 468 val &= ~IPU_DI0_COUNTER_RELEASE; 469 if (mask & IPU_CONF_DI1_EN) 470 val &= ~IPU_DI1_COUNTER_RELEASE; 471 472 ipu_cm_write(ipu, val, IPU_DISP_GEN); 473 474 spin_unlock_irqrestore(&ipu->lock, lock_flags); 475 476 return 0; 477 } 478 EXPORT_SYMBOL_GPL(ipu_module_disable); 479 480 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel) 481 { 482 struct ipu_soc *ipu = channel->ipu; 483 unsigned int chno = channel->num; 484 485 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0; 486 } 487 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer); 488 489 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num) 490 { 491 struct ipu_soc *ipu = channel->ipu; 492 unsigned long flags; 493 u32 reg = 0; 494 495 spin_lock_irqsave(&ipu->lock, flags); 496 switch (buf_num) { 497 case 0: 498 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); 499 break; 500 case 1: 501 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); 502 break; 503 case 2: 504 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); 505 break; 506 } 507 spin_unlock_irqrestore(&ipu->lock, flags); 508 509 return ((reg & idma_mask(channel->num)) != 0); 510 } 511 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready); 512 513 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num) 514 { 515 struct ipu_soc *ipu = channel->ipu; 516 unsigned int chno = channel->num; 517 unsigned long flags; 518 519 spin_lock_irqsave(&ipu->lock, flags); 520 521 /* Mark buffer as ready. */ 522 if (buf_num == 0) 523 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); 524 else 525 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); 526 527 spin_unlock_irqrestore(&ipu->lock, flags); 528 } 529 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer); 530 531 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num) 532 { 533 struct ipu_soc *ipu = channel->ipu; 534 unsigned int chno = channel->num; 535 unsigned long flags; 536 537 spin_lock_irqsave(&ipu->lock, flags); 538 539 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */ 540 switch (buf_num) { 541 case 0: 542 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); 543 break; 544 case 1: 545 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); 546 break; 547 case 2: 548 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno)); 549 break; 550 default: 551 break; 552 } 553 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ 554 555 spin_unlock_irqrestore(&ipu->lock, flags); 556 } 557 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer); 558 559 int ipu_idmac_enable_channel(struct ipuv3_channel *channel) 560 { 561 struct ipu_soc *ipu = channel->ipu; 562 u32 val; 563 unsigned long flags; 564 565 spin_lock_irqsave(&ipu->lock, flags); 566 567 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); 568 val |= idma_mask(channel->num); 569 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); 570 571 spin_unlock_irqrestore(&ipu->lock, flags); 572 573 return 0; 574 } 575 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel); 576 577 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno) 578 { 579 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno)); 580 } 581 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy); 582 583 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms) 584 { 585 struct ipu_soc *ipu = channel->ipu; 586 unsigned long timeout; 587 588 timeout = jiffies + msecs_to_jiffies(ms); 589 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & 590 idma_mask(channel->num)) { 591 if (time_after(jiffies, timeout)) 592 return -ETIMEDOUT; 593 cpu_relax(); 594 } 595 596 return 0; 597 } 598 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy); 599 600 int ipu_idmac_disable_channel(struct ipuv3_channel *channel) 601 { 602 struct ipu_soc *ipu = channel->ipu; 603 u32 val; 604 unsigned long flags; 605 606 spin_lock_irqsave(&ipu->lock, flags); 607 608 /* Disable DMA channel(s) */ 609 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); 610 val &= ~idma_mask(channel->num); 611 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); 612 613 __ipu_idmac_reset_current_buffer(channel); 614 615 /* Set channel buffers NOT to be ready */ 616 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ 617 618 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & 619 idma_mask(channel->num)) { 620 ipu_cm_write(ipu, idma_mask(channel->num), 621 IPU_CHA_BUF0_RDY(channel->num)); 622 } 623 624 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & 625 idma_mask(channel->num)) { 626 ipu_cm_write(ipu, idma_mask(channel->num), 627 IPU_CHA_BUF1_RDY(channel->num)); 628 } 629 630 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ 631 632 /* Reset the double buffer */ 633 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); 634 val &= ~idma_mask(channel->num); 635 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); 636 637 spin_unlock_irqrestore(&ipu->lock, flags); 638 639 return 0; 640 } 641 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel); 642 643 /* 644 * The imx6 rev. D TRM says that enabling the WM feature will increase 645 * a channel's priority. Refer to Table 36-8 Calculated priority value. 646 * The sub-module that is the sink or source for the channel must enable 647 * watermark signal for this to take effect (SMFC_WM for instance). 648 */ 649 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable) 650 { 651 struct ipu_soc *ipu = channel->ipu; 652 unsigned long flags; 653 u32 val; 654 655 spin_lock_irqsave(&ipu->lock, flags); 656 657 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); 658 if (enable) 659 val |= 1 << (channel->num % 32); 660 else 661 val &= ~(1 << (channel->num % 32)); 662 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); 663 664 spin_unlock_irqrestore(&ipu->lock, flags); 665 } 666 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark); 667 668 static int ipu_memory_reset(struct ipu_soc *ipu) 669 { 670 unsigned long timeout; 671 672 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); 673 674 timeout = jiffies + msecs_to_jiffies(1000); 675 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { 676 if (time_after(jiffies, timeout)) 677 return -ETIME; 678 cpu_relax(); 679 } 680 681 return 0; 682 } 683 684 /* 685 * Set the source mux for the given CSI. Selects either parallel or 686 * MIPI CSI2 sources. 687 */ 688 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2) 689 { 690 unsigned long flags; 691 u32 val, mask; 692 693 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE : 694 IPU_CONF_CSI0_DATA_SOURCE; 695 696 spin_lock_irqsave(&ipu->lock, flags); 697 698 val = ipu_cm_read(ipu, IPU_CONF); 699 if (mipi_csi2) 700 val |= mask; 701 else 702 val &= ~mask; 703 ipu_cm_write(ipu, val, IPU_CONF); 704 705 spin_unlock_irqrestore(&ipu->lock, flags); 706 } 707 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux); 708 709 /* 710 * Set the source mux for the IC. Selects either CSI[01] or the VDI. 711 */ 712 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) 713 { 714 unsigned long flags; 715 u32 val; 716 717 spin_lock_irqsave(&ipu->lock, flags); 718 719 val = ipu_cm_read(ipu, IPU_CONF); 720 if (vdi) 721 val |= IPU_CONF_IC_INPUT; 722 else 723 val &= ~IPU_CONF_IC_INPUT; 724 725 if (csi_id == 1) 726 val |= IPU_CONF_CSI_SEL; 727 else 728 val &= ~IPU_CONF_CSI_SEL; 729 730 ipu_cm_write(ipu, val, IPU_CONF); 731 732 spin_unlock_irqrestore(&ipu->lock, flags); 733 } 734 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux); 735 736 737 /* Frame Synchronization Unit Channel Linking */ 738 739 struct fsu_link_reg_info { 740 int chno; 741 u32 reg; 742 u32 mask; 743 u32 val; 744 }; 745 746 struct fsu_link_info { 747 struct fsu_link_reg_info src; 748 struct fsu_link_reg_info sink; 749 }; 750 751 static const struct fsu_link_info fsu_link_info[] = { 752 { 753 .src = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2, 754 FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC }, 755 .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1, 756 FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC }, 757 }, { 758 .src = { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2, 759 FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF }, 760 .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1, 761 FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF }, 762 }, { 763 .src = { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2, 764 FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP }, 765 .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1, 766 FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP }, 767 }, { 768 .src = { IPUV3_CHANNEL_CSI_DIRECT, 0 }, 769 .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1, 770 FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT }, 771 }, 772 }; 773 774 static const struct fsu_link_info *find_fsu_link_info(int src, int sink) 775 { 776 int i; 777 778 for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) { 779 if (src == fsu_link_info[i].src.chno && 780 sink == fsu_link_info[i].sink.chno) 781 return &fsu_link_info[i]; 782 } 783 784 return NULL; 785 } 786 787 /* 788 * Links a source channel to a sink channel in the FSU. 789 */ 790 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch) 791 { 792 const struct fsu_link_info *link; 793 u32 src_reg, sink_reg; 794 unsigned long flags; 795 796 link = find_fsu_link_info(src_ch, sink_ch); 797 if (!link) 798 return -EINVAL; 799 800 spin_lock_irqsave(&ipu->lock, flags); 801 802 if (link->src.mask) { 803 src_reg = ipu_cm_read(ipu, link->src.reg); 804 src_reg &= ~link->src.mask; 805 src_reg |= link->src.val; 806 ipu_cm_write(ipu, src_reg, link->src.reg); 807 } 808 809 if (link->sink.mask) { 810 sink_reg = ipu_cm_read(ipu, link->sink.reg); 811 sink_reg &= ~link->sink.mask; 812 sink_reg |= link->sink.val; 813 ipu_cm_write(ipu, sink_reg, link->sink.reg); 814 } 815 816 spin_unlock_irqrestore(&ipu->lock, flags); 817 return 0; 818 } 819 EXPORT_SYMBOL_GPL(ipu_fsu_link); 820 821 /* 822 * Unlinks source and sink channels in the FSU. 823 */ 824 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch) 825 { 826 const struct fsu_link_info *link; 827 u32 src_reg, sink_reg; 828 unsigned long flags; 829 830 link = find_fsu_link_info(src_ch, sink_ch); 831 if (!link) 832 return -EINVAL; 833 834 spin_lock_irqsave(&ipu->lock, flags); 835 836 if (link->src.mask) { 837 src_reg = ipu_cm_read(ipu, link->src.reg); 838 src_reg &= ~link->src.mask; 839 ipu_cm_write(ipu, src_reg, link->src.reg); 840 } 841 842 if (link->sink.mask) { 843 sink_reg = ipu_cm_read(ipu, link->sink.reg); 844 sink_reg &= ~link->sink.mask; 845 ipu_cm_write(ipu, sink_reg, link->sink.reg); 846 } 847 848 spin_unlock_irqrestore(&ipu->lock, flags); 849 return 0; 850 } 851 EXPORT_SYMBOL_GPL(ipu_fsu_unlink); 852 853 /* Link IDMAC channels in the FSU */ 854 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink) 855 { 856 return ipu_fsu_link(src->ipu, src->num, sink->num); 857 } 858 EXPORT_SYMBOL_GPL(ipu_idmac_link); 859 860 /* Unlink IDMAC channels in the FSU */ 861 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink) 862 { 863 return ipu_fsu_unlink(src->ipu, src->num, sink->num); 864 } 865 EXPORT_SYMBOL_GPL(ipu_idmac_unlink); 866 867 struct ipu_devtype { 868 const char *name; 869 unsigned long cm_ofs; 870 unsigned long cpmem_ofs; 871 unsigned long srm_ofs; 872 unsigned long tpm_ofs; 873 unsigned long csi0_ofs; 874 unsigned long csi1_ofs; 875 unsigned long ic_ofs; 876 unsigned long disp0_ofs; 877 unsigned long disp1_ofs; 878 unsigned long dc_tmpl_ofs; 879 unsigned long vdi_ofs; 880 enum ipuv3_type type; 881 }; 882 883 static struct ipu_devtype ipu_type_imx51 = { 884 .name = "IPUv3EX", 885 .cm_ofs = 0x1e000000, 886 .cpmem_ofs = 0x1f000000, 887 .srm_ofs = 0x1f040000, 888 .tpm_ofs = 0x1f060000, 889 .csi0_ofs = 0x1f030000, 890 .csi1_ofs = 0x1f038000, 891 .ic_ofs = 0x1e020000, 892 .disp0_ofs = 0x1e040000, 893 .disp1_ofs = 0x1e048000, 894 .dc_tmpl_ofs = 0x1f080000, 895 .vdi_ofs = 0x1e068000, 896 .type = IPUV3EX, 897 }; 898 899 static struct ipu_devtype ipu_type_imx53 = { 900 .name = "IPUv3M", 901 .cm_ofs = 0x06000000, 902 .cpmem_ofs = 0x07000000, 903 .srm_ofs = 0x07040000, 904 .tpm_ofs = 0x07060000, 905 .csi0_ofs = 0x07030000, 906 .csi1_ofs = 0x07038000, 907 .ic_ofs = 0x06020000, 908 .disp0_ofs = 0x06040000, 909 .disp1_ofs = 0x06048000, 910 .dc_tmpl_ofs = 0x07080000, 911 .vdi_ofs = 0x06068000, 912 .type = IPUV3M, 913 }; 914 915 static struct ipu_devtype ipu_type_imx6q = { 916 .name = "IPUv3H", 917 .cm_ofs = 0x00200000, 918 .cpmem_ofs = 0x00300000, 919 .srm_ofs = 0x00340000, 920 .tpm_ofs = 0x00360000, 921 .csi0_ofs = 0x00230000, 922 .csi1_ofs = 0x00238000, 923 .ic_ofs = 0x00220000, 924 .disp0_ofs = 0x00240000, 925 .disp1_ofs = 0x00248000, 926 .dc_tmpl_ofs = 0x00380000, 927 .vdi_ofs = 0x00268000, 928 .type = IPUV3H, 929 }; 930 931 static const struct of_device_id imx_ipu_dt_ids[] = { 932 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, }, 933 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, }, 934 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, }, 935 { .compatible = "fsl,imx6qp-ipu", .data = &ipu_type_imx6q, }, 936 { /* sentinel */ } 937 }; 938 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids); 939 940 static int ipu_submodules_init(struct ipu_soc *ipu, 941 struct platform_device *pdev, unsigned long ipu_base, 942 struct clk *ipu_clk) 943 { 944 char *unit; 945 int ret; 946 struct device *dev = &pdev->dev; 947 const struct ipu_devtype *devtype = ipu->devtype; 948 949 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); 950 if (ret) { 951 unit = "cpmem"; 952 goto err_cpmem; 953 } 954 955 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, 956 IPU_CONF_CSI0_EN, ipu_clk); 957 if (ret) { 958 unit = "csi0"; 959 goto err_csi_0; 960 } 961 962 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, 963 IPU_CONF_CSI1_EN, ipu_clk); 964 if (ret) { 965 unit = "csi1"; 966 goto err_csi_1; 967 } 968 969 ret = ipu_ic_init(ipu, dev, 970 ipu_base + devtype->ic_ofs, 971 ipu_base + devtype->tpm_ofs); 972 if (ret) { 973 unit = "ic"; 974 goto err_ic; 975 } 976 977 ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs, 978 IPU_CONF_VDI_EN | IPU_CONF_ISP_EN | 979 IPU_CONF_IC_INPUT); 980 if (ret) { 981 unit = "vdi"; 982 goto err_vdi; 983 } 984 985 ret = ipu_image_convert_init(ipu, dev); 986 if (ret) { 987 unit = "image_convert"; 988 goto err_image_convert; 989 } 990 991 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, 992 IPU_CONF_DI0_EN, ipu_clk); 993 if (ret) { 994 unit = "di0"; 995 goto err_di_0; 996 } 997 998 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, 999 IPU_CONF_DI1_EN, ipu_clk); 1000 if (ret) { 1001 unit = "di1"; 1002 goto err_di_1; 1003 } 1004 1005 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + 1006 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs); 1007 if (ret) { 1008 unit = "dc_template"; 1009 goto err_dc; 1010 } 1011 1012 ret = ipu_dmfc_init(ipu, dev, ipu_base + 1013 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk); 1014 if (ret) { 1015 unit = "dmfc"; 1016 goto err_dmfc; 1017 } 1018 1019 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); 1020 if (ret) { 1021 unit = "dp"; 1022 goto err_dp; 1023 } 1024 1025 ret = ipu_smfc_init(ipu, dev, ipu_base + 1026 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS); 1027 if (ret) { 1028 unit = "smfc"; 1029 goto err_smfc; 1030 } 1031 1032 return 0; 1033 1034 err_smfc: 1035 ipu_dp_exit(ipu); 1036 err_dp: 1037 ipu_dmfc_exit(ipu); 1038 err_dmfc: 1039 ipu_dc_exit(ipu); 1040 err_dc: 1041 ipu_di_exit(ipu, 1); 1042 err_di_1: 1043 ipu_di_exit(ipu, 0); 1044 err_di_0: 1045 ipu_image_convert_exit(ipu); 1046 err_image_convert: 1047 ipu_vdi_exit(ipu); 1048 err_vdi: 1049 ipu_ic_exit(ipu); 1050 err_ic: 1051 ipu_csi_exit(ipu, 1); 1052 err_csi_1: 1053 ipu_csi_exit(ipu, 0); 1054 err_csi_0: 1055 ipu_cpmem_exit(ipu); 1056 err_cpmem: 1057 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret); 1058 return ret; 1059 } 1060 1061 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) 1062 { 1063 unsigned long status; 1064 int i, bit, irq; 1065 1066 for (i = 0; i < num_regs; i++) { 1067 1068 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); 1069 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); 1070 1071 for_each_set_bit(bit, &status, 32) { 1072 irq = irq_linear_revmap(ipu->domain, 1073 regs[i] * 32 + bit); 1074 if (irq) 1075 generic_handle_irq(irq); 1076 } 1077 } 1078 } 1079 1080 static void ipu_irq_handler(struct irq_desc *desc) 1081 { 1082 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); 1083 struct irq_chip *chip = irq_desc_get_chip(desc); 1084 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14}; 1085 1086 chained_irq_enter(chip, desc); 1087 1088 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); 1089 1090 chained_irq_exit(chip, desc); 1091 } 1092 1093 static void ipu_err_irq_handler(struct irq_desc *desc) 1094 { 1095 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); 1096 struct irq_chip *chip = irq_desc_get_chip(desc); 1097 const int int_reg[] = { 4, 5, 8, 9}; 1098 1099 chained_irq_enter(chip, desc); 1100 1101 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); 1102 1103 chained_irq_exit(chip, desc); 1104 } 1105 1106 int ipu_map_irq(struct ipu_soc *ipu, int irq) 1107 { 1108 int virq; 1109 1110 virq = irq_linear_revmap(ipu->domain, irq); 1111 if (!virq) 1112 virq = irq_create_mapping(ipu->domain, irq); 1113 1114 return virq; 1115 } 1116 EXPORT_SYMBOL_GPL(ipu_map_irq); 1117 1118 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, 1119 enum ipu_channel_irq irq_type) 1120 { 1121 return ipu_map_irq(ipu, irq_type + channel->num); 1122 } 1123 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq); 1124 1125 static void ipu_submodules_exit(struct ipu_soc *ipu) 1126 { 1127 ipu_smfc_exit(ipu); 1128 ipu_dp_exit(ipu); 1129 ipu_dmfc_exit(ipu); 1130 ipu_dc_exit(ipu); 1131 ipu_di_exit(ipu, 1); 1132 ipu_di_exit(ipu, 0); 1133 ipu_image_convert_exit(ipu); 1134 ipu_vdi_exit(ipu); 1135 ipu_ic_exit(ipu); 1136 ipu_csi_exit(ipu, 1); 1137 ipu_csi_exit(ipu, 0); 1138 ipu_cpmem_exit(ipu); 1139 } 1140 1141 static int platform_remove_devices_fn(struct device *dev, void *unused) 1142 { 1143 struct platform_device *pdev = to_platform_device(dev); 1144 1145 platform_device_unregister(pdev); 1146 1147 return 0; 1148 } 1149 1150 static void platform_device_unregister_children(struct platform_device *pdev) 1151 { 1152 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn); 1153 } 1154 1155 struct ipu_platform_reg { 1156 struct ipu_client_platformdata pdata; 1157 const char *name; 1158 }; 1159 1160 /* These must be in the order of the corresponding device tree port nodes */ 1161 static struct ipu_platform_reg client_reg[] = { 1162 { 1163 .pdata = { 1164 .csi = 0, 1165 .dma[0] = IPUV3_CHANNEL_CSI0, 1166 .dma[1] = -EINVAL, 1167 }, 1168 .name = "imx-ipuv3-csi", 1169 }, { 1170 .pdata = { 1171 .csi = 1, 1172 .dma[0] = IPUV3_CHANNEL_CSI1, 1173 .dma[1] = -EINVAL, 1174 }, 1175 .name = "imx-ipuv3-csi", 1176 }, { 1177 .pdata = { 1178 .di = 0, 1179 .dc = 5, 1180 .dp = IPU_DP_FLOW_SYNC_BG, 1181 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC, 1182 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC, 1183 }, 1184 .name = "imx-ipuv3-crtc", 1185 }, { 1186 .pdata = { 1187 .di = 1, 1188 .dc = 1, 1189 .dp = -EINVAL, 1190 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC, 1191 .dma[1] = -EINVAL, 1192 }, 1193 .name = "imx-ipuv3-crtc", 1194 }, 1195 }; 1196 1197 static DEFINE_MUTEX(ipu_client_id_mutex); 1198 static int ipu_client_id; 1199 1200 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) 1201 { 1202 struct device *dev = ipu->dev; 1203 unsigned i; 1204 int id, ret; 1205 1206 mutex_lock(&ipu_client_id_mutex); 1207 id = ipu_client_id; 1208 ipu_client_id += ARRAY_SIZE(client_reg); 1209 mutex_unlock(&ipu_client_id_mutex); 1210 1211 for (i = 0; i < ARRAY_SIZE(client_reg); i++) { 1212 struct ipu_platform_reg *reg = &client_reg[i]; 1213 struct platform_device *pdev; 1214 struct device_node *of_node; 1215 1216 /* Associate subdevice with the corresponding port node */ 1217 of_node = of_graph_get_port_by_id(dev->of_node, i); 1218 if (!of_node) { 1219 dev_info(dev, 1220 "no port@%d node in %s, not using %s%d\n", 1221 i, dev->of_node->full_name, 1222 (i / 2) ? "DI" : "CSI", i % 2); 1223 continue; 1224 } 1225 1226 pdev = platform_device_alloc(reg->name, id++); 1227 if (!pdev) { 1228 ret = -ENOMEM; 1229 goto err_register; 1230 } 1231 1232 pdev->dev.parent = dev; 1233 1234 reg->pdata.of_node = of_node; 1235 ret = platform_device_add_data(pdev, ®->pdata, 1236 sizeof(reg->pdata)); 1237 if (!ret) 1238 ret = platform_device_add(pdev); 1239 if (ret) { 1240 platform_device_put(pdev); 1241 goto err_register; 1242 } 1243 } 1244 1245 return 0; 1246 1247 err_register: 1248 platform_device_unregister_children(to_platform_device(dev)); 1249 1250 return ret; 1251 } 1252 1253 1254 static int ipu_irq_init(struct ipu_soc *ipu) 1255 { 1256 struct irq_chip_generic *gc; 1257 struct irq_chip_type *ct; 1258 unsigned long unused[IPU_NUM_IRQS / 32] = { 1259 0x400100d0, 0xffe000fd, 1260 0x400100d0, 0xffe000fd, 1261 0x400100d0, 0xffe000fd, 1262 0x4077ffff, 0xffe7e1fd, 1263 0x23fffffe, 0x8880fff0, 1264 0xf98fe7d0, 0xfff81fff, 1265 0x400100d0, 0xffe000fd, 1266 0x00000000, 1267 }; 1268 int ret, i; 1269 1270 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, 1271 &irq_generic_chip_ops, ipu); 1272 if (!ipu->domain) { 1273 dev_err(ipu->dev, "failed to add irq domain\n"); 1274 return -ENODEV; 1275 } 1276 1277 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", 1278 handle_level_irq, 0, 0, 0); 1279 if (ret < 0) { 1280 dev_err(ipu->dev, "failed to alloc generic irq chips\n"); 1281 irq_domain_remove(ipu->domain); 1282 return ret; 1283 } 1284 1285 /* Mask and clear all interrupts */ 1286 for (i = 0; i < IPU_NUM_IRQS; i += 32) { 1287 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32)); 1288 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32)); 1289 } 1290 1291 for (i = 0; i < IPU_NUM_IRQS; i += 32) { 1292 gc = irq_get_domain_generic_chip(ipu->domain, i); 1293 gc->reg_base = ipu->cm_reg; 1294 gc->unused = unused[i / 32]; 1295 ct = gc->chip_types; 1296 ct->chip.irq_ack = irq_gc_ack_set_bit; 1297 ct->chip.irq_mask = irq_gc_mask_clr_bit; 1298 ct->chip.irq_unmask = irq_gc_mask_set_bit; 1299 ct->regs.ack = IPU_INT_STAT(i / 32); 1300 ct->regs.mask = IPU_INT_CTRL(i / 32); 1301 } 1302 1303 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu); 1304 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler, 1305 ipu); 1306 1307 return 0; 1308 } 1309 1310 static void ipu_irq_exit(struct ipu_soc *ipu) 1311 { 1312 int i, irq; 1313 1314 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL); 1315 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL); 1316 1317 /* TODO: remove irq_domain_generic_chips */ 1318 1319 for (i = 0; i < IPU_NUM_IRQS; i++) { 1320 irq = irq_linear_revmap(ipu->domain, i); 1321 if (irq) 1322 irq_dispose_mapping(irq); 1323 } 1324 1325 irq_domain_remove(ipu->domain); 1326 } 1327 1328 void ipu_dump(struct ipu_soc *ipu) 1329 { 1330 int i; 1331 1332 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", 1333 ipu_cm_read(ipu, IPU_CONF)); 1334 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", 1335 ipu_idmac_read(ipu, IDMAC_CONF)); 1336 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n", 1337 ipu_idmac_read(ipu, IDMAC_CHA_EN(0))); 1338 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n", 1339 ipu_idmac_read(ipu, IDMAC_CHA_EN(32))); 1340 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n", 1341 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0))); 1342 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n", 1343 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32))); 1344 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n", 1345 ipu_idmac_read(ipu, IDMAC_BAND_EN(0))); 1346 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n", 1347 ipu_idmac_read(ipu, IDMAC_BAND_EN(32))); 1348 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", 1349 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0))); 1350 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", 1351 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32))); 1352 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n", 1353 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1)); 1354 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n", 1355 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2)); 1356 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n", 1357 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3)); 1358 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n", 1359 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1)); 1360 for (i = 0; i < 15; i++) 1361 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i, 1362 ipu_cm_read(ipu, IPU_INT_CTRL(i))); 1363 } 1364 EXPORT_SYMBOL_GPL(ipu_dump); 1365 1366 static int ipu_probe(struct platform_device *pdev) 1367 { 1368 struct device_node *np = pdev->dev.of_node; 1369 struct ipu_soc *ipu; 1370 struct resource *res; 1371 unsigned long ipu_base; 1372 int ret, irq_sync, irq_err; 1373 const struct ipu_devtype *devtype; 1374 1375 devtype = of_device_get_match_data(&pdev->dev); 1376 if (!devtype) 1377 return -EINVAL; 1378 1379 irq_sync = platform_get_irq(pdev, 0); 1380 irq_err = platform_get_irq(pdev, 1); 1381 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1382 1383 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n", 1384 irq_sync, irq_err); 1385 1386 if (!res || irq_sync < 0 || irq_err < 0) 1387 return -ENODEV; 1388 1389 ipu_base = res->start; 1390 1391 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); 1392 if (!ipu) 1393 return -ENODEV; 1394 1395 ipu->id = of_alias_get_id(np, "ipu"); 1396 1397 if (of_device_is_compatible(np, "fsl,imx6qp-ipu") && 1398 IS_ENABLED(CONFIG_DRM)) { 1399 ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev, 1400 "fsl,prg", ipu->id); 1401 if (!ipu->prg_priv) 1402 return -EPROBE_DEFER; 1403 } 1404 1405 ipu->devtype = devtype; 1406 ipu->ipu_type = devtype->type; 1407 1408 spin_lock_init(&ipu->lock); 1409 mutex_init(&ipu->channel_lock); 1410 INIT_LIST_HEAD(&ipu->channels); 1411 1412 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n", 1413 ipu_base + devtype->cm_ofs); 1414 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n", 1415 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS); 1416 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n", 1417 ipu_base + devtype->cpmem_ofs); 1418 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n", 1419 ipu_base + devtype->csi0_ofs); 1420 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n", 1421 ipu_base + devtype->csi1_ofs); 1422 dev_dbg(&pdev->dev, "ic: 0x%08lx\n", 1423 ipu_base + devtype->ic_ofs); 1424 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n", 1425 ipu_base + devtype->disp0_ofs); 1426 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n", 1427 ipu_base + devtype->disp1_ofs); 1428 dev_dbg(&pdev->dev, "srm: 0x%08lx\n", 1429 ipu_base + devtype->srm_ofs); 1430 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n", 1431 ipu_base + devtype->tpm_ofs); 1432 dev_dbg(&pdev->dev, "dc: 0x%08lx\n", 1433 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS); 1434 dev_dbg(&pdev->dev, "ic: 0x%08lx\n", 1435 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS); 1436 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n", 1437 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS); 1438 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n", 1439 ipu_base + devtype->vdi_ofs); 1440 1441 ipu->cm_reg = devm_ioremap(&pdev->dev, 1442 ipu_base + devtype->cm_ofs, PAGE_SIZE); 1443 ipu->idmac_reg = devm_ioremap(&pdev->dev, 1444 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS, 1445 PAGE_SIZE); 1446 1447 if (!ipu->cm_reg || !ipu->idmac_reg) 1448 return -ENOMEM; 1449 1450 ipu->clk = devm_clk_get(&pdev->dev, "bus"); 1451 if (IS_ERR(ipu->clk)) { 1452 ret = PTR_ERR(ipu->clk); 1453 dev_err(&pdev->dev, "clk_get failed with %d", ret); 1454 return ret; 1455 } 1456 1457 platform_set_drvdata(pdev, ipu); 1458 1459 ret = clk_prepare_enable(ipu->clk); 1460 if (ret) { 1461 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); 1462 return ret; 1463 } 1464 1465 ipu->dev = &pdev->dev; 1466 ipu->irq_sync = irq_sync; 1467 ipu->irq_err = irq_err; 1468 1469 ret = device_reset(&pdev->dev); 1470 if (ret) { 1471 dev_err(&pdev->dev, "failed to reset: %d\n", ret); 1472 goto out_failed_reset; 1473 } 1474 ret = ipu_memory_reset(ipu); 1475 if (ret) 1476 goto out_failed_reset; 1477 1478 ret = ipu_irq_init(ipu); 1479 if (ret) 1480 goto out_failed_irq; 1481 1482 /* Set MCU_T to divide MCU access window into 2 */ 1483 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), 1484 IPU_DISP_GEN); 1485 1486 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); 1487 if (ret) 1488 goto failed_submodules_init; 1489 1490 ret = ipu_add_client_devices(ipu, ipu_base); 1491 if (ret) { 1492 dev_err(&pdev->dev, "adding client devices failed with %d\n", 1493 ret); 1494 goto failed_add_clients; 1495 } 1496 1497 dev_info(&pdev->dev, "%s probed\n", devtype->name); 1498 1499 return 0; 1500 1501 failed_add_clients: 1502 ipu_submodules_exit(ipu); 1503 failed_submodules_init: 1504 ipu_irq_exit(ipu); 1505 out_failed_irq: 1506 out_failed_reset: 1507 clk_disable_unprepare(ipu->clk); 1508 return ret; 1509 } 1510 1511 static int ipu_remove(struct platform_device *pdev) 1512 { 1513 struct ipu_soc *ipu = platform_get_drvdata(pdev); 1514 1515 platform_device_unregister_children(pdev); 1516 ipu_submodules_exit(ipu); 1517 ipu_irq_exit(ipu); 1518 1519 clk_disable_unprepare(ipu->clk); 1520 1521 return 0; 1522 } 1523 1524 static struct platform_driver imx_ipu_driver = { 1525 .driver = { 1526 .name = "imx-ipuv3", 1527 .of_match_table = imx_ipu_dt_ids, 1528 }, 1529 .probe = ipu_probe, 1530 .remove = ipu_remove, 1531 }; 1532 1533 static struct platform_driver * const drivers[] = { 1534 #if IS_ENABLED(CONFIG_DRM) 1535 &ipu_pre_drv, 1536 &ipu_prg_drv, 1537 #endif 1538 &imx_ipu_driver, 1539 }; 1540 1541 static int __init imx_ipu_init(void) 1542 { 1543 return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 1544 } 1545 module_init(imx_ipu_init); 1546 1547 static void __exit imx_ipu_exit(void) 1548 { 1549 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 1550 } 1551 module_exit(imx_ipu_exit); 1552 1553 MODULE_ALIAS("platform:imx-ipuv3"); 1554 MODULE_DESCRIPTION("i.MX IPU v3 driver"); 1555 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 1556 MODULE_LICENSE("GPL"); 1557