1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Tegra host1x Interrupt Management 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Copyright (c) 2010-2013, NVIDIA Corporation. 7 */ 8 9 #include <linux/interrupt.h> 10 #include <linux/irq.h> 11 #include <linux/io.h> 12 13 #include "../intr.h" 14 #include "../dev.h" 15 16 static irqreturn_t syncpt_thresh_isr(int irq, void *dev_id) 17 { 18 struct host1x *host = dev_id; 19 unsigned long reg; 20 unsigned int i, id; 21 22 for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); i++) { 23 reg = host1x_sync_readl(host, 24 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i)); 25 26 host1x_sync_writel(host, reg, 27 HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i)); 28 host1x_sync_writel(host, reg, 29 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i)); 30 31 for_each_set_bit(id, ®, 32) 32 host1x_intr_handle_interrupt(host, i * 32 + id); 33 } 34 35 return IRQ_HANDLED; 36 } 37 38 static void host1x_intr_disable_all_syncpt_intrs(struct host1x *host) 39 { 40 unsigned int i; 41 42 for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); ++i) { 43 host1x_sync_writel(host, 0xffffffffu, 44 HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i)); 45 host1x_sync_writel(host, 0xffffffffu, 46 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i)); 47 } 48 } 49 50 static void intr_hw_init(struct host1x *host, u32 cpm) 51 { 52 #if HOST1X_HW < 6 53 /* disable the ip_busy_timeout. this prevents write drops */ 54 host1x_sync_writel(host, 0, HOST1X_SYNC_IP_BUSY_TIMEOUT); 55 56 /* 57 * increase the auto-ack timout to the maximum value. 2d will hang 58 * otherwise on Tegra2. 59 */ 60 host1x_sync_writel(host, 0xff, HOST1X_SYNC_CTXSW_TIMEOUT_CFG); 61 62 /* update host clocks per usec */ 63 host1x_sync_writel(host, cpm, HOST1X_SYNC_USEC_CLK); 64 #endif 65 #if HOST1X_HW >= 8 66 u32 id; 67 68 /* 69 * Program threshold interrupt destination among 8 lines per VM, 70 * per syncpoint. For now, just direct all to the first interrupt 71 * line. 72 */ 73 for (id = 0; id < host->info->nb_pts; id++) 74 host1x_sync_writel(host, 0, HOST1X_SYNC_SYNCPT_INTR_DEST(id)); 75 #endif 76 } 77 78 static int 79 host1x_intr_init_host_sync(struct host1x *host, u32 cpm) 80 { 81 int err; 82 83 host1x_hw_intr_disable_all_syncpt_intrs(host); 84 85 err = devm_request_irq(host->dev, host->syncpt_irq, 86 syncpt_thresh_isr, IRQF_SHARED, 87 "host1x_syncpt", host); 88 if (err < 0) 89 return err; 90 91 intr_hw_init(host, cpm); 92 93 return 0; 94 } 95 96 static void host1x_intr_set_syncpt_threshold(struct host1x *host, 97 unsigned int id, 98 u32 thresh) 99 { 100 host1x_sync_writel(host, thresh, HOST1X_SYNC_SYNCPT_INT_THRESH(id)); 101 } 102 103 static void host1x_intr_enable_syncpt_intr(struct host1x *host, 104 unsigned int id) 105 { 106 host1x_sync_writel(host, BIT(id % 32), 107 HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id / 32)); 108 } 109 110 static void host1x_intr_disable_syncpt_intr(struct host1x *host, 111 unsigned int id) 112 { 113 host1x_sync_writel(host, BIT(id % 32), 114 HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id / 32)); 115 host1x_sync_writel(host, BIT(id % 32), 116 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id / 32)); 117 } 118 119 static const struct host1x_intr_ops host1x_intr_ops = { 120 .init_host_sync = host1x_intr_init_host_sync, 121 .set_syncpt_threshold = host1x_intr_set_syncpt_threshold, 122 .enable_syncpt_intr = host1x_intr_enable_syncpt_intr, 123 .disable_syncpt_intr = host1x_intr_disable_syncpt_intr, 124 .disable_all_syncpt_intrs = host1x_intr_disable_all_syncpt_intrs, 125 }; 126