1 /* 2 * Tegra host1x driver 3 * 4 * Copyright (c) 2010-2013, NVIDIA Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/module.h> 24 #include <linux/of_device.h> 25 #include <linux/of.h> 26 #include <linux/slab.h> 27 28 #define CREATE_TRACE_POINTS 29 #include <trace/events/host1x.h> 30 #undef CREATE_TRACE_POINTS 31 32 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 33 #include <asm/dma-iommu.h> 34 #endif 35 36 #include "bus.h" 37 #include "channel.h" 38 #include "debug.h" 39 #include "dev.h" 40 #include "intr.h" 41 42 #include "hw/host1x01.h" 43 #include "hw/host1x02.h" 44 #include "hw/host1x04.h" 45 #include "hw/host1x05.h" 46 #include "hw/host1x06.h" 47 #include "hw/host1x07.h" 48 49 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r) 50 { 51 writel(v, host1x->hv_regs + r); 52 } 53 54 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r) 55 { 56 return readl(host1x->hv_regs + r); 57 } 58 59 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r) 60 { 61 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 62 63 writel(v, sync_regs + r); 64 } 65 66 u32 host1x_sync_readl(struct host1x *host1x, u32 r) 67 { 68 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 69 70 return readl(sync_regs + r); 71 } 72 73 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r) 74 { 75 writel(v, ch->regs + r); 76 } 77 78 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r) 79 { 80 return readl(ch->regs + r); 81 } 82 83 static const struct host1x_info host1x01_info = { 84 .nb_channels = 8, 85 .nb_pts = 32, 86 .nb_mlocks = 16, 87 .nb_bases = 8, 88 .init = host1x01_init, 89 .sync_offset = 0x3000, 90 .dma_mask = DMA_BIT_MASK(32), 91 }; 92 93 static const struct host1x_info host1x02_info = { 94 .nb_channels = 9, 95 .nb_pts = 32, 96 .nb_mlocks = 16, 97 .nb_bases = 12, 98 .init = host1x02_init, 99 .sync_offset = 0x3000, 100 .dma_mask = DMA_BIT_MASK(32), 101 }; 102 103 static const struct host1x_info host1x04_info = { 104 .nb_channels = 12, 105 .nb_pts = 192, 106 .nb_mlocks = 16, 107 .nb_bases = 64, 108 .init = host1x04_init, 109 .sync_offset = 0x2100, 110 .dma_mask = DMA_BIT_MASK(34), 111 }; 112 113 static const struct host1x_info host1x05_info = { 114 .nb_channels = 14, 115 .nb_pts = 192, 116 .nb_mlocks = 16, 117 .nb_bases = 64, 118 .init = host1x05_init, 119 .sync_offset = 0x2100, 120 .dma_mask = DMA_BIT_MASK(34), 121 }; 122 123 static const struct host1x_info host1x06_info = { 124 .nb_channels = 63, 125 .nb_pts = 576, 126 .nb_mlocks = 24, 127 .nb_bases = 16, 128 .init = host1x06_init, 129 .sync_offset = 0x0, 130 .dma_mask = DMA_BIT_MASK(34), 131 .has_hypervisor = true, 132 }; 133 134 static const struct host1x_info host1x07_info = { 135 .nb_channels = 63, 136 .nb_pts = 704, 137 .nb_mlocks = 32, 138 .nb_bases = 0, 139 .init = host1x07_init, 140 .sync_offset = 0x0, 141 .dma_mask = DMA_BIT_MASK(40), 142 .has_hypervisor = true, 143 }; 144 145 static const struct of_device_id host1x_of_match[] = { 146 { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, }, 147 { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, }, 148 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, }, 149 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, }, 150 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, }, 151 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, }, 152 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, }, 153 { }, 154 }; 155 MODULE_DEVICE_TABLE(of, host1x_of_match); 156 157 static int host1x_probe(struct platform_device *pdev) 158 { 159 struct host1x *host; 160 struct resource *regs, *hv_regs = NULL; 161 int syncpt_irq; 162 int err; 163 164 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 165 if (!host) 166 return -ENOMEM; 167 168 host->info = of_device_get_match_data(&pdev->dev); 169 170 if (host->info->has_hypervisor) { 171 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm"); 172 if (!regs) { 173 dev_err(&pdev->dev, "failed to get vm registers\n"); 174 return -ENXIO; 175 } 176 177 hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, 178 "hypervisor"); 179 if (!hv_regs) { 180 dev_err(&pdev->dev, 181 "failed to get hypervisor registers\n"); 182 return -ENXIO; 183 } 184 } else { 185 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 186 if (!regs) { 187 dev_err(&pdev->dev, "failed to get registers\n"); 188 return -ENXIO; 189 } 190 } 191 192 syncpt_irq = platform_get_irq(pdev, 0); 193 if (syncpt_irq < 0) { 194 dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq); 195 return syncpt_irq; 196 } 197 198 mutex_init(&host->devices_lock); 199 INIT_LIST_HEAD(&host->devices); 200 INIT_LIST_HEAD(&host->list); 201 host->dev = &pdev->dev; 202 203 /* set common host1x device data */ 204 platform_set_drvdata(pdev, host); 205 206 host->regs = devm_ioremap_resource(&pdev->dev, regs); 207 if (IS_ERR(host->regs)) 208 return PTR_ERR(host->regs); 209 210 if (host->info->has_hypervisor) { 211 host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs); 212 if (IS_ERR(host->hv_regs)) 213 return PTR_ERR(host->hv_regs); 214 } 215 216 dma_set_mask_and_coherent(host->dev, host->info->dma_mask); 217 218 if (host->info->init) { 219 err = host->info->init(host); 220 if (err) 221 return err; 222 } 223 224 host->clk = devm_clk_get(&pdev->dev, NULL); 225 if (IS_ERR(host->clk)) { 226 dev_err(&pdev->dev, "failed to get clock\n"); 227 err = PTR_ERR(host->clk); 228 return err; 229 } 230 231 host->rst = devm_reset_control_get(&pdev->dev, "host1x"); 232 if (IS_ERR(host->rst)) { 233 err = PTR_ERR(host->rst); 234 dev_err(&pdev->dev, "failed to get reset: %d\n", err); 235 return err; 236 } 237 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 238 if (host->dev->archdata.mapping) { 239 struct dma_iommu_mapping *mapping = 240 to_dma_iommu_mapping(host->dev); 241 arm_iommu_detach_device(host->dev); 242 arm_iommu_release_mapping(mapping); 243 } 244 #endif 245 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL)) 246 goto skip_iommu; 247 248 host->group = iommu_group_get(&pdev->dev); 249 if (host->group) { 250 struct iommu_domain_geometry *geometry; 251 unsigned long order; 252 253 err = iova_cache_get(); 254 if (err < 0) 255 goto put_group; 256 257 host->domain = iommu_domain_alloc(&platform_bus_type); 258 if (!host->domain) { 259 err = -ENOMEM; 260 goto put_cache; 261 } 262 263 err = iommu_attach_group(host->domain, host->group); 264 if (err) { 265 if (err == -ENODEV) { 266 iommu_domain_free(host->domain); 267 host->domain = NULL; 268 iova_cache_put(); 269 iommu_group_put(host->group); 270 host->group = NULL; 271 goto skip_iommu; 272 } 273 274 goto fail_free_domain; 275 } 276 277 geometry = &host->domain->geometry; 278 279 order = __ffs(host->domain->pgsize_bitmap); 280 init_iova_domain(&host->iova, 1UL << order, 281 geometry->aperture_start >> order); 282 host->iova_end = geometry->aperture_end; 283 } 284 285 skip_iommu: 286 err = host1x_channel_list_init(&host->channel_list, 287 host->info->nb_channels); 288 if (err) { 289 dev_err(&pdev->dev, "failed to initialize channel list\n"); 290 goto fail_detach_device; 291 } 292 293 err = clk_prepare_enable(host->clk); 294 if (err < 0) { 295 dev_err(&pdev->dev, "failed to enable clock\n"); 296 goto fail_free_channels; 297 } 298 299 err = reset_control_deassert(host->rst); 300 if (err < 0) { 301 dev_err(&pdev->dev, "failed to deassert reset: %d\n", err); 302 goto fail_unprepare_disable; 303 } 304 305 err = host1x_syncpt_init(host); 306 if (err) { 307 dev_err(&pdev->dev, "failed to initialize syncpts\n"); 308 goto fail_reset_assert; 309 } 310 311 err = host1x_intr_init(host, syncpt_irq); 312 if (err) { 313 dev_err(&pdev->dev, "failed to initialize interrupts\n"); 314 goto fail_deinit_syncpt; 315 } 316 317 host1x_debug_init(host); 318 319 err = host1x_register(host); 320 if (err < 0) 321 goto fail_deinit_intr; 322 323 return 0; 324 325 fail_deinit_intr: 326 host1x_intr_deinit(host); 327 fail_deinit_syncpt: 328 host1x_syncpt_deinit(host); 329 fail_reset_assert: 330 reset_control_assert(host->rst); 331 fail_unprepare_disable: 332 clk_disable_unprepare(host->clk); 333 fail_free_channels: 334 host1x_channel_list_free(&host->channel_list); 335 fail_detach_device: 336 if (host->group && host->domain) { 337 put_iova_domain(&host->iova); 338 iommu_detach_group(host->domain, host->group); 339 } 340 fail_free_domain: 341 if (host->domain) 342 iommu_domain_free(host->domain); 343 put_cache: 344 if (host->group) 345 iova_cache_put(); 346 put_group: 347 iommu_group_put(host->group); 348 349 return err; 350 } 351 352 static int host1x_remove(struct platform_device *pdev) 353 { 354 struct host1x *host = platform_get_drvdata(pdev); 355 356 host1x_unregister(host); 357 host1x_intr_deinit(host); 358 host1x_syncpt_deinit(host); 359 reset_control_assert(host->rst); 360 clk_disable_unprepare(host->clk); 361 362 if (host->domain) { 363 put_iova_domain(&host->iova); 364 iommu_detach_group(host->domain, host->group); 365 iommu_domain_free(host->domain); 366 iova_cache_put(); 367 iommu_group_put(host->group); 368 } 369 370 return 0; 371 } 372 373 static struct platform_driver tegra_host1x_driver = { 374 .driver = { 375 .name = "tegra-host1x", 376 .of_match_table = host1x_of_match, 377 }, 378 .probe = host1x_probe, 379 .remove = host1x_remove, 380 }; 381 382 static struct platform_driver * const drivers[] = { 383 &tegra_host1x_driver, 384 &tegra_mipi_driver, 385 }; 386 387 static int __init tegra_host1x_init(void) 388 { 389 int err; 390 391 err = bus_register(&host1x_bus_type); 392 if (err < 0) 393 return err; 394 395 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 396 if (err < 0) 397 bus_unregister(&host1x_bus_type); 398 399 return err; 400 } 401 module_init(tegra_host1x_init); 402 403 static void __exit tegra_host1x_exit(void) 404 { 405 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 406 bus_unregister(&host1x_bus_type); 407 } 408 module_exit(tegra_host1x_exit); 409 410 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 411 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>"); 412 MODULE_DESCRIPTION("Host1x driver for Tegra products"); 413 MODULE_LICENSE("GPL"); 414