1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Tegra host1x driver 4 * 5 * Copyright (c) 2010-2013, NVIDIA Corporation. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/io.h> 11 #include <linux/list.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/of.h> 15 #include <linux/slab.h> 16 17 #define CREATE_TRACE_POINTS 18 #include <trace/events/host1x.h> 19 #undef CREATE_TRACE_POINTS 20 21 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 22 #include <asm/dma-iommu.h> 23 #endif 24 25 #include "bus.h" 26 #include "channel.h" 27 #include "debug.h" 28 #include "dev.h" 29 #include "intr.h" 30 31 #include "hw/host1x01.h" 32 #include "hw/host1x02.h" 33 #include "hw/host1x04.h" 34 #include "hw/host1x05.h" 35 #include "hw/host1x06.h" 36 #include "hw/host1x07.h" 37 38 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r) 39 { 40 writel(v, host1x->hv_regs + r); 41 } 42 43 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r) 44 { 45 return readl(host1x->hv_regs + r); 46 } 47 48 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r) 49 { 50 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 51 52 writel(v, sync_regs + r); 53 } 54 55 u32 host1x_sync_readl(struct host1x *host1x, u32 r) 56 { 57 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 58 59 return readl(sync_regs + r); 60 } 61 62 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r) 63 { 64 writel(v, ch->regs + r); 65 } 66 67 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r) 68 { 69 return readl(ch->regs + r); 70 } 71 72 static const struct host1x_info host1x01_info = { 73 .nb_channels = 8, 74 .nb_pts = 32, 75 .nb_mlocks = 16, 76 .nb_bases = 8, 77 .init = host1x01_init, 78 .sync_offset = 0x3000, 79 .dma_mask = DMA_BIT_MASK(32), 80 }; 81 82 static const struct host1x_info host1x02_info = { 83 .nb_channels = 9, 84 .nb_pts = 32, 85 .nb_mlocks = 16, 86 .nb_bases = 12, 87 .init = host1x02_init, 88 .sync_offset = 0x3000, 89 .dma_mask = DMA_BIT_MASK(32), 90 }; 91 92 static const struct host1x_info host1x04_info = { 93 .nb_channels = 12, 94 .nb_pts = 192, 95 .nb_mlocks = 16, 96 .nb_bases = 64, 97 .init = host1x04_init, 98 .sync_offset = 0x2100, 99 .dma_mask = DMA_BIT_MASK(34), 100 }; 101 102 static const struct host1x_info host1x05_info = { 103 .nb_channels = 14, 104 .nb_pts = 192, 105 .nb_mlocks = 16, 106 .nb_bases = 64, 107 .init = host1x05_init, 108 .sync_offset = 0x2100, 109 .dma_mask = DMA_BIT_MASK(34), 110 }; 111 112 static const struct host1x_sid_entry tegra186_sid_table[] = { 113 { 114 /* VIC */ 115 .base = 0x1af0, 116 .offset = 0x30, 117 .limit = 0x34 118 }, 119 }; 120 121 static const struct host1x_info host1x06_info = { 122 .nb_channels = 63, 123 .nb_pts = 576, 124 .nb_mlocks = 24, 125 .nb_bases = 16, 126 .init = host1x06_init, 127 .sync_offset = 0x0, 128 .dma_mask = DMA_BIT_MASK(40), 129 .has_hypervisor = true, 130 .num_sid_entries = ARRAY_SIZE(tegra186_sid_table), 131 .sid_table = tegra186_sid_table, 132 }; 133 134 static const struct host1x_sid_entry tegra194_sid_table[] = { 135 { 136 /* VIC */ 137 .base = 0x1af0, 138 .offset = 0x30, 139 .limit = 0x34 140 }, 141 }; 142 143 static const struct host1x_info host1x07_info = { 144 .nb_channels = 63, 145 .nb_pts = 704, 146 .nb_mlocks = 32, 147 .nb_bases = 0, 148 .init = host1x07_init, 149 .sync_offset = 0x0, 150 .dma_mask = DMA_BIT_MASK(40), 151 .has_hypervisor = true, 152 .num_sid_entries = ARRAY_SIZE(tegra194_sid_table), 153 .sid_table = tegra194_sid_table, 154 }; 155 156 static const struct of_device_id host1x_of_match[] = { 157 { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, }, 158 { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, }, 159 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, }, 160 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, }, 161 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, }, 162 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, }, 163 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, }, 164 { }, 165 }; 166 MODULE_DEVICE_TABLE(of, host1x_of_match); 167 168 static void host1x_setup_sid_table(struct host1x *host) 169 { 170 const struct host1x_info *info = host->info; 171 unsigned int i; 172 173 for (i = 0; i < info->num_sid_entries; i++) { 174 const struct host1x_sid_entry *entry = &info->sid_table[i]; 175 176 host1x_hypervisor_writel(host, entry->offset, entry->base); 177 host1x_hypervisor_writel(host, entry->limit, entry->base + 4); 178 } 179 } 180 181 static int host1x_probe(struct platform_device *pdev) 182 { 183 struct host1x *host; 184 struct resource *regs, *hv_regs = NULL; 185 int syncpt_irq; 186 int err; 187 188 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 189 if (!host) 190 return -ENOMEM; 191 192 host->info = of_device_get_match_data(&pdev->dev); 193 194 if (host->info->has_hypervisor) { 195 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm"); 196 if (!regs) { 197 dev_err(&pdev->dev, "failed to get vm registers\n"); 198 return -ENXIO; 199 } 200 201 hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, 202 "hypervisor"); 203 if (!hv_regs) { 204 dev_err(&pdev->dev, 205 "failed to get hypervisor registers\n"); 206 return -ENXIO; 207 } 208 } else { 209 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 210 if (!regs) { 211 dev_err(&pdev->dev, "failed to get registers\n"); 212 return -ENXIO; 213 } 214 } 215 216 syncpt_irq = platform_get_irq(pdev, 0); 217 if (syncpt_irq < 0) { 218 dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq); 219 return syncpt_irq; 220 } 221 222 mutex_init(&host->devices_lock); 223 INIT_LIST_HEAD(&host->devices); 224 INIT_LIST_HEAD(&host->list); 225 host->dev = &pdev->dev; 226 227 /* set common host1x device data */ 228 platform_set_drvdata(pdev, host); 229 230 host->regs = devm_ioremap_resource(&pdev->dev, regs); 231 if (IS_ERR(host->regs)) 232 return PTR_ERR(host->regs); 233 234 if (host->info->has_hypervisor) { 235 host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs); 236 if (IS_ERR(host->hv_regs)) 237 return PTR_ERR(host->hv_regs); 238 } 239 240 dma_set_mask_and_coherent(host->dev, host->info->dma_mask); 241 242 if (host->info->init) { 243 err = host->info->init(host); 244 if (err) 245 return err; 246 } 247 248 host->clk = devm_clk_get(&pdev->dev, NULL); 249 if (IS_ERR(host->clk)) { 250 err = PTR_ERR(host->clk); 251 252 if (err != -EPROBE_DEFER) 253 dev_err(&pdev->dev, "failed to get clock: %d\n", err); 254 255 return err; 256 } 257 258 host->rst = devm_reset_control_get(&pdev->dev, "host1x"); 259 if (IS_ERR(host->rst)) { 260 err = PTR_ERR(host->rst); 261 dev_err(&pdev->dev, "failed to get reset: %d\n", err); 262 return err; 263 } 264 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 265 if (host->dev->archdata.mapping) { 266 struct dma_iommu_mapping *mapping = 267 to_dma_iommu_mapping(host->dev); 268 arm_iommu_detach_device(host->dev); 269 arm_iommu_release_mapping(mapping); 270 } 271 #endif 272 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL)) 273 goto skip_iommu; 274 275 host->group = iommu_group_get(&pdev->dev); 276 if (host->group) { 277 struct iommu_domain_geometry *geometry; 278 u64 mask = dma_get_mask(host->dev); 279 dma_addr_t start, end; 280 unsigned long order; 281 282 err = iova_cache_get(); 283 if (err < 0) 284 goto put_group; 285 286 host->domain = iommu_domain_alloc(&platform_bus_type); 287 if (!host->domain) { 288 err = -ENOMEM; 289 goto put_cache; 290 } 291 292 err = iommu_attach_group(host->domain, host->group); 293 if (err) { 294 if (err == -ENODEV) { 295 iommu_domain_free(host->domain); 296 host->domain = NULL; 297 iova_cache_put(); 298 iommu_group_put(host->group); 299 host->group = NULL; 300 goto skip_iommu; 301 } 302 303 goto fail_free_domain; 304 } 305 306 geometry = &host->domain->geometry; 307 start = geometry->aperture_start & mask; 308 end = geometry->aperture_end & mask; 309 310 order = __ffs(host->domain->pgsize_bitmap); 311 init_iova_domain(&host->iova, 1UL << order, start >> order); 312 host->iova_end = end; 313 } 314 315 skip_iommu: 316 err = host1x_channel_list_init(&host->channel_list, 317 host->info->nb_channels); 318 if (err) { 319 dev_err(&pdev->dev, "failed to initialize channel list\n"); 320 goto fail_detach_device; 321 } 322 323 err = clk_prepare_enable(host->clk); 324 if (err < 0) { 325 dev_err(&pdev->dev, "failed to enable clock\n"); 326 goto fail_free_channels; 327 } 328 329 err = reset_control_deassert(host->rst); 330 if (err < 0) { 331 dev_err(&pdev->dev, "failed to deassert reset: %d\n", err); 332 goto fail_unprepare_disable; 333 } 334 335 err = host1x_syncpt_init(host); 336 if (err) { 337 dev_err(&pdev->dev, "failed to initialize syncpts\n"); 338 goto fail_reset_assert; 339 } 340 341 err = host1x_intr_init(host, syncpt_irq); 342 if (err) { 343 dev_err(&pdev->dev, "failed to initialize interrupts\n"); 344 goto fail_deinit_syncpt; 345 } 346 347 host1x_debug_init(host); 348 349 if (host->info->has_hypervisor) 350 host1x_setup_sid_table(host); 351 352 err = host1x_register(host); 353 if (err < 0) 354 goto fail_deinit_intr; 355 356 return 0; 357 358 fail_deinit_intr: 359 host1x_intr_deinit(host); 360 fail_deinit_syncpt: 361 host1x_syncpt_deinit(host); 362 fail_reset_assert: 363 reset_control_assert(host->rst); 364 fail_unprepare_disable: 365 clk_disable_unprepare(host->clk); 366 fail_free_channels: 367 host1x_channel_list_free(&host->channel_list); 368 fail_detach_device: 369 if (host->group && host->domain) { 370 put_iova_domain(&host->iova); 371 iommu_detach_group(host->domain, host->group); 372 } 373 fail_free_domain: 374 if (host->domain) 375 iommu_domain_free(host->domain); 376 put_cache: 377 if (host->group) 378 iova_cache_put(); 379 put_group: 380 iommu_group_put(host->group); 381 382 return err; 383 } 384 385 static int host1x_remove(struct platform_device *pdev) 386 { 387 struct host1x *host = platform_get_drvdata(pdev); 388 389 host1x_unregister(host); 390 host1x_intr_deinit(host); 391 host1x_syncpt_deinit(host); 392 reset_control_assert(host->rst); 393 clk_disable_unprepare(host->clk); 394 395 if (host->domain) { 396 put_iova_domain(&host->iova); 397 iommu_detach_group(host->domain, host->group); 398 iommu_domain_free(host->domain); 399 iova_cache_put(); 400 iommu_group_put(host->group); 401 } 402 403 return 0; 404 } 405 406 static struct platform_driver tegra_host1x_driver = { 407 .driver = { 408 .name = "tegra-host1x", 409 .of_match_table = host1x_of_match, 410 }, 411 .probe = host1x_probe, 412 .remove = host1x_remove, 413 }; 414 415 static struct platform_driver * const drivers[] = { 416 &tegra_host1x_driver, 417 &tegra_mipi_driver, 418 }; 419 420 static int __init tegra_host1x_init(void) 421 { 422 int err; 423 424 err = bus_register(&host1x_bus_type); 425 if (err < 0) 426 return err; 427 428 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 429 if (err < 0) 430 bus_unregister(&host1x_bus_type); 431 432 return err; 433 } 434 module_init(tegra_host1x_init); 435 436 static void __exit tegra_host1x_exit(void) 437 { 438 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 439 bus_unregister(&host1x_bus_type); 440 } 441 module_exit(tegra_host1x_exit); 442 443 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 444 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>"); 445 MODULE_DESCRIPTION("Host1x driver for Tegra products"); 446 MODULE_LICENSE("GPL"); 447