1 /* 2 * Tegra host1x driver 3 * 4 * Copyright (c) 2010-2013, NVIDIA Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/module.h> 24 #include <linux/of_device.h> 25 #include <linux/of.h> 26 #include <linux/slab.h> 27 28 #define CREATE_TRACE_POINTS 29 #include <trace/events/host1x.h> 30 #undef CREATE_TRACE_POINTS 31 32 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 33 #include <asm/dma-iommu.h> 34 #endif 35 36 #include "bus.h" 37 #include "channel.h" 38 #include "debug.h" 39 #include "dev.h" 40 #include "intr.h" 41 42 #include "hw/host1x01.h" 43 #include "hw/host1x02.h" 44 #include "hw/host1x04.h" 45 #include "hw/host1x05.h" 46 #include "hw/host1x06.h" 47 #include "hw/host1x07.h" 48 49 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r) 50 { 51 writel(v, host1x->hv_regs + r); 52 } 53 54 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r) 55 { 56 return readl(host1x->hv_regs + r); 57 } 58 59 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r) 60 { 61 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 62 63 writel(v, sync_regs + r); 64 } 65 66 u32 host1x_sync_readl(struct host1x *host1x, u32 r) 67 { 68 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 69 70 return readl(sync_regs + r); 71 } 72 73 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r) 74 { 75 writel(v, ch->regs + r); 76 } 77 78 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r) 79 { 80 return readl(ch->regs + r); 81 } 82 83 static const struct host1x_info host1x01_info = { 84 .nb_channels = 8, 85 .nb_pts = 32, 86 .nb_mlocks = 16, 87 .nb_bases = 8, 88 .init = host1x01_init, 89 .sync_offset = 0x3000, 90 .dma_mask = DMA_BIT_MASK(32), 91 }; 92 93 static const struct host1x_info host1x02_info = { 94 .nb_channels = 9, 95 .nb_pts = 32, 96 .nb_mlocks = 16, 97 .nb_bases = 12, 98 .init = host1x02_init, 99 .sync_offset = 0x3000, 100 .dma_mask = DMA_BIT_MASK(32), 101 }; 102 103 static const struct host1x_info host1x04_info = { 104 .nb_channels = 12, 105 .nb_pts = 192, 106 .nb_mlocks = 16, 107 .nb_bases = 64, 108 .init = host1x04_init, 109 .sync_offset = 0x2100, 110 .dma_mask = DMA_BIT_MASK(34), 111 }; 112 113 static const struct host1x_info host1x05_info = { 114 .nb_channels = 14, 115 .nb_pts = 192, 116 .nb_mlocks = 16, 117 .nb_bases = 64, 118 .init = host1x05_init, 119 .sync_offset = 0x2100, 120 .dma_mask = DMA_BIT_MASK(34), 121 }; 122 123 static const struct host1x_sid_entry tegra186_sid_table[] = { 124 { 125 /* VIC */ 126 .base = 0x1af0, 127 .offset = 0x30, 128 .limit = 0x34 129 }, 130 }; 131 132 static const struct host1x_info host1x06_info = { 133 .nb_channels = 63, 134 .nb_pts = 576, 135 .nb_mlocks = 24, 136 .nb_bases = 16, 137 .init = host1x06_init, 138 .sync_offset = 0x0, 139 .dma_mask = DMA_BIT_MASK(40), 140 .has_hypervisor = true, 141 .num_sid_entries = ARRAY_SIZE(tegra186_sid_table), 142 .sid_table = tegra186_sid_table, 143 }; 144 145 static const struct host1x_sid_entry tegra194_sid_table[] = { 146 { 147 /* VIC */ 148 .base = 0x1af0, 149 .offset = 0x30, 150 .limit = 0x34 151 }, 152 }; 153 154 static const struct host1x_info host1x07_info = { 155 .nb_channels = 63, 156 .nb_pts = 704, 157 .nb_mlocks = 32, 158 .nb_bases = 0, 159 .init = host1x07_init, 160 .sync_offset = 0x0, 161 .dma_mask = DMA_BIT_MASK(40), 162 .has_hypervisor = true, 163 .num_sid_entries = ARRAY_SIZE(tegra194_sid_table), 164 .sid_table = tegra194_sid_table, 165 }; 166 167 static const struct of_device_id host1x_of_match[] = { 168 { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, }, 169 { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, }, 170 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, }, 171 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, }, 172 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, }, 173 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, }, 174 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, }, 175 { }, 176 }; 177 MODULE_DEVICE_TABLE(of, host1x_of_match); 178 179 static void host1x_setup_sid_table(struct host1x *host) 180 { 181 const struct host1x_info *info = host->info; 182 unsigned int i; 183 184 for (i = 0; i < info->num_sid_entries; i++) { 185 const struct host1x_sid_entry *entry = &info->sid_table[i]; 186 187 host1x_hypervisor_writel(host, entry->offset, entry->base); 188 host1x_hypervisor_writel(host, entry->limit, entry->base + 4); 189 } 190 } 191 192 static int host1x_probe(struct platform_device *pdev) 193 { 194 struct host1x *host; 195 struct resource *regs, *hv_regs = NULL; 196 int syncpt_irq; 197 int err; 198 199 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 200 if (!host) 201 return -ENOMEM; 202 203 host->info = of_device_get_match_data(&pdev->dev); 204 205 if (host->info->has_hypervisor) { 206 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm"); 207 if (!regs) { 208 dev_err(&pdev->dev, "failed to get vm registers\n"); 209 return -ENXIO; 210 } 211 212 hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, 213 "hypervisor"); 214 if (!hv_regs) { 215 dev_err(&pdev->dev, 216 "failed to get hypervisor registers\n"); 217 return -ENXIO; 218 } 219 } else { 220 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 221 if (!regs) { 222 dev_err(&pdev->dev, "failed to get registers\n"); 223 return -ENXIO; 224 } 225 } 226 227 syncpt_irq = platform_get_irq(pdev, 0); 228 if (syncpt_irq < 0) { 229 dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq); 230 return syncpt_irq; 231 } 232 233 mutex_init(&host->devices_lock); 234 INIT_LIST_HEAD(&host->devices); 235 INIT_LIST_HEAD(&host->list); 236 host->dev = &pdev->dev; 237 238 /* set common host1x device data */ 239 platform_set_drvdata(pdev, host); 240 241 host->regs = devm_ioremap_resource(&pdev->dev, regs); 242 if (IS_ERR(host->regs)) 243 return PTR_ERR(host->regs); 244 245 if (host->info->has_hypervisor) { 246 host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs); 247 if (IS_ERR(host->hv_regs)) 248 return PTR_ERR(host->hv_regs); 249 } 250 251 dma_set_mask_and_coherent(host->dev, host->info->dma_mask); 252 253 if (host->info->init) { 254 err = host->info->init(host); 255 if (err) 256 return err; 257 } 258 259 host->clk = devm_clk_get(&pdev->dev, NULL); 260 if (IS_ERR(host->clk)) { 261 dev_err(&pdev->dev, "failed to get clock\n"); 262 err = PTR_ERR(host->clk); 263 return err; 264 } 265 266 host->rst = devm_reset_control_get(&pdev->dev, "host1x"); 267 if (IS_ERR(host->rst)) { 268 err = PTR_ERR(host->rst); 269 dev_err(&pdev->dev, "failed to get reset: %d\n", err); 270 return err; 271 } 272 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 273 if (host->dev->archdata.mapping) { 274 struct dma_iommu_mapping *mapping = 275 to_dma_iommu_mapping(host->dev); 276 arm_iommu_detach_device(host->dev); 277 arm_iommu_release_mapping(mapping); 278 } 279 #endif 280 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL)) 281 goto skip_iommu; 282 283 host->group = iommu_group_get(&pdev->dev); 284 if (host->group) { 285 struct iommu_domain_geometry *geometry; 286 u64 mask = dma_get_mask(host->dev); 287 dma_addr_t start, end; 288 unsigned long order; 289 290 err = iova_cache_get(); 291 if (err < 0) 292 goto put_group; 293 294 host->domain = iommu_domain_alloc(&platform_bus_type); 295 if (!host->domain) { 296 err = -ENOMEM; 297 goto put_cache; 298 } 299 300 err = iommu_attach_group(host->domain, host->group); 301 if (err) { 302 if (err == -ENODEV) { 303 iommu_domain_free(host->domain); 304 host->domain = NULL; 305 iova_cache_put(); 306 iommu_group_put(host->group); 307 host->group = NULL; 308 goto skip_iommu; 309 } 310 311 goto fail_free_domain; 312 } 313 314 geometry = &host->domain->geometry; 315 start = geometry->aperture_start & mask; 316 end = geometry->aperture_end & mask; 317 318 order = __ffs(host->domain->pgsize_bitmap); 319 init_iova_domain(&host->iova, 1UL << order, start >> order); 320 host->iova_end = end; 321 } 322 323 skip_iommu: 324 err = host1x_channel_list_init(&host->channel_list, 325 host->info->nb_channels); 326 if (err) { 327 dev_err(&pdev->dev, "failed to initialize channel list\n"); 328 goto fail_detach_device; 329 } 330 331 err = clk_prepare_enable(host->clk); 332 if (err < 0) { 333 dev_err(&pdev->dev, "failed to enable clock\n"); 334 goto fail_free_channels; 335 } 336 337 err = reset_control_deassert(host->rst); 338 if (err < 0) { 339 dev_err(&pdev->dev, "failed to deassert reset: %d\n", err); 340 goto fail_unprepare_disable; 341 } 342 343 err = host1x_syncpt_init(host); 344 if (err) { 345 dev_err(&pdev->dev, "failed to initialize syncpts\n"); 346 goto fail_reset_assert; 347 } 348 349 err = host1x_intr_init(host, syncpt_irq); 350 if (err) { 351 dev_err(&pdev->dev, "failed to initialize interrupts\n"); 352 goto fail_deinit_syncpt; 353 } 354 355 host1x_debug_init(host); 356 357 if (host->info->has_hypervisor) 358 host1x_setup_sid_table(host); 359 360 err = host1x_register(host); 361 if (err < 0) 362 goto fail_deinit_intr; 363 364 return 0; 365 366 fail_deinit_intr: 367 host1x_intr_deinit(host); 368 fail_deinit_syncpt: 369 host1x_syncpt_deinit(host); 370 fail_reset_assert: 371 reset_control_assert(host->rst); 372 fail_unprepare_disable: 373 clk_disable_unprepare(host->clk); 374 fail_free_channels: 375 host1x_channel_list_free(&host->channel_list); 376 fail_detach_device: 377 if (host->group && host->domain) { 378 put_iova_domain(&host->iova); 379 iommu_detach_group(host->domain, host->group); 380 } 381 fail_free_domain: 382 if (host->domain) 383 iommu_domain_free(host->domain); 384 put_cache: 385 if (host->group) 386 iova_cache_put(); 387 put_group: 388 iommu_group_put(host->group); 389 390 return err; 391 } 392 393 static int host1x_remove(struct platform_device *pdev) 394 { 395 struct host1x *host = platform_get_drvdata(pdev); 396 397 host1x_unregister(host); 398 host1x_intr_deinit(host); 399 host1x_syncpt_deinit(host); 400 reset_control_assert(host->rst); 401 clk_disable_unprepare(host->clk); 402 403 if (host->domain) { 404 put_iova_domain(&host->iova); 405 iommu_detach_group(host->domain, host->group); 406 iommu_domain_free(host->domain); 407 iova_cache_put(); 408 iommu_group_put(host->group); 409 } 410 411 return 0; 412 } 413 414 static struct platform_driver tegra_host1x_driver = { 415 .driver = { 416 .name = "tegra-host1x", 417 .of_match_table = host1x_of_match, 418 }, 419 .probe = host1x_probe, 420 .remove = host1x_remove, 421 }; 422 423 static struct platform_driver * const drivers[] = { 424 &tegra_host1x_driver, 425 &tegra_mipi_driver, 426 }; 427 428 static int __init tegra_host1x_init(void) 429 { 430 int err; 431 432 err = bus_register(&host1x_bus_type); 433 if (err < 0) 434 return err; 435 436 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 437 if (err < 0) 438 bus_unregister(&host1x_bus_type); 439 440 return err; 441 } 442 module_init(tegra_host1x_init); 443 444 static void __exit tegra_host1x_exit(void) 445 { 446 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 447 bus_unregister(&host1x_bus_type); 448 } 449 module_exit(tegra_host1x_exit); 450 451 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 452 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>"); 453 MODULE_DESCRIPTION("Host1x driver for Tegra products"); 454 MODULE_LICENSE("GPL"); 455